semiconductor memory devices

Abstract

A semiconductor memory device includes an array region and a peripheral region surrounding the array region. The array region includes a plurality of active regions and a first insulating layer located between the active regions. The peripheral region includes a peripheral structure, a second insulating layer surrounding the peripheral structure, and a third insulating layer surrounding the second insulating layer. At least one buried word line extends through the array region and the peripheral region, wherein the portion of the buried word line that cuts through the second insulating layer includes a neck profile, which is the point of highest resistance along the buried word line. When the semiconductor memory device includes multiple buried word lines, the present invention can ensure that the buried word lines have more consistent resistance values and signal delay times.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device including a buried word line. Background Art

[0002] Dynamic random access memory (DRAM) is a type of volatile memory that includes an array area consisting of multiple memory cells and a peripheral area consisting of control circuits. Each memory cell is composed of a transistor and a capacitor electrically connected to the transistor. The transistor controls the storage or release of charge in the capacitor to achieve the purpose of storing data. The control circuit can address each memory cell to control the access of data to each memory cell through word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell.

[0003] In advanced technologies, memory cell structures are evolving towards three-dimensional structures. For example, buried word line (BWL) architectures have been widely adopted to reduce memory cell size and create chips with higher density. However, reducing resistance variations between BWLs to achieve more consistent signal delay times remains a research topic in this field. Summary of the Invention

[0004] The present invention provides a semiconductor memory device in which a buried word line includes a neck profile near the outer edge of a peripheral region, representing the portion of the buried word line with the narrowest line width. By controlling the narrowest line width portion of the buried word line near the outer edge of the peripheral region, the present invention achieves more consistent resistance values and signal delay times across the buried word lines, resulting in optimized performance.

[0005] A semiconductor memory device according to one embodiment of the present invention includes an array region and a peripheral region surrounding the array region. The array region includes a plurality of active regions and a first insulating layer located between the plurality of active regions. The peripheral region includes a peripheral structure, a second insulating layer surrounding the peripheral structure, and a third insulating layer surrounding the second insulating layer. At least one buried word line extends through the array region and the peripheral region, wherein the portion of the buried word line that cuts through the second insulating layer includes a neck profile. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings provide a deeper understanding of these embodiments and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all figures are schematic and relative sizes and proportions have been adjusted for ease of illustration and drawing. The same symbols in different embodiments represent corresponding or similar features.

[0007] Figure 1 FIG2 is a schematic top view of a semiconductor memory device according to an embodiment of the present invention.

[0008] Figure 2 Shown is Figure 1 A partially enlarged top view of a semiconductor memory device.

[0009] Figure 3 The diagram is shown along Figure 2 A schematic cross-sectional view of a section line II' cutting through one of the buried word lines.

[0010] Figure 4 Illustrated is a partially enlarged schematic top view of a semiconductor memory device according to another embodiment of the present invention.

[0011] The description of the accompanying drawings is as follows:

[0012] 10 substrate

[0013] 12 Active region

[0014] 14 First insulation layer

[0015] 14a Part 1

[0016] 14b Part 2

[0017] 16 Surrounding structures

[0018] 16a Inside edge

[0019] 16b Outside edge

[0020] 18 Second insulation layer

[0021] 20 Third insulation layer

[0022] 20a Top surface

[0023] 25 word line groove

[0024] 25a lower part

[0025] 25b Upper

[0026] 30 buried word lines

[0027] 32 Neck Contour

[0028] 34 Insulation cover

[0029] 34a Top surface

[0030] 40 interlayer dielectric layer

[0031] CT word line contact plug

[0032] D1 direction

[0033] D2 direction

[0034] D3 direction

[0035] R1 array area

[0036] R2 surrounding area

[0037] T1 first thickness

[0038] T2 Second thickness

[0039] T3 third thickness

[0040] T4 fourth thickness

[0041] T5 Fifth Thickness

[0042] W1 first line width

[0043] W2 Second line width

[0044] W3 third line width

[0045] W4 fourth line width

[0046] W5 Fifth line width

[0047] I-I' tangent DETAILED DESCRIPTION

[0048] To help those skilled in the art further understand the present invention, the following lists preferred embodiments of the present invention and, together with the accompanying drawings, describes in detail the components and intended effects of the present invention. It should be noted that the features of the following embodiments may be replaced, recombined, or combined to create other embodiments without departing from the spirit of the present invention.

[0049] Please refer to Figure 1 、 Figure 2 and Figure 3 . Figure 1 FIG. 1 is a schematic top view of a semiconductor memory device according to an embodiment of the present invention. Figure 2 for Figure 1 An enlarged top view of the dotted line portion of the semiconductor memory device is shown. Figure 3 To follow Figure 2 A schematic cross-sectional view of a tangent line II' (a tangent line extending along the direction D1) cutting through one of the buried word lines. Figure 3 The interlayer dielectric layer 40 and the insulating cap layer 34 are not shown. Figure 2 In addition, other components of the semiconductor memory device, such as bit lines, storage node contacts, storage node contact pads, and capacitors, are well known in the art and are not described herein to simplify the description.

[0050] like Figure 1 As shown, the semiconductor memory device includes a substrate 10, which includes an array region R1 and a peripheral region R2. Figure 2 and Figure 3 As shown, array region R1 includes a plurality of mutually parallel active regions 12 and a first insulating layer 14 (first portion 14a) located between the active regions 12. The active regions 12 extend along direction D3 and are arranged in an array along directions D2 and D1. Directions D1 and D2 are perpendicular to each other, and direction D3 is different from direction D1 or direction D2. According to one embodiment of the present invention, direction D3 may include an angle between 30 degrees and 75 degrees with direction D2.

[0051] The peripheral region R2 surrounds the array region R1 and may include, from the inside (close to the array region R1) to the outside (away from the array region R1), a peripheral structure 16, a first insulating layer 14 (second portion 14b), a second insulating layer 18, and a third insulating layer 20. According to one embodiment of the present invention, a portion of the active region 12 may be connected to the inner edge 16a of the peripheral structure 16. The first insulating layer 14 (second portion 14b) and the second insulating layer 18 surround the outer edge 16b of the peripheral structure 16, and the peripheral structure 16 and the second insulating layer 18 are separated by the first insulating layer 14 and are not in direct contact. In some embodiments, as Figure 2 As shown, the outer edge 16b of the peripheral structure 16 may include a wavy profile, so the first insulating layer 14 (second portion 14b) and the second insulating layer 18 also have wavy profiles. The third insulating layer 20 surrounds the second insulating layer 18, and the third insulating layer 20 and the first insulating layer 14 (second portion 14b) are separated by the second insulating layer 18 and do not directly contact each other.

[0052] Multiple buried word lines 30 extend along direction D1 through array region R1 and peripheral region R2, and are arranged parallel to direction D2. An insulating capping layer 34 is disposed directly above the buried word lines 30 and extends in the same direction as the buried word lines 30, cutting through the active area 12, the first insulating layer 14, the peripheral structure 16, the second insulating layer 18, and the third insulating layer 20. An interlayer dielectric layer 40 is disposed on the insulating capping layer 34. Word line contact plugs CT are formed in the interlayer dielectric layer 40 and pass through the insulating capping layer 34, directly contacting the ends of the buried word lines 30 that cut through the third insulating layer 20.

[0053] According to one embodiment of the present invention, a method for fabricating an active region 12, peripheral structures 16, a first insulating layer 14, a second insulating layer 18, and a third insulating layer 20 of a semiconductor memory device may include the following steps. First, a substrate 10 is provided, such as, but not limited to, a silicon (Si) substrate, an epitaxial silicon substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate. Next, a patterning process (e.g., a lithography-etching process, a double patterning process, a multiple patterning process, or a spacer pattern transfer process) is performed to form isolation trenches (not shown) in the substrate 10. The isolation trenches define the pattern of the active region 12 and peripheral structures 16 in the substrate 10, and also separate the array region R1 from the peripheral region R2. Next, an oxidation process (e.g., a thermal oxidation process or an in-situ steam oxidation process) may be performed to oxidize a portion of the substrate 10, thereby forming the first insulating layer 14 along the bottom and sidewalls of the isolation trenches. The first insulating layer 14 is made of silicon monoxide (SiO x) layer. The thickness of the first insulating layer 14 can be controlled by controlling the oxidation time, so that the first insulating layer 14 (first portion 14a) formed in the array region R1 can completely fill the isolation trenches in the array region R1, and the first insulating layer 14 (second portion 14b) formed in the peripheral region R2 conformally covers the sidewalls (i.e., the outer edge 16b of the peripheral structure 16) and bottom surface of the isolation trench outside the peripheral structure 16, without filling the isolation trench outside the peripheral structure 16. In some embodiments, a deposition process with excellent gap filling capability (such as an atomic layer deposition process) can be selected to form the first insulating layer 14 to fill the isolation trenches in the array region R1. Next, a deposition process (such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process) can be performed to fully form the second insulating layer 18 and the third insulating layer 20 on the first insulating layer 14, so that the third insulating layer 20 fills the isolation trenches outside the peripheral structure 16. The second insulating layer 18 and the third insulating layer 20 can each include an insulating material. In some embodiments, the second insulating layer 18 preferably includes silicon nitride (SiN), which can reduce the phenomenon of edge divots occurring in the first insulating layer 14 (second portion 14b) sandwiched between the second insulating layer 18 and the surrounding structure 16. The third insulating layer 20 is the main filling material of the isolation trench outside the surrounding structure 16, and can include silicon oxide (SiO x ) or a low-k dielectric material. Next, a planarization process (e.g., a chemical mechanical polishing process) is performed on the third insulating layer 20, the second insulating layer 18, and the first insulating layer 14 to remove excess third insulating layer 20, second insulating layer 18, and first insulating layer 14 until the top surfaces of the active area 12 and the surrounding structures 16 are exposed. After the planarization process, the top surfaces of the third insulating layer 20, the second insulating layer 18, the first insulating layer 14, the active area 12, and the surrounding structures 16 may be substantially flush.

[0054] According to one embodiment of the present invention, a method for fabricating a buried wordline 30, an insulating cap layer 34, an interlayer dielectric layer 40, and a wordline contact plug CT of a semiconductor memory device may include the following steps. After completing a planarization process for the third insulating layer 20, the second insulating layer 18, and the first insulating layer 14, the substrate 10 is subjected to another patterning process to form a wordline trench 25 in the substrate 10 that cuts through the active area 12, the first insulating layer 14, the surrounding structure 16, the second insulating layer 18, and the third insulating layer 20 along a direction D1. Subsequently, an oxidation process or a deposition process may be performed to form a gate dielectric layer (not shown) and a conductive material (not shown) within the wordline trench 25, so that the conductive material completely fills the wordline trench 25. The gate dielectric layer may include an insulating material such as silicon oxide, silicon nitride, or a high-k dielectric material. The conductive material may include a metal such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds or alloys thereof, but is not limited thereto. A planarization process may then be performed to remove excess gate dielectric layer and conductive material outside the wordline trench 25. The conductive material is then etched back until the conductive material only fills the lower portion 25a of the wordline trench 25, thereby forming a buried wordline 30. A deposition process may then be performed to form an insulating material on the substrate 10, covering the buried wordline 30 and filling the wordline trench 25. A planarization process may then be performed to remove excess insulating material outside the wordline trench 25, thereby forming an insulating capping layer 34 filling the upper portion 25b of the wordline trench 25. The insulating capping layer 34 may include an insulating material such as, but is not limited to, silicon oxide (SiOx) or silicon nitride (SiN). The top surface 34a of the insulating capping layer 34 may be flush with the top surface 20a of the third insulating layer 20. After the insulating cap layer 34 is completed, a plurality of bit lines (not shown) can be formed on the substrate 10. These bit lines can extend along direction D2 and be arranged parallel to direction D1. Next, a deposition process can be performed to form an interlayer dielectric layer 40 on the substrate 10, so that the interlayer dielectric layer 40 fills the gaps between the bit lines. Conventional semiconductor manufacturing methods such as patterning, etching, deposition, and planarization are then used to form word line contact plugs CT that penetrate through the interlayer dielectric layer 40 and the insulating cap layer 34 to contact the ends of the buried word lines 30, as well as storage node contacts (not shown) that penetrate through the interlayer dielectric layer 40 to contact the ends of the active regions 12. The interlayer dielectric layer 40 may comprise an insulating material such as, but not limited to, silicon oxide or silicon nitride. The word line contact plugs CT may comprise a metal such as, but not limited to, tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds or alloys thereof.

[0055] In the above manufacturing process, since the etching step for forming the word line trench 25 has different etching behaviors for different materials (such as silicon, silicon oxide and silicon nitride), the portions of the word line trench 25 that cut through different materials may have different widths and depths, resulting in the buried word lines 30 in the word line trench 25 having different line widths and thicknesses. Figure 2 and Figure 3 As shown, the portion of the buried word line 30 that cuts through the active area 12 may include a first line width W1 and a first thickness T1, the portion that cuts through the surrounding structure 16 may include a second line width W2 and a second thickness T2, the portion that cuts through the second insulating layer 18 may include a third line width W3 and a third thickness T3, the portion that cuts through the first insulating layer 14 (first portion 14a) of the array region R1 may include a fourth line width W4 and a fourth thickness T4, and the portion that cuts through the third insulating layer 20 may include a fifth line width W5 and a fifth thickness T5. According to one embodiment of the present invention, by selecting the materials of the active area 12, the surrounding structure 16, the first insulating layer 14, the second insulating layer 18, and the third insulating layer 20, for example, selecting the active area 12 and the surrounding structure 16 to include the same material as the substrate 10 (e.g., silicon), and the first insulating layer 14 to include silicon oxide (SiO x ), the second insulating layer 18 includes silicon nitride (SiN), and the third insulating layer 20 includes silicon oxide (SiO x ), the first line width W1 and the second line width W2 of the buried word line 30 can be substantially equal, and the second thickness T2 is greater than the first thickness T1. The fourth line width W4 and the fifth line width W5 can be substantially equal, and the fourth line width W4 and the fifth line width W5 can be greater than or equal to the first line width W1 and the second line width W2, and the fourth thickness T4 is greater than the first thickness T1 and the second thickness T2. In some embodiments, the parameters of the etching step of the word line trench 25 can be further adjusted so that the portions of the word line trench 25 that cut through the first insulating layer 14 and the active area 12 have substantially equal widths, that is, the first line width W1 and the fourth line width W4 can be substantially equal. Thereby, as Figure 2As shown, the portion of the buried word line 30 that cuts through the array region R1 may have a substantially straight edge. Notably, the portion of the buried word line 30 that cuts through the second insulating layer 18 may have a neck profile 32 and a minimum line width. That is, the third line width W3 may be smaller than any of the first line width W1, the second line width W2, the fourth line width W4, and the fifth line width W5. Furthermore, the portion with the neck profile 32 may have a third thickness T3. The third thickness T3 and the fifth thickness T5 may be substantially equal, greater than the first thickness T1 and the second thickness T2, and less than the fourth thickness T4. The portion with the neck profile 32 is the point where the buried word line 30 has the smallest line width and, therefore, the highest resistance value along the buried word line 30. In other words, the present invention can control the highest resistance value of each buried word line 30 to be formed at the portion where it cuts through the second insulating layer 18 (i.e., the portion with the neck profile 32), rather than randomly forming it at other portions of the buried word line 30. Furthermore, the isolation trenches in the array region R1 of the present invention are completely filled with the first insulating layer 14 (first portion 14 a ), so the second insulating layer 18 is not formed in the array region R1 , thereby preventing the buried word lines 30 in the array region R1 from being narrowed in width.

[0056] Please refer to Figure 4 , depicted is a partially enlarged top view schematic diagram of a semiconductor memory device according to another embodiment of the present invention. To meet the specifications of the buried word line 30, the parameters of the etching step for the word line trench 25 can be adjusted so that the portions of the word line trench 25 that cut through the first insulating layer 14 and the active area 12 have different widths. For example, the fourth line width W4 can be made larger than the first line width W1, thereby allowing the portion of the buried word line 30 that cuts through the array region R1 to have a wavy edge.

[0057] In summary, the semiconductor memory device provided by the present invention employs a second insulating layer disposed along the outer side of the surrounding structure. This allows the highest resistance of each buried word line to be located at the portion that cuts through the second insulating layer (i.e., the neck contour), rather than randomly forming at other portions of the buried word line. This results in more consistent resistance and signal delay time across the buried word lines, resulting in optimized performance.

[0058] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A semiconductor memory device, characterized in that: include: an array region comprising a plurality of active regions, and a first portion of a first insulating layer located between the plurality of active regions; A peripheral area surrounding the array area includes: - surrounding structures; a second insulating layer surrounding the peripheral structure; and a second portion of the first insulating layer disposed between the surrounding structure and the second insulating layer, wherein the surrounding structure and the second insulating layer are separated by the second portion of the first insulating layer; a third insulating layer surrounding the second insulating layer; and At least one buried word line extends through the active area, the first portion of the first insulating layer, the second insulating layer, and the second portion of the first insulating layer. From a plan view, the portion of the buried word line that cuts through the second insulating layer includes a neck profile.

2. The semiconductor memory device according to claim 1, wherein The portion of the buried word line that cuts through the multiple active areas includes a first line width, the portion of the buried word line that cuts through the surrounding structure includes a second line width, and the neck profile includes a third line width, wherein the third line width is smaller than the first line width and the second line width.

3. The semiconductor memory device according to claim 2, wherein The first line width is equal to the second line width.

4. The semiconductor memory device according to claim 2, wherein The first portion of the buried word line that cuts through the first insulating layer includes a fourth line width, and the portion of the buried word line that cuts through the third insulating layer includes a fifth line width, wherein the fourth line width and the fifth line width are greater than or equal to the first line width and the second line width.

5. The semiconductor memory device according to claim 4, wherein The fourth line width is equal to the fifth line width.

6. The semiconductor memory device according to claim 1, wherein The surrounding structure and the second insulating layer are separated by a second portion of the first insulating layer and are not in direct contact with each other.

7. The semiconductor memory device according to claim 6, wherein The second portion of the first insulating layer is separated from the third insulating layer by the second insulating layer and is not in direct contact with the third insulating layer.

8. The semiconductor memory device according to claim 1, wherein The first portion of the first insulating layer, the second portion of the first insulating layer, and the third insulating layer include silicon oxide, and the second insulating layer includes silicon nitride.

9. The semiconductor memory device according to claim 1, wherein The portion of the buried word line that cuts through the multiple active areas includes a first thickness, the portion of the buried word line that cuts through the surrounding structure includes a second thickness, and the portion of the buried word line that cuts through the second insulating layer includes a third thickness, wherein the third thickness is greater than the first thickness and the second thickness.

10. The semiconductor memory device according to claim 9, wherein The second thickness is greater than the first thickness.

11. The semiconductor memory device according to claim 9, wherein A first portion of the buried word line that cuts through the first insulating layer includes a fourth thickness, and the fourth thickness is greater than the first thickness, the second thickness, and the third thickness.

12. The semiconductor memory device according to claim 9, wherein The portion of the buried word line that cuts through the third insulating layer includes a fifth thickness, and the fifth thickness is equal to the third thickness.

13. The semiconductor memory device according to claim 1, wherein An insulating cap layer is further included on the buried word line, wherein a top surface of the insulating cap layer is flush with a top surface of the third insulating layer.

14. The semiconductor memory device according to claim 1, wherein The second insulating layer surrounding the peripheral structure includes a wavy profile.

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