Anti-punch-through logic circuit

Abstract

This invention relates to a punch-through protection logic circuit, belonging to the field of analog integrated circuit technology. The circuit consists of a high-voltage side punch-through protection circuit and a low-voltage side punch-through protection circuit. The output signal NG of the low-voltage side punch-through protection circuit is transmitted in real-time to the gate of MN1 in the high-voltage side punch-through protection circuit, while the output signal PG of the high-voltage side punch-through protection circuit is transmitted in real-time to the gate of MP3 in the low-voltage side punch-through protection circuit. Only when the low-voltage side output signal is low and the high-side input HIN is low can point A be pulled high, causing the subsequent NAND gate output to be low, thus making the high-voltage side output signal low. Similarly, in a symmetrical structure, only when the high-voltage side output signal is high can point B be pulled low when the LIN input is high, causing the subsequent NOR gate output to be high, thus making the low-voltage side output signal high. This invention, through improvements in the design of the punch-through protection logic circuit, reduces circuit complexity, improves reliability, and effectively prevents power transistor punch-through.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits and relates to an anti-punch-through logic circuit. Background Art

[0002] In analog integrated circuits, the power switch tube of the power stage gate drive circuit is one of the core circuits of chips such as power conversion and motor drive; other functional modules also need to amplify the control signal to drive the subsequent transistors. The characteristics of the drive circuit directly affect the safety, reliability and performance indicators of the switching power supply.

[0003] In the switching power supply circuit using synchronous rectification technology, in order to ensure that the upper and lower tubes are not turned on at the same time to avoid damage to the circuit caused by penetration, it is necessary to set a dead time during the switching process to protect the safe operation of the circuit; in the non-power stage drive, in order to ensure the normal switching of the subsequent circuit, it is still necessary to ensure that the upper and lower tubes of the charge and discharge drive stage are not turned on at the same time, and dead time is also required. The traditional circuit to prevent the upper and lower tubes from penetrating through requires a level converter to transfer the gate signal of the low-voltage domain power tube to the high-voltage domain anti-penetration logic circuit, and at the same time, it is necessary to transfer the gate signal of the high-voltage domain power tube to the low-voltage domain anti-penetration logic circuit. This places high requirements on the speed and delay matching of the two level converters, which inevitably increases the complexity and power loss of the drive circuit.

[0004] In order to minimize the impact of the speed and delay matching of the two level converters on the circuit performance, it is necessary to improve the design of the anti-punch-through logic circuit and remove the level conversion circuit to reduce the complexity of the circuit and improve reliability. Summary of the invention

[0005] In view of this, an object of the present invention is to provide an anti-punch-through logic circuit structure to reduce circuit complexity and avoid circuit punch-through.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] An anti-punch-through logic circuit is divided into a high-voltage side anti-punch-through circuit and a low-voltage side anti-punch-through circuit. The output signal NG of the low-voltage side anti-punch-through circuit is transmitted to the high-voltage side anti-punch-through circuit in real time, and the output signal PG of the high-voltage side anti-punch-through circuit is transmitted to the low-voltage side anti-punch-through circuit in real time.

[0008] Optionally, the high-voltage side anti-punch-through circuit includes field effect transistors MP1, MP2, MN1, a resistor R1, a Zener transistor D1, inverters INV1, INV2, INV3, and a NAND gate NAND1; wherein one end of the resistor R1 is connected to the power supply VDD, and the other end is connected to the source of the field effect transistor MP1, the gate of the field effect transistor MP1 is connected to the control signal HIN, the drain of the field effect transistor MP1 is connected to the source of the field effect transistor MP2, the gate of the field effect transistor MP2 is connected to the relative power rail RAIL_H, the drain of the field effect transistor MP2 is connected to the drain of the field effect transistor MN1, the source of the field effect transistor MN1 is grounded, and the gate of the field effect transistor MN1 is connected to the low-voltage side anti-punch-through circuit. The negative electrode of the Zener tube D1 is connected to the power supply VDD, and the positive electrode is connected to the first input terminal of the NAND gate NAND1, wherein the intersection of the first input terminal of the NAND gate NAND1 and the connecting line of the drain of the field effect tube MP1 and the source of the field effect tube MP2 is defined as point A, the input terminal of the inverter INV1 is connected to the control signal HIN, the output terminal of the inverter INV1 is connected to the second input terminal of the NAND gate NAND1, the output terminal of the NAND gate NAND1 is connected to the input terminal of the inverter INV2, the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3, and the output terminal of the inverter INV3 outputs the output signal PG of the high-voltage side anti-punch-through circuit.

[0009] Optionally, the low-voltage side anti-punch-through circuit includes field effect transistors MP3, MN2, MN3, resistor R2, Zener transistor D2, inverters INV4, INV5, INV6, and NOR gate NOR1; wherein one end of the resistor R2 is grounded, and the other end is connected to the source of the field effect transistor MN3, the gate of the field effect transistor MN3 is connected to the control signal LIN, the drain of the field effect transistor MN3 is connected to the source of the field effect transistor MN2, the gate of the field effect transistor MN2 is connected to the relative power rail RAIL_L, the drain of the field effect transistor MN2 is connected to the drain of the field effect transistor MP3, the source of the field effect transistor MP3 is connected to the power supply VDD, and the gate of the field effect transistor MP3 is connected to the high voltage The negative electrode of the Zener tube D2 is connected to the first input terminal of the NOR gate NOR1, wherein the intersection of the first input terminal of the NOR gate NOR1 and the connection line of the source of the field effect tube MN2 and the drain of the field effect tube MN3 is defined as point B, the positive electrode of the Zener tube D2 is grounded, the input terminal of the inverter INV4 is connected to the control signal LIN, the output terminal of the inverter INV4 is connected to the second input terminal of the NOR gate NOR1, the output terminal of the NOR gate NOR1 is connected to the input terminal of the inverter INV5, the output terminal of the inverter INV5 is connected to the input terminal of the inverter INV6, and the output terminal of the inverter INV6 outputs the output signal NG of the low-voltage side anti-punch-through circuit.

[0010] Optionally, the condition for the high-voltage side anti-punch-through circuit to output a low level is: the output signal NG of the low-voltage side anti-punch-through circuit is a low level, the control signal HIN is a low level, and the potential at point A is a high level, so that the output of the NAND gate NAND1 is a low level.

[0011] Optionally, the condition for the low-voltage side anti-punch-through circuit to output a high level is: the output signal PG of the high-voltage side anti-punch-through circuit is high, the control signal LIN is high, and the potential at point B is low, so that the output of the NOR gate NOR1 is high.

[0012] By transmitting the output signal NG of the low-voltage side anti-punch-through circuit to the gate of MN1 in the high-voltage side anti-punch-through circuit in real time, only when the output signal of the low-voltage side anti-punch-through circuit is at a low level, the pull-down path of the high-voltage side anti-punch-through circuit is closed, and the control signal HIN input to the high-voltage side anti-punch-through circuit is at a low level to pull point A high, so that the subsequent NAND gate output is at a low level, and the output signal of the high-voltage side anti-punch-through circuit is at a low level, and the output signal of the high-voltage side anti-punch-through circuit continues to be transmitted backward to the gate of the power tube connected to the high-voltage side anti-punch-through circuit, and turns on the power tube.

[0013] The same symmetrical structure transmits the output signal PG of the high-voltage side anti-punch-through circuit to the gate of MP3 in the low-voltage side anti-punch-through circuit in real time. When the output signal of the high-voltage side anti-punch-through circuit is low, MP3 is turned on to pull up point B, the subsequent NOR gate outputs a low level, and the output signal NG of the low-voltage side anti-punch-through circuit is low, so that the power tube connected to the low-voltage side anti-punch-through circuit is turned off, thus ensuring that the power tubes of the high-voltage and low-voltage side anti-punch-through circuits cannot be turned on at the same time to prevent the occurrence of punch-through. To turn on the power tube of the low-voltage side anti-punch-through circuit, only when the power tube of the high-voltage side anti-punch-through circuit is turned off, that is, the output signal PG of the high-voltage side anti-punch-through circuit is high, the gate of MP3 is high, and the pull-up path of the low-voltage side anti-punch-through circuit is turned off, can the B point be pulled down when the LIN input is high, the subsequent NOR gate outputs a high level, the output signal NG of the low-voltage side anti-punch-through circuit is high, and is transmitted to the gate of the power tube connected to the low-voltage side anti-punch-through circuit to turn on the power tube connected to the low-voltage side anti-punch-through circuit.

[0014] The beneficial effects of the present invention are as follows: the present invention adopts an anti-punch-through logic circuit to transmit the output signal of the anti-punch-through circuit on the low-voltage side to the anti-punch-through circuit on the high-voltage side in real time, and at the same time transmits the output signal of the anti-punch-through circuit on the high-voltage side to the anti-punch-through circuit on the low-voltage side in real time and generates a drive signal together with a logic control signal for actually controlling the subsequent power tube switch, and then controls the switch of the power tube through a drive chain, effectively preventing the power tube from punching through, avoiding problems such as power loss, and enabling the power tube to achieve reliable switching action. At the same time, the level conversion circuit is removed, the complexity of the circuit is reduced, and the reliability is improved.

[0015] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0017] Figure 1 To prevent punch-through logic circuit schematic;

[0018] Figure 2 This is a basic timing logic diagram. DETAILED DESCRIPTION

[0019] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0020] like Figure 1As shown, VDD in the circuit is the power supply voltage, GND is the power ground, RAIL_H is a relative power rail with a certain value lower than the power supply voltage VDD, and RAIL_L is a relative power rail with a certain value higher than GND. These two power rails must ensure that MP2 and MN2 in the anti-punch-through structure remain in the on state, HIN is the control signal for controlling the power tube switch connected to the high-voltage side anti-punch-through circuit, LIN is the control signal for controlling the power tube switch connected to the low-voltage side anti-punch-through circuit, PG is the output signal of the high-voltage side anti-punch-through circuit, which is output to the gate of the high-voltage side power tube, and NG is the output signal of the low-voltage side anti-punch-through circuit, which is output to the gate of the low-voltage side power tube. Zener tube D1 clamps point A so that it will not be too low to protect MP1, so MP1 can use a low-voltage 5V MOS tube to increase the speed, and the high voltage is resisted by MN1 and MP2. When MP1, MP2 and MN1 are all turned on, the voltage at point A is determined by resistor R1. It is necessary to keep point A at a low level relative to the subsequent NAND gate input. Point A can only be pulled high when the pull-down path MN1 is turned off. Similarly, Zener D2 clamps point B so that it will not be too low, protecting MN3. Therefore, MN3 can use a low-voltage 5V MOS tube to increase the speed, and the high voltage is resisted by MP3 and MN2. When MP3, MN2 and MN3 are all turned on, the voltage at point B is determined by resistor R2. It is necessary to keep point B at a high level relative to the subsequent NOR gate input. Only when the pull-up path MP3 is turned off can point B be pulled down.

[0021] When the low-voltage side power tube is to be turned on, LIN needs to be high and point B needs to be low. If PG is low at this time, the high-voltage side power tube is not turned off, and MP3 and MN2 are not turned off. In order to prevent the power stage MOS from punching through, the gate logic of the low-voltage side power tube needs to be low at this time, that is, point B is high. Therefore, the voltage at point B should be higher than the high-to-low flip point of the subsequent NOR gate NOR1, so that the NOR gate will not flip. At this time, MP3, MN2, and MN3 are all turned on. The voltage at point B is determined by the resistance value of resistor R2. The value of R2 is small, and a large current is required to make point B high, but it must be lower than RAIL_L. Once the high-voltage side power tube is turned off and PG is high, MP3 is turned off at this time, and the pull-up path at point B is turned off. Only when LIN is high can MN3 be turned on to pull down point B, so that the input of the NOR gate NOR1 is all low and the output is high. After two inverters INV5 and INV6 with gradually enhanced driving capabilities, the low-voltage side power tube is turned on and NG flips high. The dead time of this process is the time it takes for point B to be pulled down by resistor R2. Figure 2 shown.

[0022] When the high-side power stage is turned on, HIN needs to be low and point A needs to be high. If NG is high at this time, the low-voltage side power tube is not turned off, and MP2 and MN1 are not turned off. In order to prevent the power stage MOS from punching through, the gate logic of the high-voltage side power tube needs to be high at this time, that is, point A is low, so the voltage at point A should be lower than the low-to-high flip point of the subsequent NAND gate NAND1, so as not to flip the NAND gate. At this time, MP1, MP2, and MN1 are all turned on, and the voltage at point A is determined by the resistance value of resistor R1. The value of R1 is small, and a large current is required to make point A low, but it must be higher than RAIL_H. Once the low-voltage side power tube is turned off and NG is low, MN1 is turned off at this time, and the pull-down path at point A is turned off. Only when HIN is low can MP1 be turned on to pull point A high, so that the inputs of the NAND gate NOR1 are all high and the output is low. After two inverters INV2 and INV3 with gradually enhanced driving capabilities, the high-voltage side power tube is turned on and PG flips low. The dead time of this process is the time it takes for point A to be pulled high by resistor R1. Figure 2 shown.

[0023] Through the above analysis of the anti-punch-through driving switching process, it can be seen that the anti-punch-through logic circuit effectively prevents the upper and lower power tubes from being turned on at the same time, avoiding power loss and other problems, so that the power tube or driver tube can achieve reliable switching action.

[0024] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. An anti-punch-through logic circuit, characterized in that: It is divided into a high-voltage side anti-punch-through circuit and a low-voltage side anti-punch-through circuit. The output signal NG of the low-voltage side anti-punch-through circuit is transmitted to the high-voltage side anti-punch-through circuit in real time. At the same time, the output signal PG of the high-voltage side anti-punch-through circuit is transmitted to the low-voltage side anti-punch-through circuit in real time. When the output signal NG of the low-voltage side anti-punch-through circuit is at a low level, and the control signal input to the high-voltage side anti-punch-through circuit is at a low level, the output signal PG of the high-voltage side anti-punch-through circuit is at a low level, and the output signal PG turns on the power tube subsequently connected to the high-voltage side anti-punch-through circuit; the low-level output signal PG is input to the low-voltage side anti-punch-through circuit, so that the output signal NG of the low-voltage side anti-punch-through circuit remains at a low level, so that the power tube subsequently connected to the low-voltage side anti-punch-through circuit is turned off, thereby ensuring that the power tubes respectively connected to the high- and low-voltage side anti-punch-through circuits cannot be turned on at the same time, thereby preventing the occurrence of punch-through phenomenon.

2. The anti-punch-through logic circuit according to claim 1, characterized in that: The high-voltage side anti-punch-through circuit includes field effect transistors MP1, MP2, MN1, a resistor R1, a Zener transistor D1, inverters INV1, INV2, INV3, and a NAND gate NAND1; wherein one end of the resistor R1 is connected to a power supply VDD, and the other end is connected to a source of the field effect transistor MP1, a gate of the field effect transistor MP1 is connected to a control signal HIN, a drain of the field effect transistor MP1 is connected to a source of the field effect transistor MP2, a gate of the field effect transistor MP2 is connected to a relative power rail RAIL_H, a drain of the field effect transistor MP2 is connected to a drain of the field effect transistor MN1, a source of the field effect transistor MN1 is grounded, and a gate of the field effect transistor MN1 is connected to a low-voltage side anti-punch-through circuit. The negative electrode of the Zener tube D1 is connected to the power supply VDD, and the positive electrode is connected to the first input terminal of the NAND gate NAND1, wherein the intersection of the first input terminal of the NAND gate NAND1 and the connecting line of the drain of the field effect tube MP1 and the source of the field effect tube MP2 is defined as point A, the input terminal of the inverter INV1 is connected to the control signal HIN, the output terminal of the inverter INV1 is connected to the second input terminal of the NAND gate NAND1, the output terminal of the NAND gate NAND1 is connected to the input terminal of the inverter INV2, the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3, and the output terminal of the inverter INV3 outputs the output signal PG of the high-voltage side anti-punch-through circuit.

3. The anti-punch-through logic circuit according to claim 1, characterized in that: The low-voltage side anti-punch-through circuit includes field effect transistors MP3, MN2, MN3, resistor R2, Zener transistor D2, inverters INV4, INV5, INV6, and NOR gate NOR1; wherein one end of the resistor R2 is grounded, and the other end is connected to the source of the field effect transistor MN3, the gate of the field effect transistor MN3 is connected to the control signal LIN, the drain of the field effect transistor MN3 is connected to the source of the field effect transistor MN2, the gate of the field effect transistor MN2 is connected to the relative power rail RAIL_L, the drain of the field effect transistor MN2 is connected to the drain of the field effect transistor MP3, the source of the field effect transistor MP3 is connected to the power supply VDD, and the gate of the field effect transistor MP3 is connected to the high voltage The negative electrode of the Zener tube D2 is connected to the first input terminal of the NOR gate NOR1, wherein the intersection of the first input terminal of the NOR gate and the connection line of the source of the field effect tube MN2 and the drain of the field effect tube MN3 is defined as point B, the positive electrode of the Zener tube D2 is grounded, the input terminal of the inverter INV4 is connected to the control signal LIN, the output terminal of the inverter INV4 is connected to the second input terminal of the NOR gate NOR1, the output terminal of the NOR gate NOR1 is connected to the input terminal of the inverter INV5, the output terminal of the inverter INV5 is connected to the input terminal of the inverter INV6, and the output terminal of the inverter INV6 outputs the output signal NG of the low-voltage side anti-punch-through circuit.

4. The anti-punch-through logic circuit according to claim 2, characterized in that: The conditions for the high-voltage side anti-punch-through circuit to output a low level are: the output signal NG of the low-voltage side anti-punch-through circuit is low, the control signal HIN is low, and the potential at point A is high, so that the output of the NAND gate NAND1 is low.

5. The anti-punch-through logic circuit according to claim 3, characterized in that: The conditions for the low-voltage side anti-punch-through circuit to output a high level are: the output signal PG of the high-voltage side anti-punch-through circuit is high, the control signal LIN is high, and the potential at point B is low, so that the output of the NOR gate NOR1 is high.

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