Digital and Heart Rate Signal Processing Method, Device, Storage Medium, and Electronic Device

Abstract

The present disclosure provides a method, apparatus, storage medium, and electronic device for processing digital and heart rate signals. The method includes: determining whether an input signal meets a preset compensation condition; when the input signal meets the preset compensation condition, performing an operation of compensating the Nth digit value of the input signal by 1, and intercepting the first N digit values of the compensated input signal as an output signal; when the input signal does not meet the preset compensation condition, intercepting the first N digit values of the input signal as an output signal; where M and N are both positive integers, M is an integer power of 2, and M is greater than N. By performing compensation processing on the digital input signal to be intercepted that meets the preset conditions before each truncation operation, the error caused by the truncation operation in each operation process is reduced through the operation of compensating by 1, thereby improving the accuracy of the final output result.

Description

Technical Field

[0001] The present disclosure relates to the technical field of signal processing, and particularly to a method, device, storage medium, and electronic device for digital and heart rate signal processing. Background Art

[0002] Digital signal processing has simple logic and strong anti-interference ability, and is widely used in the fields of communication and signal processing. In the prior art, there are also a large number of cases where analog signals are converted into digital signals for arithmetic processing. However, in actual implementation, a large number of addition and multiplication operations performed on digital signals will cause the bit width of the output signal to increase as the number of operations increases, and the consumption of logic resources and storage space will also increase exponentially accordingly. To avoid the above situation, the prior art performs truncation processing on the output result of each operation, and the bit width of the truncated signal only needs to meet the requirements of subsequent operations.

[0003] The traditional truncation method is: directly truncate positive value data, and perform compensation plus 1 processing on negative value data. The above method can quickly implement the truncation operation of digital signals, but the error between the data corresponding to the truncated signal and the data corresponding to the original signal during the truncation process will continuously increase as the number of operations increases, thereby affecting the accuracy of the final output result. Summary of the Invention

[0004] The purpose of the embodiments of the present disclosure is to provide a method, device, storage medium, and electronic device for digital and heart rate signal processing, so as to solve the problem of increased error caused by digital signal truncation in the prior art.

[0005] The embodiments of the present disclosure adopt the following technical solutions: A method for processing a digital signal, which is used to truncate an M-bit input signal into an N-bit output signal, includes: determining whether the input signal meets a preset compensation condition; when the input signal meets the preset compensation condition, performing an operation of compensating 1 on the Nth bit value of the input signal, and truncating the first N bit values of the compensated input signal as the output signal; when the input signal does not meet the preset compensation condition, truncating the first N bit values of the input signal as the output signal; where M and N are both positive integers, M is an integer power of 2, and M is greater than N.

[0006] Further, the preset compensation condition at least includes: the value of the second highest bit of the input signal is 1, where the second highest bit is the (N + 1)th bit of the input signal.

[0007] Embodiments of the present disclosure also provide a method for processing a heart rate signal, including: converting the heart rate signal into a digital signal; mixing the digital signal, and processing the mixed digital signal based on the provided method to obtain a first output signal; filtering the first output signal, and processing the filtered digital signal based on the provided method to obtain a second output signal; determining spectral data of the heart rate signal based on the second output signal.

[0008] Embodiments of the present disclosure also provide a processing device for a digital signal, at least including: an input buffer, a compensation circuit, a gating circuit, and an output buffer; wherein, the input buffer is used for buffering an M-bit input signal, inputting the M-bit input signal to the control end of the gating circuit, and using the first N-bit values of the M-bit input signal as an intermediate signal to input to the first input end of the compensation circuit and the second input end of the gating circuit; the compensation circuit is used for performing an operation of compensating 1 on the Nth-bit value of the intermediate signal, and inputting the compensated intermediate signal to the first input end of the gating circuit; the gating circuit is used for judging whether the M-bit input signal meets a preset compensation condition, and in the case where the M-bit input signal meets the preset compensation condition, inputting the compensated intermediate signal to the input end of the output buffer; in the case where the M-bit input signal does not meet the preset compensation condition, directly inputting the N-bit intermediate signal to the input end of the output buffer; the output buffer is used for outputting an N-bit output signal.

[0009] Further, the gating circuit is specifically used for: judging whether the value of the second highest bit of the M-bit input signal is 1; in the case where the value of the second highest bit is 1, inputting the compensated intermediate signal to the input end of the output buffer; in the case where the value of the second highest bit is not 1, directly inputting the N-bit intermediate signal to the input end of the output buffer.

[0010] Further, the compensation circuit is an adder.

[0011] Further, it further includes: a clock circuit, used for providing a clock signal to the input buffer and the output buffer.

[0012] Further, the input buffer is an M-bit register; the output buffer is an N-bit register.

[0013] Embodiments of the present disclosure also provide a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned digital signal and / or heart rate signal processing method are executed.

[0014] Embodiments of the present disclosure also provide an electronic device, including at least a memory and a processor. A computer program is stored on the memory, and when the processor executes the computer program on the memory, the steps of the above digital signal and / or heart rate signal processing method are implemented.

[0015] The beneficial effects of the embodiments of the present disclosure are as follows: By performing compensation processing on the digital input signal to be intercepted that meets the preset conditions before each truncation, the error caused by the truncation operation in each operation process is reduced through the operation of compensating 1, and the accuracy of the final output result is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 It is a flowchart of the method for processing digital signals in the first embodiment of the present disclosure;

[0018] Figure 2 It is a flowchart of the method for processing heart rate signals in the second embodiment of the present disclosure;

[0019] Figure 3 It is a schematic structural diagram of the digital signal processing device in the third embodiment of the present disclosure;

[0020] Figure 4 It is a schematic structural diagram of the electronic device in the fifth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] Reference is made herein to the accompanying drawings to describe various aspects and features of the present disclosure.

[0022] It should be understood that various modifications can be made to the embodiments claimed herein. Accordingly, the above specification should not be construed as limiting, but merely as exemplifying the embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the present disclosure.

[0023] The drawings included in and forming a part of this specification illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.

[0024] These and other features of the present disclosure will become apparent from the following description of the preferred forms of the embodiments given by way of non-limiting examples with reference to the accompanying drawings.

[0025] It should also be understood that although the present disclosure has been described with reference to some specific examples, those skilled in the art can surely implement many other equivalent forms of the present disclosure, which have the features of the claims and thus are all within the protection scope defined hereby.

[0026] When combined with the accompanying drawings, the above and other aspects, features and advantages of the present disclosure will become more obvious in view of the following detailed description.

[0027] Specific embodiments of the present disclosure will be described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments claimed are merely examples of the present disclosure and can be implemented in various ways. Well-known and / or repetitive functions and structures are not described in detail to avoid obscuring the present disclosure with unnecessary or redundant details. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but are merely used as a basis and representative basis for the claims to teach those skilled in the art to use the present disclosure in substantially any suitable detailed structure in various ways.

[0028] This specification may use the phrase "in one embodiment", "in another embodiment", "in yet another embodiment" or "in other embodiments", which may each refer to one or more of the same or different embodiments according to the present disclosure.

[0029] Digital signals are usually represented by binary numbers with a finite number of bits. The binary representation form of a number in a computer is called the machine number of this number. The machine number is signed. In a computer, the highest bit of a number is used to store the sign, that is, 0 for a positive number and 1 for a negative number; for example, the number +3 in decimal, with a computer word length of 8 bits, is converted to binary as 00000011, and if it is -3, it is 10000011. It should be noted that all digital signals in the present disclosure are in the form of machine numbers, and for the convenience of operation, all digital signals are represented in the form of binary complements.

[0030] To solve the problems existing in the transmission truncation method, the first embodiment of the present disclosure provides a method for processing digital signals, which is mainly applied to process the digital signals output by an operation before the operation result of any digital signal is output, and is used to truncate the M-bit input signal (the digital signal output by the operation) into an N-bit output signal as the final output result of this operation. The flowchart is as Figure 1 shown, mainly including steps S11 to S13:

[0031] S11, determine whether the input signal meets the preset compensation condition. If the input signal meets the preset compensation condition, execute step S2; if the input signal does not meet the preset compensation condition, execute S3;

[0032] S12. Perform the operation of compensating 1 on the Nth bit value of the input signal, and intercept the first N bit values of the compensated input signal as the output signal;

[0033] S13. Intercept the first N bit values of the input signal as the output signal.

[0034] In this embodiment, the input signal is an M-bit digital signal, where M is a positive integer, usually an integer power of 2, such as 8, 16, 32, 64, etc. Its specific value can be adjusted according to actual requirements. The output signal is an N-bit digital signal, where N is also a positive integer. And since the output signal is formed by intercepting the input signal, the value of N is less than M. It can be any positive integer value less than M and greater than 0. However, for the convenience of computer operation, the value of N is also preferably taken as an integer power of 2. For example, M is 16 and N is 8.

[0035] Before intercepting, first determine whether the input signal meets the preset compensation condition. Specifically, the preset compensation condition in this embodiment is that the second-highest bit of the M-bit input signal is 1. That is, determining whether the input signal meets the preset compensation condition is equivalent to determining whether the second-highest bit of the M-bit input signal is 1. The second-highest bit is the value of the (N + 1)th bit of the input signal. That is, when the M-bit input signal is intercepted to the N-bit output signal, the second-highest bit is the first bit of the part that is cut off.

[0036] When the input signal is positive (i.e., the first bit of the input signal is 0), if the second-highest bit of the input signal is 1, it proves that the value of the part of the input signal that is cut off may be relatively large, and directly truncating it will cause a large error from the original value. Therefore, by performing the operation of compensating 1 on the last bit of the part retained after truncation, it is equivalent to performing "rounding" on the part that is intercepted, thereby reducing the error between the intercepted signal and the original signal. If the second-highest bit of the input signal is 0, it proves that the value of the part of the input signal that is cut off may be relatively small, and the error between the truncated value and the original value is also relatively small. Therefore, truncation can be directly performed at this time.

[0037] When the input signal is negative (i.e., the first bit of the input signal is 1), if the second-highest bit of the input signal is 1, the corresponding original code has an increased error from the original value during the conversion to the complement code because 1 bit has been compensated. Therefore, by performing the operation of compensating 1 on the last bit of the part retained after truncation to eliminate the offset caused by the complement code. If the second-highest bit of the input signal is 0, its original code has been compensated once during the conversion to the complement code, which is equivalent to eliminating the error from the original value. Therefore, truncation can be directly performed at this time.

[0038] Combining the above two cases, in this embodiment, there is no need to consider the positive or negative value of the digital signal, and the input signal can be directly intercepted according to the value of the second-highest bit. By compensating the digital input signal to be intercepted that meets the preset conditions before each truncation operation, the error caused by the truncation operation in each operation process is reduced through the operation of compensating 1, improving the accuracy of the final output result.

[0039] The second embodiment of the present disclosure provides a method for processing a heart rate signal, which can be applied to a heart rate monitoring system to eliminate the signal offset caused by signal quantization and truncation during the processing of the heart rate signal. The flowchart is as Figure 2 shown, and mainly includes steps S21 to S24:

[0040] S21, convert the heart rate signal into a digital signal, and the digital signal is represented in the form of two's complement.

[0041] S22, mix the digital signal, and process the mixed digital signal based on the processing method of the digital signal to obtain a first output signal.

[0042] S23, filter the first output signal, and process the filtered digital signal based on the processing method of the digital signal to obtain a second output signal.

[0043] S24, determine the spectral data of the heart rate signal based on the second output signal.

[0044] The heart rate monitoring system collects the user's heart rate signal, which is an analog signal. For convenience of noise reduction, filtering and other processing, the analog signal can be converted into a digital signal through an analog-to-digital converter (ADC, Analog to Digital Converter). It should be noted that the number of bits of the digital signal output by the ADC is usually the same as the number of bits of the output signal obtained after truncation. In this embodiment, 8 bits are taken as an example, that is, N = 8, and the digital signal is represented in the form of two's complement.

[0045] After analog-to-digital conversion, the digital signal is mixed with the local oscillator signal, and then passed through a cascaded FIR low-pass filter to obtain two quadrature signal components with a 90-degree phase difference between the I and Q channels. Inputting the above two quadrature signal components into a fast Fourier transform (FFT) module can obtain the spectral data of the heart rate signal. During the mixing process and the filtering process, the bit width of the digital signal will increase. Therefore, before the corresponding mixing result and filtering result are output after the mixing process and the filtering process, the operation result is truncated based on the digital signal processing method provided in the first embodiment of the present disclosure. It should be understood that the method for truncating the digital signal has been described in the first embodiment and will not be repeated in this embodiment.

[0046] Specifically, after the digital signal after mixing is truncated using the digital signal processing method provided in the first embodiment, the corresponding first output signal is output, and the number of bits of the first output signal is 8. Subsequently, the first output signal is filtered, and the digital signal obtained after filtering is truncated using the digital signal processing method provided in the first embodiment to obtain a second output signal, which is also an 8-bit digital signal. When performing the FFT transformation, the second output signal is used as the input signal for the FFT transformation, and the spectral data corresponding to the heart rate signal is determined.

[0047] In this embodiment, through the improved truncation method of the digital signal, the corresponding operation result is truncated in each operation process of the heart rate signal processing. While simplifying the operation logic and saving cache space, the error between the truncated signal and the original signal is reduced, and the accuracy of the finally obtained spectral signal of the heart rate signal is improved.

[0048] The third embodiment of the present disclosure provides a digital signal processing device, which is mainly used to implement the digital signal processing method of the first embodiment of the present disclosure. It mainly includes the following circuit elements, such as Figure 3As shown: an input buffer 10, a compensation circuit 20, a gating circuit 30, and an output buffer 40. Among them, the input buffer 10 is used to buffer an M-bit input signal, input the M-bit input signal to the control end of the gating circuit 30, and use the first N-bit values of the M-bit input signal as an intermediate signal to input to the first input end of the compensation circuit 20 and the second input end of the gating circuit 30; the compensation circuit 20 is used to perform an operation of compensating by 1 on the Nth-bit value of the intermediate signal, and input the compensated intermediate signal to the first input end of the gating circuit 30; the gating circuit 30 is used to determine whether the M-bit input signal meets a preset compensation condition. When the M-bit input signal meets the preset compensation condition, input the compensated intermediate signal to the input end of the output buffer 40; when the M-bit input signal does not meet the preset compensation condition, directly input the N-bit intermediate signal to the input end of the output buffer 40; the output buffer 40 is used to output an N-bit output signal.

[0049] Specifically, in this embodiment, taking the input signal as a 16-bit digital signal and the output signal as an 8-bit digital signal as an example, in combination with Figure 3 the specific structure of the digital signal processing device will be described. The input buffer 10 is mainly used to store the input signal. In this embodiment, a 16-bit register is selected, and the digital signal output by it is also 8 bits; the output buffer 40 is mainly used to store the output signal. In this embodiment, an 8-bit register is selected; the compensation circuit 20 mainly realizes the addition operation of the signal, so an adder can be selected. Its first input end is connected to the output end of the input buffer 10, and the second input end of the compensation circuit 20 is fixedly input with a signal with a value of 1 of 8 bits (00000001) for performing an operation of compensating by 1 on the signal input to the second input end; the gating circuit 30 judges the second highest bit of the 16-bit digital signal received at the control end. When the value of the second highest bit is 1, output the compensated intermediate signal received at its first input end. When the value of the second highest bit is 0, directly output the N-bit intermediate signal received at its second input end, and after passing through the output buffer 40, the output of the finally intercepted output signal is realized.

[0050] Furthermore, the digital signal processing device further includes a clock circuit 50, which is mainly used to provide a standard clock signal to the input buffer 10 and the output buffer 40, so that the input buffer 10 and the output buffer 40 output signals based on the clock signal.

[0051] This embodiment describes in detail the process of truncating a digital signal in combination with an actual circuit structure, reducing the error caused by the truncation operation in each arithmetic process of the digital signal that meets the preset conditions through the operation of compensating by 1, and improving the accuracy of the final output result. The processing device for the digital signal in this embodiment can be used in combination with any arithmetic circuit for digital signals. For example, the processing device of this embodiment is connected to the output end of a filter to implement truncation processing on the filtered result output by the filter. It can also be used in combination with a system similar to a heart rate monitoring system to process the arithmetic results existing in the process of converting a heart rate signal into spectral data, realizing the simplification of the arithmetic logic and saving cache space while reducing the error between the truncated signal and the original signal.

[0052] The fourth embodiment of the present disclosure provides a storage medium, which can be installed in any electronic device with processing functions. Specifically, it is a computer-readable medium storing a computer program. When the computer program is executed by a processor, it implements the method provided in the first embodiment of the present disclosure, for example, including the following steps S41 to S43:

[0053] S41, determine whether the input signal meets the preset compensation condition;

[0054] S42, when the input signal meets the preset compensation condition, perform an operation of compensating by 1 on the Nth digit value of the input signal, and truncate the first N digit values of the compensated input signal as the output signal;

[0055] S43, when the input signal does not meet the preset compensation condition, truncate the first N digit values of the input signal as the output signal; where M and N are both positive integers, M is an integer power of 2, and M is greater than N.

[0056] Specifically, the preset compensation condition at least includes: the value of the second highest bit of the input signal is 1, where the second highest bit is the (N + 1)th bit of the input signal.

[0057] In addition, when the computer program is executed by the processor, it can also implement the method provided in the second embodiment of the present disclosure, for example, including the following steps S44 to S47:

[0058] S44, convert the heart rate signal into a digital signal;

[0059] S45, perform frequency mixing on the digital signal, and process the frequency-mixed digital signal based on the processing method of the digital signal to obtain a first output signal;

[0060] S46, perform filtering processing on the first output signal, and process the filtered digital signal based on the processing method of the digital signal to obtain a second output signal;

[0061] S47. Determine the spectral data of the heart rate signal based on the second output signal.

[0062] In this embodiment, a compensation process is performed on the digital input signal to be intercepted that meets the preset conditions before each truncation. By operating to compensate by 1, the error caused by the truncation operation in each operation process is reduced, improving the accuracy of the final output result.

[0063] The fifth embodiment of the present disclosure provides an electronic device, which can be used as a terminal node in the Internet of Things. The schematic structural diagram is as Figure 4 shown, including at least a memory 100 and a processor 200. A computer program is stored on the memory 100. When the processor 200 executes the computer program on the memory 100, the method provided in any embodiment of the present disclosure is implemented. Exemplarily, when the processor 200 executes the computer program on the memory 100 to implement the method provided in the first embodiment of the present disclosure, the computer program steps of the electronic device are as follows: S51 to S53:

[0064] S51. Determine whether the input signal meets the preset compensation condition;

[0065] S52. When the input signal meets the preset compensation condition, perform an operation to compensate the Nth digit value of the input signal by 1, and intercept the first N digit values of the compensated input signal as the output signal;

[0066] S53. When the input signal does not meet the preset compensation condition, intercept the first N digit values of the input signal as the output signal; where M and N are both positive integers, M is an integer power of 2, and M is greater than N.

[0067] Specifically, the preset compensation condition at least includes: the value of the second highest bit of the input signal is 1, where the second highest bit is the (N + 1)th bit of the input signal.

[0068] In addition, when the processor 200 executes the computer program on the memory 100 to implement the method provided in the second embodiment of the present disclosure, the computer program steps of the electronic device are as follows: S54 to S57:

[0069] S54. Convert the heart rate signal into a digital signal;

[0070] S55. Mix the digital signal, and process the mixed digital signal based on the digital signal processing method to obtain a first output signal;

[0071] S56. Perform a filtering process on the first output signal, and process the filtered digital signal based on the digital signal processing method to obtain a second output signal;

[0072] S57. Determine the spectral data of the heart rate signal based on the second output signal.

[0073] In this embodiment, a compensation process is performed on the digital input signal to be intercepted that meets the preset conditions before each truncation. By operating to compensate by 1, the error caused by the truncation operation in each operation process is reduced, improving the accuracy of the final output result.

[0074] The above has described multiple embodiments of the present disclosure in detail. However, the present disclosure is not limited to these specific embodiments. Based on the concept of the present disclosure, those skilled in the art can make various variations and modifications to the embodiments, and these variations and modifications should fall within the scope of protection required by the present disclosure.

Claims

1. A method for processing a digital signal, which is used to intercept an M-bit input signal into an N-bit output signal, characterized in that, it includes: judging whether the input signal meets a preset compensation condition; when the input signal meets the preset compensation condition, performing an operation of compensating the Nth bit value of the input signal by 1, and intercepting the first N bit values of the compensated input signal as the output signal; when the input signal does not meet the preset compensation condition, intercepting the first N bit values of the input signal as the output signal; wherein, both M and N are positive integers, M is an integer power of 2, and M is greater than N; the preset compensation condition at least includes: the value of the second highest bit of the input signal is 1, wherein, the second highest bit is the (N + 1)th bit of the input signal.

2. A method for processing a heart rate signal, characterized in that, it includes: converting the heart rate signal into a digital signal; performing frequency mixing on the digital signal, and processing the frequency-mixed digital signal based on the method provided in claim 1 to obtain a first output signal; performing filtering processing on the first output signal, and processing the filtered digital signal based on the method provided in claim 1 to obtain a second output signal; determining the spectral data of the heart rate signal based on the second output signal.

3. A processing device for a digital signal, characterized in that, it at least includes: an input buffer, a compensation circuit, a gating circuit, and an output buffer; wherein, the input buffer is used to buffer an M-bit input signal, input the M-bit input signal to the control end of the gating circuit, and input the first N bit values of the M-bit input signal as an intermediate signal to the first input end of the compensation circuit and the second input end of the gating circuit; the compensation circuit is used to perform an operation of compensating the Nth bit value of the intermediate signal by 1, and input the compensated intermediate signal to the first input end of the gating circuit; the gating circuit is used to judge whether the M-bit input signal meets the preset compensation condition. When the M-bit input signal meets the preset compensation condition, input the compensated intermediate signal to the input end of the output buffer; when the M-bit input signal does not meet the preset compensation condition, directly input the N-bit intermediate signal to the input end of the output buffer; the output buffer is used to output an N-bit output signal; the gating circuit is specifically used for: judging whether the value of the second highest bit of the M-bit input signal is 1; when the value of the second highest bit is 1, input the compensated intermediate signal to the input end of the output buffer; when the value of the second highest bit is not 1, directly input the N-bit intermediate signal to the input end of the output buffer.

4. The processing device according to claim 3, characterized in that, the compensation circuit is an adder.

5. The processing device according to claim 3, characterized in that, it further includes: a clock circuit, which is used to provide a clock signal to the input buffer and the output buffer.

6. The processing device according to claim 3, characterized in that, The input buffer is a register of M bits; the output buffer is a register of N bits.

7. A storage medium storing a computer program, wherein, when the computer program is executed by a processor, the steps of the processing method according to any one of claims 1 to 2 are implemented.

8. An electronic device comprising at least a memory and a processor, and a computer program is stored on the memory, wherein, when the processor executes the computer program on the memory, the steps of the processing method according to any one of claims 1 to 2 are implemented.

Images