Semiconductor element and method for manufacturing the same

Abstract

A semiconductor element and a manufacturing method thereof are disclosed. The semiconductor element mainly comprises a synthetic antiferromagnetic layer, a barrier layer and a free layer. The synthetic antiferromagnetic layer comprises a first fixed layer, a first spacer layer, a second fixed layer, a second spacer layer and a reference layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a method for fabricating the same, and more particularly, to a magnetoresistive random access memory (MRAM) and a method for fabricating the same. BACKGROUND

[0002] It is known that the magnetoresistance (MR) effect is an effect in which the resistance of a material changes with an applied magnetic field. The physical quantity is defined as the difference in resistance with and without a magnetic field divided by the original resistance, and is used to represent the resistance change rate. At present, the magnetoresistance effect has been successfully applied to the production of hard disks, and has important commercial application value. In addition, using the characteristic that the giant magnetoresistance material has different resistance values in different magnetization states, a magnetic random access memory (MRAM) can also be made. The advantage is that the stored data can be retained without power supply.

[0003] The above-mentioned magnetoresistance effect is also applied in the field of magnetic field sensors, for example, an electronic compass component in a mobile phone matched with a global positioning system (GPS), used to provide the user with information such as the moving direction. At present, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned prior art usually include: occupying a large chip area, expensive manufacturing process, high power consumption, insufficient sensitivity, and being easily affected by temperature changes, etc., and it is necessary to further improve. SUMMARY

[0004] One embodiment of the present application discloses a method for fabricating a semiconductor device, which mainly forms a fixed layer on a substrate, forms a first spacer layer on the first fixed layer, forms a second fixed layer on the first spacer layer, forms a second spacer layer on the second fixed layer, forms a third fixed layer on the second spacer layer, forms a third spacer layer on the third fixed layer, forms a reference layer on the third spacer layer, forms a barrier layer on the reference layer, and then forms a free layer on the barrier layer.

[0005] Another embodiment of the present application discloses a semiconductor device, which mainly comprises a synthetic antiferromagnetic layer disposed on a substrate, a barrier layer disposed on the synthetic antiferromagnetic layer, and a free layer disposed on the barrier layer, wherein the synthetic antiferromagnetic layer further comprises a first fixed layer, a first spacer layer disposed on the first fixed layer, a second fixed layer disposed on the first spacer layer, a second spacer layer disposed on the second fixed layer, and a reference layer disposed on the second spacer layer. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figures 1 to 3 A schematic diagram of a method for fabricating an MRAM cell according to an embodiment of the present application;

[0007] Figure 4 A schematic diagram of a structure of an MRAM cell according to an embodiment of the present application.

[0008] Explanation of main component symbols

[0009] 12: substrate

[0010] 14: MRAM region

[0011] 16: interlayer dielectric layer

[0012] 18: metal interconnect structure

[0013] 20: intermetal dielectric layer

[0014] 22: metal interconnect

[0015] 24: barrier layer

[0016] 26: metal layer

[0017] 28: stop layer

[0018] 30: intermetal dielectric layer

[0019] 32: metal interconnect

[0020] 34: metal interconnect structure

[0021] 36: lower electrode

[0022] 38: synthetic antiferromagnetic layer

[0023] 40: fixed layer

[0024] 42: spacer layer

[0025] 44: fixed layer

[0026] 46: spacer layer

[0027] 48: fixed layer

[0028] 50: spacer layer

[0029] 56: Reference Layer

[0030] 58: Barrier Layer

[0031] 60: Free Layer

[0032] 62: MTJ stacked structure

[0033] 64: Upper electrode

[0034] 66:MTJ

[0035] 68: Covering layer

[0036] 70: Intermetallic dielectric layer

[0037] 72: Metal interconnects

[0038] 74: Stop Layer Detailed Implementation

[0039] Please refer to Figures 1 to 3 , Figures 1 to 3 This is a schematic diagram illustrating a method for fabricating a semiconductor device, or more specifically, an MRAM cell, according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region (not shown) are preferably defined on the substrate 12.

[0040] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 16 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric 16 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric 16 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectrics are well known in the art, they will not be described in detail here.

[0041] Then, metal interconnect structures 18 and 34 are sequentially formed on the interlayer dielectric layer 16 to electrically connect the aforementioned contact plug. The metal interconnect structure 18 includes an intermetal dielectric layer 20 and a metal interconnect 22 embedded in the intermetal dielectric layer 20. The metal interconnect structure 34 includes a stop layer 28, an intermetal dielectric layer 30, and a metal interconnect 32 embedded in the stop layer 28 and the intermetal dielectric layer 30.

[0042] In this embodiment, each metal interconnect 26 in the metal interconnect structure 18 preferably includes a trench conductor, and the metal interconnect 32 in the metal interconnect structure 22 located directly below the subsequently formed MTJ includes a via conductor. Furthermore, each metal interconnect 22 and 32 in each metal interconnect structure 18 and 34 can be embedded in the intermetallic dielectric layers 20 and 30 and / or the stop layer 28 and electrically connected to each other using a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 22 and 32 may more specifically include a barrier layer 24 and a metal layer 26, wherein the barrier layer 24 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 26 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. Furthermore, in this example, the metal layer 26 in the metal interconnect 22 preferably contains copper, the metal layer 26 in the metal interconnect 32 preferably contains tungsten, the intermetallic dielectric layers 20 and 30 preferably contain silicon oxide such as tetraethyl orthosilicate (TEOS), and the stop layer 28 contains a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0043] Next, a lower electrode 36 can be formed on the surface of the intermetallic dielectric layer 30 and the intermetallic interconnect 32. Then, an MTJ stack structure 62 consisting of a synthetic antiferromagnetic (SAF) layer 38, a barrier layer 58, and a free layer 60 can be formed on the lower electrode 36, and an upper electrode 64 can be formed on the MTJ stack structure 62. In this embodiment, the method of forming the synthetic antiferromagnetic layer 38 is preferably to first perform step (a) to form a fixed layer 40 on the substrate 12 or the lower electrode 36, and then perform step (b) to form a spacer layer 42 on the fixed layer 40. Steps (a) and (b) are repeated, for example, forming a fixed layer 44 and a spacer layer 46 on the spacer layer 42, and then forming a reference layer 56 on the uppermost spacer layer 46. In other words, the synthetic antiferromagnetic layer 38 prepared by the above method is preferably composed of multiple layers of staggered stacked fixed layers 40, 44 and spacer layers 42, 46, and a reference layer 56 disposed on the surface of the uppermost spacer layer 46. Taking the MRAM cell disclosed in this embodiment as an example, the synthetic antiferromagnetic layer 38 preferably includes two layers of staggered stacked fixed layers 40, 44 and spacer layers 42, 46, and a reference layer 56 disposed on the surface of the uppermost spacer layer 46. The fixed layer 40 is disposed on the surface of the lower electrode 36, the spacer layer 42 is disposed on the surface of the fixed layer 40, the fixed layer 44 is disposed on the surface of the spacer layer 42, the spacer layer 46 is disposed on the surface of the fixed layer 44, and the reference layer 56 is disposed on the surface of the spacer layer 46.

[0044] In this embodiment, each fixing layer 40, 44 may comprise a ferromagnetic layer made of the same or different ferromagnetic materials. The fixing layers 40, 44 and the reference layer 56 may comprise the same or different ferromagnetic materials. The materials of the fixing layers 40, 44 may include, but are not limited to, combinations of materials selected from the group consisting of cobalt and platinum, cobalt and palladium, cobalt and iridium, or cobalt and nickel. Each spacer layer 42, 46 comprises a non-magnetic layer made of a non-magnetic material, such as a material selected from the group consisting of ruthenium, iridium, and rhodium.

[0045] Generally, the reverse magnetic field generated by the synthetic antiferromagnetic layer 38 can be used to balance the stray field of the subsequent magnetic tunneling junction, so that the exchange coupling value between the reference layer and the fixed layer does not decrease and affect the performance of the magnetic tunneling junction. However, since the existing synthetic antiferromagnetic layers only have one set of fixed layer, spacer layer and reference layer to generate antiferromagnetic coupling (AFM coupling) effect, the insufficient effect can easily cause the reference layer to generate a large number of flipping pulses, which will affect the operation of the device. To improve this problem, the present invention mainly involves repeatedly setting one or more sets of alternating stacked structures of fixed layers and spacer layers on the lower electrode, and combining them with the uppermost reference layer to form a synthetic antiferromagnetic layer. The sandwich structure of the spacer layer with the fixed layer and / or reference layer below and above can be used to generate an antiferromagnetic coupling effect. For example, the fixed layer 40, spacer layer 42 and fixed layer 44 can generate an antiferromagnetic coupling effect, and the fixed layer 44, spacer layer 46 and reference layer 56 can generate another antiferromagnetic coupling effect. At the same time, the adjacent antiferromagnetic coupling effect generated by the above-mentioned repeated alternating stacked structure can generate a dipolar coupling effect, thereby improving the stability of the reference layer and preventing the reference layer from flipping due to insufficient antiferromagnetic coupling effect.

[0046] Furthermore, the lower electrode layer 36 and the upper electrode 64 preferably comprise conductive materials, such as, but not limited to, tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or combinations thereof. The reference layer 56 is preferably disposed between the spacer layer 46 and the barrier layer 58, and may comprise ferromagnetic materials, such as iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB), but is not limited thereto. The barrier layer 58 may be composed of an insulating material comprising oxides, such as aluminum oxide (AlO). x The free layer 60, comprising a first free layer and a second free layer, may be composed of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB) and nickel-iron (NiFe), but is not limited to these. The magnetization direction of the free layer 60 can be "freely" changed by an external magnetic field.

[0047] Subsequently, as Figure 2As shown, a patterned mask (not shown) is used as the mask to perform one or more etching processes to remove a portion of the upper electrode 64, a portion of the MTJ stack structure 62, a portion of the lower electrode 36, and a portion of the intermetallic dielectric layer 30 to form an MTJ 66 on the metal interconnect 32. It is worth noting that the etching process performed on the patterned MTJ stack structure 62 and the intermetallic dielectric layer 30 in this embodiment may include reactive ion etching (RIE) and / or ion beam etching (IBE). Due to the characteristics of the ion beam etching process, the top surface of the remaining intermetallic dielectric layer 30 is preferably slightly lower than the top surface of the metal interconnect 32, and the top surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface.

[0048] Then Figure 3 As shown, a masking layer 68 is formed on the MTJ 66 and covers the surface of the intermetallic dielectric layer 30. An intermetallic dielectric layer 70 is formed on the masking layer 68. Then, one or more photolithography and etching processes are performed to remove part of the intermetallic dielectric layer 70 and part of the masking layer 68 to form contact holes (not shown). Next, conductive material is filled into each contact hole and a planarization process such as CMP is used to form metal interconnects 72 that connect to the upper electrode 64 below. Finally, another stop layer 74 is formed on the intermetallic dielectric layer 70 and covers the metal interconnects 72.

[0049] In this embodiment, the masking layer 68 preferably comprises silicon nitride, but other dielectric materials may be selected according to the fabrication process requirements, such as silicon oxide, silicon oxynitride, or silicon carbide. The stop layer 74 may be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbide (SiCN), and preferably comprises silicon carbide. As with the aforementioned metal interconnects 22, each metal interconnect 72 disposed in the intermetallic dielectric layer 70 may be embedded in the intermetallic dielectric layer according to a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 72 may further include a barrier layer and a metal layer. The barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well known in the art, they will not be described in detail here. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

[0050] Please refer to againFigure 4 , Figure 4 A schematic diagram of the structure of an MRAM cell according to an embodiment of the present invention is shown. Figure 4 As shown, compared to the previous embodiment where only two sets of staggered stacked fixing layers 40, 44 and spacer layers 42, 46 are formed on the lower electrode 36, the present invention can adjust the number of fixing layers and spacer layers according to the manufacturing process or product requirements. For example, three sets of staggered stacked fixing layers 40, 44, 48 and spacer layers 42, 46, 50 can be formed on the lower electrode 36, and then a reference layer 56 is formed on the surface of the spacer layer 50 to form a synthetic antiferromagnetic layer 38. This variation is also within the scope of the present invention.

[0051] In summary, to address the issue of insufficient antiferromagnetic coupling in existing synthetic antiferromagnetic layers, which can easily lead to numerous flipping pulses in the reference layer and affect device operation, this invention primarily involves repeatedly stacking one or more alternating layers of fixed and spacer layers on the lower electrode, along with an uppermost reference layer, to form a synthetic antiferromagnetic layer. The sandwich structure of the spacer layer with the fixed and / or reference layers below and above it can generate an antiferromagnetic coupling (AFM) effect. For example, the fixed layer, spacer layer, and fixed layer can generate one antiferromagnetic coupling effect, and the fixed layer, spacer layer, and reference layer can generate another antiferromagnetic coupling effect. The adjacent antiferromagnetic coupling effect generated by the aforementioned repeated alternating stacked structure can also produce a dipolar coupling effect, improving the stability of the reference layer and preventing flipping due to insufficient antiferromagnetic coupling.

[0052] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: A first fixing layer is formed on the substrate; A first spacer layer is formed on the first fixed layer; A second fixing layer is formed on the first spacer layer; A second spacer layer is formed on the second fixed layer; A third fixing layer is formed on the second spacer layer; A third spacer layer is formed on the third fixed layer; A reference layer is formed on the third spacer layer; A barrier layer is formed on the reference layer; as well as A free layer is formed on the barrier layer.

2. The method of claim 1, wherein the first fixing layer is selected from the group consisting of cobalt and platinum.

3. The method of claim 1, wherein the first fixing layer is selected from the group consisting of cobalt and palladium.

4. The method of claim 1, wherein the first fixing layer is selected from the group consisting of cobalt and iridium.

5. The method of claim 1, wherein the first fixing layer is selected from the group consisting of cobalt and nickel.

6. The method of claim 1, wherein the first spacer layer is selected from the group consisting of ruthenium, iridium and rhodium.

7. A semiconductor element, characterized in that, Include: A synthetic antiferromagnetic layer is disposed on a substrate, wherein the synthetic antiferromagnetic layer comprises: First fixed layer; A first spacer layer is disposed on the first fixed layer; The second fixing layer is disposed on the first partition layer; A second spacer layer is disposed on the second fixed layer; The third fixing layer is disposed on the second spacer layer; The third spacer layer is disposed on the third fixed layer; as well as The reference layer is located on the third spacer layer.

8. The semiconductor device of claim 7, further comprising: A barrier layer is disposed on the synthetic antiferromagnetic layer; and The free layer is located on the barrier layer.

9. The semiconductor element of claim 7, wherein the first fixing layer is selected from the group consisting of cobalt and platinum.

10. The semiconductor device of claim 7, wherein the first fixing layer is selected from the group consisting of cobalt and palladium.

11. The semiconductor element of claim 7, wherein the first fixing layer is selected from the group consisting of cobalt and iridium.

12. The semiconductor element of claim 7, wherein the first fixing layer is selected from the group consisting of cobalt and nickel.

13. The semiconductor element of claim 7, wherein the first spacer layer is selected from the group consisting of ruthenium, iridium and rhodium.

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