Switching converter circuit and drive circuit therein with adaptive dead time

Abstract

A switching converter circuit and a driving circuit with adaptive dead time therein. The switching converter circuit switches the voltage at one end of an inductor therein according to a pulse width modulation signal to convert an input power supply into an output power supply. The switching converter circuit includes an upper bridge MOSFET, a lower bridge MOSFET, and a driving circuit. The driving circuit includes an upper bridge driver, a lower bridge driver, and a dead time control circuit. The dead time control circuit adaptively delays a lower bridge driving signal according to an output current to generate an upper bridge enabling signal, enabling the upper bridge driver to generate an upper bridge driving signal according to the pulse width modulation signal; and / or adaptively delays the upper bridge driving signal to generate a lower bridge enabling signal, enabling the lower bridge driver to generate a lower bridge driving signal according to the pulse width modulation signal; so as to adaptively control a dead time period during which neither the upper bridge MOSFET nor the lower bridge MOSFET conducts.

Description

Technical Field

[0001] The present invention relates to a switching converter circuit, and particularly to a switching converter circuit having an adaptive dead time and capable of avoiding short-circuit current. The present invention also relates to a driving circuit in the switching converter circuit. Background Art

[0002] Figure 1A FIG. shows a circuit schematic diagram of a prior art switching converter circuit 10. The switching converter circuit 10 includes a driving circuit 11 and a power stage circuit 12. As shown in the figure, the power stage circuit 12 includes an upper bridge switch 121, a lower bridge switch 122, and an inductor 123. The driving circuit 11 generates an upper bridge signal UG and a lower bridge signal LG according to a pulse width modulation (PWM) signal P1. The upper bridge switch 121 and the lower bridge switch 122 operate according to the upper bridge signal UG and the lower bridge signal LG respectively to convert an input voltage Vin into an output voltage Vout and generate an inductor current IL flowing through the inductor 123 of the power stage circuit 12.

[0003] As Figure 1A In the switching converter circuit 10 shown in the figure, the power stage circuit 12 is a buck-type power stage circuit. During normal operation, the upper bridge switch 121 and the lower bridge switch 122 are alternately turned on to switch the end of the inductor 123 electrically connected to the phase node LX between the input voltage Vin and the ground potential GND, so that the inductor current IL alternately switches between the following two current channels: one is from the input voltage Vin flowing through the upper bridge switch 121 to the phase node LX and then through the inductor L to the output; the other is from the ground potential GND flowing through the lower bridge switch 122 to the phase node LX and then through the inductor L to the output. During normal operation, the upper bridge switch 121 and the lower bridge switch 122 must avoid being turned on simultaneously to avoid shoot through and damage to the circuit. Therefore, a dead time when both the upper bridge switch 121 and the lower bridge switch 122 are not turned on is required to separate the conduction periods of the upper bridge switch 121 and the lower bridge switch 122.

[0004] Figure 1B FIG. shows a circuit schematic diagram of the prior art driving circuit 11. As Figure 1BAs shown, the drive circuit 11 includes latch circuits 111 and 112, a level shift circuit 113, an inverter 114, delay circuits 115 and 116, and a plurality of other inverters. Among them, the PWM signal P1 serves as the reset signal of the latch circuit 111. When the PWM signal P1 is at a low level, the latch circuit 111 outputs a high level. After passing through the level shift circuit 113 and then through 3 inverters, the generated upper bridge signal UG is at a low level, and the upper bridge switch 121 is not turned on. When the PWM signal P1 turns to a high level, it is necessary to determine whether to turn the upper bridge signal UG to a high level and turn on the upper bridge switch 121 according to the output signal of the delay circuit 116.

[0005] On the other hand, the PWM signal P1 passes through the inverter 114, and its inverted signal serves as the reset signal of the latch circuit 112. When the PWM signal P1 is at a high level, the latch circuit 112 outputs a high level. After passing through 3 inverters, the generated lower bridge signal LG is at a low level, and the lower bridge switch 122 is not turned on. When the PWM signal P1 turns to a low level, it is necessary to determine whether to turn the lower bridge signal LG to a high level and turn on the upper bridge switch 121 according to the output signal of the delay circuit 115.

[0006] The output signal of the latch circuit 111 is input to the latch circuit 112 after being delayed by the delay circuit 115 for a predetermined fixed upper bridge delay time, serving as the set signal of the latch circuit 112, so as to enable the latch circuit 112 to generate the lower bridge signal LG according to the inverted signal of the PWM signal P1. On the other hand, the output signal of the latch circuit 112 is input to the latch circuit 111 after being delayed by the delay circuit 116 for a predetermined fixed lower bridge delay time, serving as the set signal of the latch circuit 111, so as to enable the latch circuit 111 to generate the upper bridge signal UG according to the PWM signal P1.

[0007] Among them, the upper bridge delay time must be long enough to cover the dead time after the upper bridge switch 121 finishes conduction; and the lower bridge delay time must be long enough to cover the dead time after the lower bridge switch 122 finishes conduction, so as to prevent the upper bridge switch 121 and the lower bridge switch 122 from being turned on simultaneously. Among them, the drive circuit 11 generates a bootstrap voltage BOOT according to the DC voltage VCC. The level shift circuit 113 level shifts the PWM signal P1 after passing through the latch circuit 111 to the startup voltage range (boot voltage domain).

[0008] See also Figure 1A, during the normal operation of the switching converter circuit 10, the dead time is a fixed preset period. After the lower bridge switch 122 ends conduction, after a fixed dead time, the upper bridge switch 121 conducts. After this dead time, the parasitic diode LD in the lower bridge switch 122 changes from forward bias to reverse bias. And during another dead time, after the upper bridge switch 121 ends conduction and before the lower bridge switch 122 conducts, during this dead time, the parasitic diode LD in the lower bridge switch 122 changes from reverse bias to forward bias. During this dead time, the inductor current IL only flows from the ground potential GND through the parasitic diode LD in the lower bridge switch 122 to the phase node LX and then through the inductor L. That is to say, in one switching cycle of the upper bridge switch 121 and the lower bridge switch 122, during the aforementioned two dead times, the PN junction of the parasitic diode LD in the lower bridge switch 122 has two bias reversals, resulting in power and time losses of the reverse recovery charge (Qrr).

[0009] During the normal operation of the prior art switching converter circuit 10, the dead time must be preset to a fixed time long enough to meet the requirements of different dead times caused by the errors generated by the electronic components and circuits in the switching converter circuit 10 during various manufacturing processes. That is to say, the dead time must be preset to exceed the maximum value among the requirements of different dead times caused by various different errors to avoid the simultaneous conduction of the upper bridge switch 121 and the lower bridge switch 122. In this way, most of the switching converter circuits 10 that only require a short dead time will relatively generate more serious power and time losses of the reverse recovery charge, resulting in relatively low conversion efficiency.

[0010] Compared with the aforementioned prior art, the present invention proposes a switching converter circuit with an adaptive dead time and a driving circuit therein that can avoid short-circuit current caused by the simultaneous conduction of the upper bridge switch and the lower bridge switch. Summary of the Invention

[0011] In one aspect, the present invention provides a switching converter circuit for switching one end of an inductor between a first voltage and a second voltage according to a pulse width modulation (PWM) signal to convert an input power supply into an output power supply. The switching converter circuit includes: an upper bridge metal oxide semiconductor field effect transistor (MOSFET) having an N-type conductivity type and coupled between the first voltage and the end of the inductor; a lower bridge MOSFET having an N-type conductivity type and coupled between the second voltage and the end of the inductor; and a driving circuit including: an upper bridge driver enabled by an upper bridge enable signal to generate an upper bridge driving signal according to a PWM signal to drive the upper bridge MOSFET; a lower bridge driver enabled by a lower bridge enable signal to generate a lower bridge driving signal according to the PWM signal to drive the lower bridge MOSFET; and a dead time control circuit for generating a dead time signal according to an output current of the output power supply to adaptively delay the lower bridge driving signal or its in-phase signal, and / or adaptively delay the upper bridge driving signal or its in-phase signal to generate the upper bridge enable signal and / or the lower bridge enable signal to adaptively control a dead time; wherein the dead time is a period during which neither the upper bridge MOSFET nor the lower bridge MOSFET is conducting.

[0012] In another aspect, the present invention also provides a driving circuit for a switching converter circuit, including: an upper bridge driver enabled by an upper bridge enable signal to generate an upper bridge driving signal according to a PWM signal to drive an upper bridge MOSFET; a lower bridge driver enabled by a lower bridge enable signal to generate a lower bridge driving signal according to the PWM signal to drive a lower bridge MOSFET; and a dead time control circuit for generating a dead time signal according to an output current of the output power supply to adaptively delay the lower bridge driving signal or its in-phase signal, and / or adaptively delay the upper bridge driving signal or its in-phase signal to generate the upper bridge enable signal and / or the lower bridge enable signal to adaptively control a dead time; wherein the upper bridge MOSFET and the lower bridge MOSFET are used to switch one end of an inductor between a first voltage and a second voltage to convert an input power supply into the output power supply; wherein the dead time is a period during which neither the upper bridge MOSFET nor the lower bridge MOSFET is conducting.

[0013] In a preferred embodiment, the dead time length is inversely proportional to the output current.

[0014] In a preferred embodiment, the dead time control circuit includes a sensing MOSFET having an N-type conductivity type. The gate of the sensing MOSFET is coupled to the gate of the upper bridge MOSFET or the lower bridge MOSFET. The sensing MOSFET is configured to generate the dead time signal at a sensing resistor serially coupled to the sensing MOSFET according to an upper bridge current flowing through the upper bridge MOSFET or a lower bridge current flowing through the lower bridge MOSFET.

[0015] In a preferred embodiment, the dead time control circuit further includes a Zener diode coupled between the gate and the source of the sensing MOSFET for clamping the gate-source voltage of the sensing MOSFET.

[0016] In a preferred embodiment, the dead time control circuit further includes a clamping MOSFET having an N-type conductivity type. The clamping MOSFET is serially coupled with the sensing MOSFET, and the gate of the clamping MOSFET is coupled to a fixed voltage to clamp the dead time signal.

[0017] In a preferred embodiment, the dead time control circuit further includes a clamping MOSFET having a P-type conductivity type. The clamping MOSFET is serially coupled with the sensing MOSFET, and the gate of the clamping MOSFET is coupled to a bias voltage to clamp the dead time signal, where: the bias voltage is the voltage of a phase node coupled between the upper bridge MOSFET and the lower bridge MOSFET; or the bias voltage is generated by serially connecting at least one MOSFET diode between an input voltage of the input power supply and the gate of the clamping MOSFET.

[0018] In a preferred embodiment, the dead time control circuit further includes an analog-to-digital converter coupled to the sensing MOSFET for converting the dead time signal into a digital signal.

[0019] In a preferred embodiment, the dead time control circuit further includes a latch circuit coupled to the analog-to-digital converter for latching the digital signal enabled by the upper bridge driving signal or the lower bridge driving signal to generate a digital latch signal.

[0020] In a preferred embodiment, the dead time control circuit further includes a delay circuit coupled to the latch circuit for delaying the lower bridge driving signal or the upper bridge driving signal according to the digital latch signal to correspondingly generate the upper bridge enabling signal or the lower bridge enabling signal for adaptively adjusting the dead time.

[0021] In a preferred embodiment, the dead time control circuit further includes: a clamping MOSFET serially coupled to the sensing MOSFET to clamp the dead time signal; and an amplifier having its inverting input terminal coupled to the source of the sensing MOSFET, its non-inverting input terminal coupled to the source of the upper bridge MOSFET, and its output terminal controlling the clamping MOSFET to feedback control such that the source of the sensing MOSFET and the source of the upper bridge MOSFET have the same voltage, thereby ensuring that the operating points of the sensing MOSFET and the upper bridge MOSFET are consistent.

[0022] The following will be described in detail through specific embodiments, and it will be easier to understand the purpose, technical content, features, and achieved effects of the present invention. Brief Description of the Drawings

[0023] Figure 1A Schematic diagram showing a switching converter circuit 10 of the prior art.

[0024] Figure 1B Circuit schematic diagram showing a drive circuit 11 of the prior art.

[0025] Figure 2 Schematic diagram showing a switching converter circuit 20 according to the present invention.

[0026] Figure 3 Schematic diagram showing an embodiment of a drive circuit 31 according to the present invention.

[0027] Figure 4 Schematic diagram showing a more specific embodiment of a drive circuit 31 according to the present invention.

[0028] Figure 5 Schematic diagram showing another more specific embodiment of a drive circuit 31 according to the present invention.

[0029] Figure 6 Schematic diagram showing another more specific embodiment of a drive circuit 31 according to the present invention.

[0030] Figure 7 Schematic diagram showing another more specific embodiment of a drive circuit 31 according to the present invention.

[0031] Figure 8 Schematic diagram showing a more specific embodiment of a delay circuit 3137 according to the present invention.

[0032] Figure 9 Schematic diagram showing another more specific embodiment of a drive circuit 31 according to the present invention.

[0033] Description of Symbols in the Drawings

[0034] 10, 20: Switching converter circuit

[0035] 11, 21, 31: Drive circuit

[0036] 12: Power stage circuit

[0037] 23: Load circuit

[0038] 111, 112, 3136: Latch circuit

[0039] 113, 314, 315: Level shift circuit

[0040] 114: Inverter

[0041] 115, 116: Delay circuit

[0042] 121: High-side switch

[0043] 122: Low-side switch

[0044] 123, 223: Inductor

[0045] 211, 311: High-side driver

[0046] 213, 313: Dead-time control circuit

[0047] 212, 312: Low-side driver

[0048] 221: High-side MOSFET

[0049] 222: Low-side MOSFET

[0050] 3111, 3121: Enable logic circuit

[0051] 3132: Sense resistor

[0052] 3133: Zener diode

[0053] 3134: Clamp MOSFET

[0054] 3135: Analog-to-digital converter

[0055] 3137: Delay circuit

[0056] 3138: Amplifier

[0057] ADH, ADL: Dead-time signal

[0058] BOOT: Bootstrap voltage

[0059] DGL: Digital latch signal

[0060] DGT: Digital signal

[0061] DT<0> - DT<n>: Digital bit signal

[0062] ENH: High-bridge enable signal

[0063] ENL: Low-bridge enable signal

[0064] GND: Ground potential

[0065] Iin: Input current

[0066] Ih: High-bridge current

[0067] IL: Inductor current

[0068] Ilo: Low-bridge current

[0069] Iout: Output current

[0070] Is: Sensing current

[0071] LD: Parasitic diode

[0072] LG: Low-bridge signal

[0073] LX: Phase node

[0074] P1: PWM signal

[0075] Q0, Q11, Q20 - Q2n: Transistors

[0076] SG: High-bridge offset signal

[0077] SH: High-bridge PWM signal

[0078] SL: Low-bridge PWM signal

[0079] VCC: DC voltage

[0080] Vin: Input voltage

[0081] Vg: Fixed voltage

[0082] Vout: Output voltage

[0083] UG: High-bridge signal Detailed implementation mode

[0084] The drawings in the present invention are all schematic, mainly intended to show the coupling relationship between each circuit and the relationship between each signal waveform. As for the circuit, signal waveform and frequency, they are not drawn according to the proportion.

[0085] Figure 2 FIG. shows a schematic diagram of the switching converter circuit 20 according to the present invention. The switching converter circuit 20 is configured to switch one end of the inductor 223 (in this embodiment, the end electrically connected to the phase node LX) between a first voltage (in this embodiment, the input voltage Vin) and a second voltage (in this embodiment, the ground potential GND) according to a pulse width modulation (PWM) signal P1, so as to convert a power supply (including the input voltage Vin and the input current Iin) into an output power supply (including the output voltage Vout and the output current Iout), and provide power to the load circuit 23. The switching converter circuit 20 includes: an upper-bridge metal oxide semiconductor field effect transistor (MOSFET) 221, a lower-bridge MOSFET 222, an inductor 223, and a driving circuit 21.

[0086] In this embodiment, the upper-bridge MOSFET 221 has an N-type conductivity type and is coupled between the input voltage Vin and the phase node LX (this end of the inductor). The lower-bridge MOSFET 222 has an N-type conductivity type and is coupled between the ground potential GND and the phase node LX (this end of the inductor). It should be noted that, in addition to the buck power stage circuit, the present invention can also be applied to boost power stage circuits and buck-boost power stage circuits. As long as the power stage circuit has an N-type upper-bridge MOSFET and an N-type lower-bridge MOSFET, the present invention can be applied to improve the conversion efficiency and reduce the reverse recovery charge loss, and only need to correspondingly change the connection point to which this end of the inductor is coupled, and change the relative connection points to which the upper-bridge MOSFET and the lower-bridge MOSFET are coupled to: the input voltage, the ground potential, the phase node, and the output voltage.

[0087] The driving circuit 21 is configured to generate a PWM signal P1 according to a feedback signal related to the output voltage Vout, and further generate an upper-bridge driving signal UG and a lower-bridge driving signal LG to correspondingly operate the upper-bridge MOSFET 221 and the lower-bridge MOSFET 222, so as to switch this end of the inductor 223 between the first voltage (input voltage Vin) and the second voltage (ground potential GND). The driving circuit 21 includes: an upper-bridge driver 211, a lower-bridge driver 212, and a dead-time control circuit 213.

[0088] The upper bridge driver 211 is enabled by the upper bridge enable signal ENH and generates an upper bridge drive signal UG according to the PWM signal P1 to drive the upper bridge MOSFET 221. The lower bridge driver 212 is enabled by the lower bridge enable signal ENL and generates a lower bridge drive signal LG according to the PWM signal P1 to drive the lower bridge MOSFET 222. The dead time control circuit 213 generates a dead time signal (not shown, to be described in detail later) according to the output current Iout of the output power supply, adaptively delays the lower bridge drive signal LG or its in-phase signal, and / or adaptively delays the upper bridge drive signal UG or its in-phase signal, and generates the upper bridge enable signal ENH and / or the lower bridge enable signal ENL to adaptively control a dead time during which neither the upper bridge MOSFET 221 nor the lower bridge MOSFET 222 conducts.

[0089] In a preferred embodiment, the dead time length is inversely proportional to the output current Iout. The higher the output current Iout, the shorter the dead time length.

[0090] Figure 3 Shows an embodiment of a drive circuit according to the present invention. As Figure 3 shown, the drive circuit 31 includes: an upper bridge driver 311, a lower bridge driver 312, a dead time control circuit 313, and a level shift circuit 315. Among them, the upper bridge driver 311 is enabled by the upper bridge enable signal ENH and generates an upper bridge drive signal UG according to the upper bridge PWM signal SH in phase with the PWM signal P1 (in this embodiment, the upper bridge PWM signal SH is the PWM signal P1) to drive the upper bridge MOSFET 221. The lower bridge driver 312 is enabled by the lower bridge enable signal ENL and generates a lower bridge drive signal LG according to the lower bridge PWM signal SL generated by the PWM signal P1 passing through an inverter to drive the lower bridge MOSFET 222. The dead time control circuit 313 generates a dead time signal ADH according to the output current Iout of the output power supply, adaptively delays the lower bridge drive signal LG or its in-phase signal, and generates the upper bridge enable signal ENH to adaptively control a dead time during which neither the upper bridge MOSFET 221 nor the lower bridge MOSFET 222 conducts.

[0091] As Figure 3 As shown, the upper bridge driver 311 includes an enable logic circuit 3111, a level shift circuit 314, and three inverters connected in series with each other. The lower bridge driver 312 includes an enable logic circuit 3121 and three inverters connected in series with each other. The dead time control circuit 313 includes a sense MOSFET 3131 and a sense resistor 3132. After shifting the level of the upper bridge drive signal UG downward, the level shift circuit 315 generates a lower bridge enable signal ENL to be input to the lower bridge driver 312, so that the lower bridge driver 312 can prohibit the lower bridge driver 312 from generating a lower bridge drive signal LG according to the lower bridge PWM signal SL when the upper bridge MOSFET 221 is turned on; and enable the lower bridge driver 312 to generate a lower bridge drive signal LG according to the lower bridge PWM signal SL when the upper bridge MOSFET 221 is not turned on.

[0092] Please continue to refer to Figure 3 , the sense MOSFET 3131 has an N-type conductivity type, and the gate of the sense MOSFET 3131 is coupled to the gate of the upper bridge MOSFET 221. The sense MOSFET 3131 is used to generate a dead time signal ADH at the sense resistor 3132 connected in series between the sense MOSFET 3131 and the ground potential GND according to the upper bridge current Ih flowing through the upper bridge MOSFET 221. In a preferred embodiment, the size of the sense MOSFET 3131 is scaled down in proportion to that of the upper bridge MOSFET 221. That is, the sizes of the gate, source, and drain of the sense MOSFET 3131 are scaled down proportionally to the sizes of the gate, source, and drain of the upper bridge MOSFET 221, so that the sense current Is flowing through the sense MOSFET 3131 is proportional to the upper bridge current Ih flowing through the upper bridge MOSFET 221. In a preferred embodiment, the ratio of the sizes of the gate, source, and drain of the sense MOSFET 3131 to the corresponding sizes of the gate, source, and drain of the upper bridge MOSFET 221 is 1:10000.

[0093] The dead time control circuit 313 generates a dead time signal ADH according to the sense current Is flowing through the sense resistor 3132, and adaptively delays the lower bridge drive signal LG according to the dead time signal ADH to generate an upper bridge enable signal ENH. The upper bridge enable signal ENH enables the upper bridge driver 311 to generate an upper bridge drive signal UG according to the upper bridge PWM signal SH to drive the upper bridge MOSFET 221. That is, the dead time signal ADH adaptively delays the lower bridge drive signal LG to determine the time point when the upper bridge enable signal ENH enables the upper bridge driver 311, and adaptively adjusts the dead time.

[0094] The upper bridge current Ih is proportional to the output current Iout. Therefore, the sense current Is is proportional to the output current Iout, that is, the dead time signal ADH is positively correlated with the output current Iout. When the output current Iout is higher, the dead time signal ADH is also higher, and the time for delaying the lower bridge drive signal LG is shorter, causing the upper bridge enable signal ENH to reach the low potential earlier, and enabling the upper bridge driver 311 to generate the upper bridge drive signal UG according to the upper bridge PWM signal SH earlier to drive the upper bridge MOSFET 221. Therefore, the dead time length is also shorter, making the dead time length inversely proportional to the output current Iout.

[0095] In Figure 3 the lower bridge driver 312 shown, the enable logic circuit 3121 is, for example, a NAND gate latch circuit as shown in Figure 3 Figure. Therefore, one input terminal of the enable logic circuit 3121, for example, the reset pin of the NAND gate latch circuit, receives the lower bridge PWM signal SL; the other end, for example, the set pin of the NAND gate latch circuit, receives the lower bridge enable signal ENL. The lower bridge PWM signal SL is a signal inverted with respect to the PWM signal P1.

[0096] For example, as shown in Figure 3 Figure, when the upper bridge MOSFET 221 is conducting, it means that the lower bridge MOSFET 222 should not conduct. In this case, the lower bridge enable signal ENL is at a prohibited level (high potential in this embodiment) to prohibit the lower bridge driver 312 from operating the lower bridge MOSFET 222 according to the lower bridge PWM signal SL to ensure that the lower bridge MOSFET 222 does not conduct.

[0097] Specifically, the high-potential lower bridge enable signal ENL is input to the enable logic circuit 3121. The enable logic circuit 3121 is, for example, a NAND gate latch circuit as shown in Figure 3 Figure. Therefore, one input terminal of the enable logic circuit 3121, for example, the reset pin of the NAND gate latch circuit, receives the lower bridge PWM signal SL; the other end, for example, the set pin of the NAND gate latch circuit, receives the lower bridge enable signal ENL.

[0098] When the lower bridge PWM signal SL is at a low potential representing 0, the enable logic circuit 3121 outputs a high potential representing 1. This high potential passes through three inverters, and the generated lower bridge drive signal LG is at a low potential, and the lower bridge MOSFET 222 does not conduct.

[0099] When the lower-bridge PWM signal SL changes from a low potential representing 0 to a high potential representing 1, and at this time the logic level of the lower-bridge enable signal ENL is still a high potential representing 1 for example, the enable logic circuit 3121 outputs a high potential representing 1, the lower-bridge drive signal LG is at a low potential, and the lower-bridge MOSFET 222 is also not conducting. That is to say, when the lower-bridge enable signal ENL is at a high potential (inhibiting level), regardless of the logic level of the lower-bridge PWM signal SL, the lower-bridge drive signal LG is at a low potential, and the lower-bridge MOSFET 222 does not conduct.

[0100] On the other hand, when the upper-bridge MOSFET 221 is not conducting, it also means that at this time the lower-bridge MOSFET 222 can operate according to the lower-bridge PWM signal SL. In this case, the lower-bridge enable signal ENL changes to an enabling level (low potential in this embodiment) to enable the lower-bridge driver 312, so that the lower-bridge driver 312 operates the lower-bridge MOSFET 222 according to the lower-bridge PWM signal SL.

[0101] Specifically, the low-potential lower-bridge enable signal ENL is input to the enable logic circuit 3121, that is, the set pin of the NAND latch circuit. The output signal of the NAND latch circuit is a signal inverted with respect to the lower-bridge PWM signal SL. This signal passes through three inverters, making the lower-bridge drive signal LG in phase with the lower-bridge PWM signal SL. At the same time, these three inverters also form a tapered buffer. That is to say, when the upper-bridge MOSFET 221 is not conducting and the lower-bridge enable signal ENL is at a low potential (enabling level), the lower-bridge driver 312 switches the lower-bridge MOSFET 222 according to the lower-bridge PWM signal SL that is inverted with respect to the PWM signal P1.

[0102] Please continue to refer to Figure 3 The DC voltage VCC is used to generate the bootstrap voltage BOOT of the upper-bridge driver 311. The level shift circuit 314 is used to shift the output signal of the enable logic circuit 3111 upward in level to the boot voltage domain, so that the upper-bridge driver 311 can adjust the upper-bridge drive signal UG according to the upper-bridge enable signal ENH generated by adaptively delaying the lower-bridge drive signal LG through the dead time signal ADH, and further adaptively adjust the dead time.

[0103] For example, as Figure 3 As shown, one input terminal of the enable logic circuit 3111, such as the reset pin of the latch circuit, receives the upper bridge PWM signal SH; the other end, such as the set pin of the NAND latch circuit, receives the upper bridge enable signal ENH. Among them, the upper bridge PWM signal SH is in phase with the PWM signal P1. When the dead time signal ADH increases as the output current Iout rises, the shorter the delay time of the lower bridge drive circuit LG, the faster the upper bridge enable signal ENH reaches the enable level (low level in this embodiment), enabling the enable logic circuit 3111, and enabling the upper bridge drive circuit 311 to generate the upper bridge drive signal UG earlier according to the upper bridge PWM signal SH, thereby shortening the dead time.

[0104] Figure 4 Shows a more specific embodiment of the drive circuit 31 according to the present invention. As Figure 4 shown, the drive circuit 31 includes: an upper bridge driver 311, a lower bridge driver 312, a dead time control circuit 313, and a level shift circuit 315. Among them, the PWM signal P1 is the upper bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper bridge PWM signal SH; the PWM signal P1 generates the lower bridge PWM signal SL through an inverter, indicating that the PWM signal P1 is out of phase with the lower bridge PWM signal SL. The upper bridge driver 311 is enabled by the upper bridge enable signal ENH and generates the upper bridge drive signal UG according to the PWM signal P1 to drive the upper bridge MOSFET 221. The lower bridge driver 312 is enabled by the lower bridge enable signal ENL and generates the lower bridge drive signal LG according to the PWM signal P1 to drive the lower bridge MOSFET 222. The dead time control circuit 313 generates the dead time signal ADH according to the output current Iout of the output power supply to adaptively delay the lower bridge drive signal LG and generate the upper bridge enable signal ENH to adaptively control a dead time during which both the upper bridge MOSFET 221 and the lower bridge MOSFET 222 are not conducting.

[0105] As Figure 4 shown, compared with Figure 3 , the dead time control circuit 313 of this embodiment further includes a Zener diode 3133, a clamping MOSFET 3134, an analog-to-digital converter 3135, a latch circuit 3136, and a delay circuit 3137 in addition to the sense MOSFET 3131 and the sense resistor 3132. Among them, the Zener diode 3133 is coupled between the gate and source of the sense MOSFET 3131 to clamp the gate-source voltage of the sense MOSFET 3131 to avoid excessive sense current Is.

[0106] Please continue to refer to Figure 4 , the clamping MOSFET 3134 has, for example, an N-type conductivity type, and the clamping MOSFET 3134 is serially coupled between the sensing MOSFET 3131 and the sensing resistor 3132. The gate of the clamping MOSFET 3134 is coupled to a fixed voltage Vg (e.g., but not limited to 5V), for example, to clamp the dead time signal ADH.

[0107] Please continue to refer to Figure 4 , the analog-to-digital converter 3135 is serially coupled between the sensing MOSFET 3131 and the latch circuit 3136, for converting the dead time signal ADH into a digital signal DGT and inputting it to the latch circuit 3136.

[0108] Please continue to refer to Figure 4 , the latch circuit 3136 is coupled to the analog-to-digital converter 3135, for example, and is enabled according to the upper bridge drive signal UG to latch the digital signal DGT and generate a digital latch signal DGL.

[0109] Please continue to refer to Figure 4 , the delay circuit 3137 is serially coupled to the latch circuit 3136, for delaying the lower bridge drive signal LG according to the digital latch signal DGL to generate an upper bridge enable signal ENH for inputting to the enable logic circuit 3111 to adaptively delay and adjust the dead time.

[0110] For example, when the lower bridge drive signal LG is at a low level, representing that the lower bridge MOSFET 222 is not conducting, the delay circuit 3137 adaptively delays the lower bridge drive signal LG for a period according to the digital latch signal DGL to generate the upper bridge enable signal ENH to enable the enable logic circuit 3111. The higher the output current Iout, the higher the dead time signal ADH, the higher the digital latch signal DGL, the shorter the period for which the delay circuit 3137 delays the lower bridge drive signal LG, and the earlier the upper bridge drive circuit 311 operates the upper bridge MOSFET 221 according to the upper bridge PWM signal SH, so the dead time is shorter.

[0111] In this embodiment, the function of the latch circuit 3136 is similar to a kind of memory circuit, for latching (memorizing) the digital signal DGT to generate a digital latch signal DGL (the latched digital signal DGT). The digital latch signal DGT is latched (memorized) in the latch circuit 3136 at the falling edge of the upper bridge drive signal UG to generate a digital latch signal DGL (the latched digital latch signal DGT), so that later, when the lower bridge drive signal LG changes from a high level (and at this time the upper bridge drive signal UG is already at a low level) to a low level (the upper bridge drive signal UG has not yet changed to a high level), the period for delaying the lower bridge drive signal LG is determined according to the digital latch signal DGT related to the output current Iout and retained in the latch circuit 3136.

[0112] In addition, the rest of this embodiment is the same as that of Figure 3 the embodiment shown. Please refer to Figure 3 the description of

[0113] Figure 5 Another more specific embodiment of the driving circuit 31 according to the present invention is shown. As Figure 5 shown, the driving circuit 31 includes: an upper bridge driver 311, a lower bridge driver 312, a dead time control circuit 313, and a level shift circuit 315. Among them, the PWM signal is the upper bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper bridge PWM signal SH; the PWM signal P1 generates a lower bridge PWM signal SL through an inverter, indicating that the PWM signal P1 is out of phase with the lower bridge PWM signal SL. The upper bridge driver 311 is used to generate an upper bridge driving signal UG according to the PWM signal P1 to drive the upper bridge MOSFET 221. The lower bridge driver 312 is used to generate a lower bridge driving signal LG according to the PWM signal P1 to drive the lower bridge MOSFET 222. The dead time control circuit 313 is used to generate a dead time signal ADH according to the output current Iout of the output power supply to adjust the upper bridge driving signal UG, and adaptively control a dead time when both the upper bridge MOSFET 221 and the lower bridge MOSFET 222 are not conducting.

[0114] The difference between this embodiment and Figure 4 the embodiment shown is that, in this embodiment, the clamping MOSFET 3134 has, for example, a P-type conductivity type, and the clamping MOSFET 3134 is serially coupled to the sensing MOSFET 3131. The gate of the clamping MOSFET 3134 is coupled to a bias voltage to clamp the dead time signal ADH. In a preferred embodiment, as Figure 5 shown, the bias voltage is the voltage of the phase node LX, and the phase node LX is coupled between the upper bridge MOSFET 221 and the lower bridge MOSFET 222. This embodiment omits Figure 4 the Zener diode 3133 shown in Figure 4 ; instead, a Zener diode is coupled in parallel between one end of the sensing resistor 3132 that generates the dead time signal ADH and the ground potential GND to prevent the dead time signal ADH from being too high. In addition, in this embodiment, the drain of the sensing MOSFET 3131 is electrically connected to the input voltage Vin, while Figure 4 in the embodiment shown in Figure 4 the drain of the sensing MOSFET 3131 is electrically connected to the bootstrap voltage BOOT. In addition, the rest of this embodiment is the same as that of

[0115] Figure 6 Show another more specific embodiment of the drive circuit 31 according to the present invention. As Figure 6 shown, the drive circuit 31 includes: an upper bridge driver 311, a lower bridge driver 312, a dead time control circuit 313, and a level shift circuit 315. Among them, the PWM signal is the upper bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper bridge PWM signal SH; the PWM signal P1 generates a lower bridge PWM signal SL through an inverter, indicating that the PWM signal P1 is out of phase with the lower bridge PWM signal SL. The upper bridge driver 311 is used to generate an upper bridge drive signal UG according to the PWM signal P1 to drive the upper bridge MOSFET 221. The lower bridge driver 312 is used to generate a lower bridge drive signal LG according to the PWM signal P1 to drive the lower bridge MOSFET 222. The dead time control circuit 313 is used to generate a dead time signal ADH according to the output current Iout of the output power supply to adjust the upper bridge drive signal UG to adaptively control a dead time period when both the upper bridge MOSFET 221 and the lower bridge MOSFET 222 are not conducting.

[0116] This embodiment is different from the Figure 5 embodiment shown in that, in this embodiment, the clamping MOSFET 3134 has, for example, a P-type conductivity type, and the clamping MOSFET 3134 is serially coupled with the sensing MOSFET 3131. The gate of the clamping MOSFET 3134 is coupled to a bias voltage to clamp the dead time signal ADH. In a preferred embodiment, as Figure 6 shown, the bias voltage is generated by serially connecting at least one MOSFET diode between the input voltage Vout of the input power supply and the gate of the clamping MOSFET 3134. The number of MOSFET diodes is not limited to the Figure 6 3 shown, and can also be a single one, or other numbers in series to provide the bias voltage. In addition, the rest of this embodiment is the same as the Figure 5 embodiment shown. Please refer to the Figure 5 description.

[0117] Figure 7 Show another more specific embodiment of the drive circuit 31 according to the present invention. As Figure 7 As shown, the drive circuit 31 includes: an upper bridge driver 311, a lower bridge driver 312, a dead time control circuit 313, and a level shift circuit 315. Among them, the PWM signal is the upper bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper bridge PWM signal SH; the PWM signal P1 passes through an inverter to generate the lower bridge PWM signal SL, indicating that the PWM signal P1 is out of phase with the lower bridge PWM signal SL. The upper bridge driver 311 is used to generate an upper bridge drive signal UG according to the PWM signal P1 to drive the upper bridge MOSFET 221. The lower bridge driver 312 is used to generate a lower bridge drive signal LG according to the PWM signal P1 to drive the lower bridge MOSFET 222. The dead time control circuit 313 is used to generate a dead time signal ADH according to the output current Iout of the output power supply to adjust the upper bridge drive signal UG and adaptively control a dead time period during which neither the upper bridge MOSFET 221 nor the lower bridge MOSFET 222 conducts.

[0118] This embodiment is different from Figure 6 the embodiment shown in that, in this embodiment, the dead time control circuit 313 further includes an amplifier 3138. Its inverting input terminal is coupled to the source of the sensing MOSFET 3131, its non-inverting input terminal is coupled to the source of the upper bridge MOSFET 221, and the output terminal of the amplifier 3138 controls the clamping MOSFET 3134 to feedback control such that the source of the sensing MOSFET 3131 and the source of the upper bridge MOSFET 221 have the same voltage, ensuring that the operating points of the sensing MOSFET 3131 and the upper bridge MOSFET 221 are the same, forming the effect of a current mirror circuit, even when the sensing MOSFET 3131 and the upper bridge MOSFET 221 operate in the linear region. It should be noted that, in this embodiment, the clamping MOSFET 3134 is a P-type MOSFET. According to the present invention, the clamping MOSFET 3134 can also be an N-type MOSFET, and it is only necessary to correspondingly couple the inverting input terminal of the amplifier 3138 to the source of the upper bridge MOSFET 221 and its non-inverting input terminal to the source of the sensing MOSFET 3131. Except for this, the rest of this embodiment is the same as Figure 6 the embodiment shown. Please refer to Figure 6 the description.

[0119] Figure 8 shows a more specific embodiment of the delay circuit 3137 according to the present invention. As Figure 8 shown, the delay circuit 3137 receives the digital latch signal DGL to delay the lower bridge drive signal LG. Among them, the digital latch signal DGL is positively correlated with the dead time. As Figure 8 As shown, when the lower bridge drive signal LG changes from a high potential to a low potential, the transistor Q0 of the delay circuit 3137 conducts. After the currents provided by the transistors Q11 and Q20 - Q2n are summed up, the capacitor Cd is charged, and then after passing through an inverter, the upper bridge enable signal ENH is generated. Among them, the currents provided by the transistors Q20 - Q2n are respectively from the corresponding digital bit signals DT<0> - DT <n>Adjustment. Among them, the digital bit signals DT<0>-DT <n>For multiple bits corresponding to the digital latch signal DGL. In a preferred embodiment, the higher the dead time signal ADH, the greater the value of the digital latch signal DGL, the greater the current provided by the transistors Q20 - Q2n, resulting in a greater total current, a higher voltage generated after charging the capacitor Cd, and after passing through an inverter, the delay signal DAH is lower, and the upper bridge enable signal ENH reaches a low potential faster to enable the upper bridge driver 311 to drive the upper bridge MOSFET 221 according to the PWM signal P1, so that the dead time is adaptively shortened.

[0120] Figure 9 Shows another more specific embodiment of the drive circuit 31 according to the present invention. As Figure 9 shown, the drive circuit 31 includes: an upper bridge driver 311, a lower bridge driver 312, a dead time control circuit 313, and a level shift circuit 315. Among them, the PWM signal P1 is the upper bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper bridge PWM signal SH; the PWM signal P1 generates a lower bridge PWM signal SL through an inverter, indicating that the PWM signal P1 is out of phase with the lower bridge PWM signal SL. The upper bridge driver 311 is enabled by the upper bridge enable signal ENH and generates an upper bridge drive signal UG according to the PWM signal P1 to drive the upper bridge MOSFET 221. The lower bridge driver 312 is enabled by the lower bridge enable signal ENL and generates a lower bridge drive signal LG according to the lower bridge PWM signal SL that is out of phase with the PWM signal P1 to drive the lower bridge MOSFET 222. The dead time control circuit 313 generates a dead time signal ADL according to the output current Iout of the output power supply to adaptively delay the upper bridge offset signal SG that is in phase with the upper bridge drive signal UG, and generates a lower bridge enable signal ENL to adaptively control a dead time during which neither the upper bridge MOSFET 221 nor the lower bridge MOSFET 222 conducts. Among them, the level shift circuit shifts the level of the upper bridge drive signal UG downward to generate an upper bridge offset signal SG so that the dead time control circuit 313 can process the upper bridge offset signal SG that is in phase with the upper bridge drive signal UG.

[0121] As Figure 9 As shown, different from the several embodiments shown previously, in the dead time control circuit 313 of this embodiment, the sensing MOSFET 3131 is used to generate a dead time signal ADL at the sensing resistor 3132 serially coupled between the sensing MOSFET 3131 and the DC voltage VCC according to the output current Iout and the lower bridge current Ilo flowing through the lower bridge MOSFET 222. In a preferred embodiment, the size of the sensing MOSFET 3131 is scaled down proportionally with the lower bridge MOSFET 222. That is to say, the sizes of the gate, source, and drain of the sensing MOSFET 3131 are scaled down proportionally with the sizes of the gate, source, and drain of the lower bridge MOSFET 222, so that the sensing current Is flowing through the sensing MOSFET 3131 is proportional to the lower bridge current Ilo flowing through the lower bridge MOSFET 222. In a preferred embodiment, the ratio of the sizes of the gate, source, and drain of the sensing MOSFET 3131 to the corresponding sizes of the gate, source, and drain of the lower bridge MOSFET 222 is 1:10000.

[0122] In addition to the sensing MOSFET 3131 and the sensing resistor 3132, it further includes a Zener diode 3133, a clamping MOSFET 3134, an analog-to-digital converter 3135, a latch circuit 3136, and a delay circuit 3137. Among them, the Zener diode 3133 is coupled between the gate and source of the sensing MOSFET 3131 to clamp the gate-source voltage of the sensing MOSFET 3131 to avoid excessive sensing current Is.

[0123] Please continue to refer to Figure 9 , the dead time control circuit 313 generates a dead time signal ADL according to the sensing current Is flowing through the sensing resistor 3132, and adaptively delays the upper bridge offset signal SG in phase with the upper bridge driving signal UG according to the dead time signal ADL to generate a lower bridge enabling signal ENL. The lower bridge enabling signal ENL enables the lower bridge driver 312 to generate a lower bridge driving signal LG according to the lower bridge PWM signal SL to drive the lower bridge MOSFET 222. That is to say, the dead time signal ADL adaptively delays the upper bridge offset signal SG in phase with the upper bridge driving signal UG to determine the time point when the lower bridge enabling signal ENL enables the lower bridge driver 312, and adaptively adjusts the dead time.

[0124] The lower bridge current Ilo is proportional to the output current Iout. Therefore, the sense current Is is proportional to the output current Iout, that is, the dead time signal ADL is positively correlated with the output current Iout. When the output current Iout is higher, the dead time signal ADL is also higher, and the time for delaying the upper bridge shift signal SG is shorter, causing the lower bridge enable signal ENL to reach the low potential earlier, and enabling the lower bridge driver 312 to generate the lower bridge drive signal UG according to the lower bridge PWM signal SL earlier to drive the lower bridge MOSFET 222. Therefore, the dead time length is also shorter, making the dead time length inversely proportional to the output current Iout.

[0125] The present invention has been described with respect to the preferred embodiments. However, the above description is only for making those skilled in the art easily understand the content of the present invention and is not used to limit the scope of the rights of the present invention. Each of the described embodiments is not limited to being applied alone and can also be combined. For example, two or more embodiments can be combined, and some components in one embodiment can also be used to replace the corresponding components in another embodiment. For example, Figures 3 to 6 the upper bridge driver 311 shown can also be correspondingly applied to the lower bridge driver 312, only need to correspondingly sense the lower bridge current, adjust the corresponding relationships of the upper bridge enable signal, the lower bridge enable signal, the dead time signal and the lower bridge current, and correspondingly change the upper bridge driver 311. In addition, in the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the so-called "processing or calculating or generating a certain output result according to a certain signal" in the present invention is not limited to the signal itself, and also includes, when necessary, performing voltage-current conversion, current-voltage conversion, and / or ratio conversion on the signal, and then processing or calculating according to the converted signal to generate a certain output result. It can be seen that in the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combination methods, which are not listed one by one here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.< / n> < / n> < / n>

Claims

1. A switching converter circuit is configured to switch one end of an inductor between a first voltage and a second voltage according to a pulse-width modulation signal to convert an input power supply into an output power supply. The switching converter circuit includes: An upper-bridge metal-oxide semiconductor field-effect transistor having an N-type conductivity type and coupled between the first voltage and the end of the inductor; A following bridge metal oxide semiconductor field effect transistor has an N-type conductivity type and is coupled between the second voltage and the end of the inductor; And A driving circuit, including: An upper-bridge driver configured to be enabled by an upper-bridge enable signal and generate an upper-bridge driving signal according to a pulse-width modulation signal to drive the upper-bridge metal-oxide semiconductor field-effect transistor; A lower-bridge driver configured to be enabled by a lower-bridge enable signal and generate a lower-bridge driving signal according to the pulse-width modulation signal to drive the lower-bridge metal-oxide semiconductor field-effect transistor; and A dead-time control circuit configured to generate a dead-time signal according to an output current of the output power supply to adaptively delay the lower-bridge driving signal or its in-phase signal, and / or adaptively delay the upper-bridge driving signal or its in-phase signal, and generate the upper-bridge enable signal and / or the lower-bridge enable signal to adaptively control a dead-time; Wherein, the dead-time is a period during which neither the upper-bridge metal-oxide semiconductor field-effect transistor nor the lower-bridge metal-oxide semiconductor field-effect transistor is conducting, Wherein, the dead-time control circuit includes a sensing metal-oxide semiconductor field-effect transistor having an N-type conductivity type. The gate of the sensing metal-oxide semiconductor field-effect transistor is coupled to the gate of the upper-bridge metal-oxide semiconductor field-effect transistor or the lower-bridge metal-oxide semiconductor field-effect transistor. The sensing metal-oxide semiconductor field-effect transistor is configured to generate the dead-time signal at a sensing resistor serially coupled to the sensing metal-oxide semiconductor field-effect transistor according to an upper-bridge current flowing through the upper-bridge metal-oxide semiconductor field-effect transistor or a lower-bridge current flowing through the lower-bridge metal-oxide semiconductor field-effect transistor.

2. The switching converter circuit according to claim 1, wherein, The length of the dead-time is inversely proportional to the output current.

3. The switching converter circuit according to claim 1, wherein, The dead-time control circuit further includes a Zener diode coupled between the gate and the source of the sensing metal-oxide semiconductor field-effect transistor to clamp the gate-source voltage of the sensing metal-oxide semiconductor field-effect transistor.

4. The switching converter circuit according to claim 1, wherein, The dead-time control circuit further includes a clamping metal-oxide semiconductor field-effect transistor having an N-type conductivity type. The clamping metal-oxide semiconductor field-effect transistor is serially coupled with the sensing metal-oxide semiconductor field-effect transistor. The gate of the clamping metal-oxide semiconductor field-effect transistor is coupled to a fixed voltage to clamp the dead-time signal.

5. The switching converter circuit according to claim 1, wherein, The dead-time control circuit further includes a clamping metal-oxide semiconductor field-effect transistor having a P-type conductivity type. The clamping metal-oxide semiconductor field-effect transistor is serially coupled with the sensing metal-oxide semiconductor field-effect transistor. The gate of the clamping metal-oxide semiconductor field-effect transistor is coupled to a bias voltage to clamp the dead-time signal, wherein: The bias voltage is the voltage of a phase node, and the phase node is coupled between the upper-bridge metal-oxide-semiconductor field-effect transistor and the lower-bridge metal-oxide-semiconductor field-effect transistor; or The bias voltage is generated by connecting at least one metal-oxide-semiconductor field-effect transistor diode in series between an input voltage of the input power supply and the gate of the clamping metal-oxide-semiconductor field-effect transistor.

6. The switching converter circuit according to claim 1, wherein, The dead-time control circuit further includes an analog-to-digital converter, coupled to the sensing metal-oxide-semiconductor field-effect transistor, for converting the dead-time signal into a digital signal.

7. The switching converter circuit according to claim 6, wherein, The dead-time control circuit further includes a latch circuit, coupled to the analog-to-digital converter, for latching the digital signal enabled by the upper-bridge drive signal or the lower-bridge drive signal to generate a digital latch signal.

8. The switched converter circuit according to claim 7, wherein, The dead-time control circuit further includes a delay circuit, coupled to the latch circuit, for delaying the lower-bridge drive signal or the upper-bridge drive signal according to the digital latch signal to correspondingly generate the upper-bridge enable signal or the lower-bridge enable signal, so as to adaptively adjust the dead time.

9. The switching converter circuit according to claim 1, wherein, The dead-time control circuit further includes: a clamping metal-oxide-semiconductor field-effect transistor, which is serially coupled with the sensing metal-oxide-semiconductor field-effect transistor to clamp the dead-time signal; and an amplifier, the inverting input terminal of the amplifier is coupled to the source of the sensing metal-oxide-semiconductor field-effect transistor, the non-inverting input terminal of the amplifier is coupled to the source of the upper-bridge metal-oxide-semiconductor field-effect transistor, and the output terminal of the amplifier controls the clamping metal-oxide-semiconductor field-effect transistor to feedback-control the source of the sensing metal-oxide-semiconductor field-effect transistor and the source of the upper-bridge metal-oxide-semiconductor field-effect transistor to have the same voltage, so as to ensure that the operating points of the sensing metal-oxide-semiconductor field-effect transistor and the upper-bridge metal-oxide-semiconductor field-effect transistor are consistent.

10. A drive circuit for a switching converter circuit, comprising: an upper-bridge driver, which is enabled by an upper-bridge enable signal and generates an upper-bridge drive signal according to a pulse-width modulation signal to drive an upper-bridge metal-oxide-semiconductor field-effect transistor; a lower-bridge driver, which is enabled by a lower-bridge enable signal and generates a lower-bridge drive signal according to the pulse-width modulation signal to drive a lower-bridge metal-oxide-semiconductor field-effect transistor; and a dead-time control circuit, which generates a dead-time signal according to an output current of an output power supply to adaptively delay the lower-bridge drive signal or its in-phase signal, and / or adaptively delay the upper-bridge drive signal or its in-phase signal, and generate the upper-bridge enable signal and / or the lower-bridge enable signal to adaptively control a dead time; wherein, the upper-bridge metal-oxide-semiconductor field-effect transistor and the lower-bridge metal-oxide-semiconductor field-effect transistor are used to switch one end of an inductor between a first voltage and a second voltage to convert an input power supply into the output power supply; wherein, the dead time is a period during which neither the upper-bridge metal-oxide-semiconductor field-effect transistor nor the lower-bridge metal-oxide-semiconductor field-effect transistor is conducting Among them, the dead time control circuit includes a sensing metal oxide semiconductor field effect transistor with an N-type conductivity type. The gate of the sensing metal oxide semiconductor field effect transistor is coupled to the gate of the upper bridge metal oxide semiconductor field effect transistor or the lower bridge metal oxide semiconductor field effect transistor. The sensing metal oxide semiconductor field effect transistor is used to generate the dead time signal according to an upper bridge current flowing through the upper bridge metal oxide semiconductor field effect transistor or a lower bridge current flowing through the lower bridge metal oxide semiconductor field effect transistor, and at a sensing resistor connected in series to the sensing metal oxide semiconductor field effect transistor.

11. The drive circuit according to claim 10, wherein, The length of the dead time is inversely proportional to the output current.

12. The drive circuit according to claim 10, wherein, The dead time control circuit further includes a Zener diode coupled between the gate and the source of the sensing metal oxide semiconductor field effect transistor for clamping the gate-source voltage of the sensing metal oxide semiconductor field effect transistor.

13. The drive circuit according to claim 10, wherein, The dead time control circuit further includes a clamping metal oxide semiconductor field effect transistor with an N-type conductivity type. The clamping metal oxide semiconductor field effect transistor is connected in series with the sensing metal oxide semiconductor field effect transistor, and the gate of the clamping metal oxide semiconductor field effect transistor is coupled to a fixed voltage to clamp the dead time signal.

14. The drive circuit according to claim 10, wherein The dead time control circuit further includes a clamping metal oxide semiconductor field effect transistor with a P-type conductivity type. The clamping metal oxide semiconductor field effect transistor is connected in series with the sensing metal oxide semiconductor field effect transistor, and the gate of the clamping metal oxide semiconductor field effect transistor is coupled to a bias voltage to clamp the dead time signal, where: The bias voltage is the voltage of a phase node, and the phase node is coupled between the upper bridge metal oxide semiconductor field effect transistor and the lower bridge metal oxide semiconductor field effect transistor; or The bias voltage is generated by connecting at least one metal oxide semiconductor field effect transistor diode in series between an input voltage of the input power supply and the gate of the clamping metal oxide semiconductor field effect transistor.

15. The drive circuit according to claim 10, wherein, The dead time control circuit further includes an analog-to-digital converter coupled to the sensing metal oxide semiconductor field effect transistor for converting the dead time signal into a digital signal.

16. The drive circuit according to claim 15, wherein, The dead time control circuit further includes a latch circuit coupled to the analog-to-digital converter for latching the digital signal enabled by the upper bridge drive signal or the lower bridge drive signal to generate a digital latch signal.

17. The drive circuit according to claim 16, wherein, The dead time control circuit further includes a delay circuit coupled to the latch circuit for delaying the lower bridge drive signal or the upper bridge drive signal according to the digital latch signal to correspondingly generate the upper bridge enable signal or the lower bridge enable signal to adaptively adjust the dead time.

18. The drive circuit according to claim 10, wherein The dead time control circuit further includes: a clamping metal oxide semiconductor field effect transistor, the clamping metal oxide semiconductor field effect transistor is connected in series with the sensing metal oxide semiconductor field effect transistor to clamp the dead time signal; and An amplifier, the inverting input terminal of which is coupled to the source of a sensing metal-oxide-semiconductor field-effect transistor, the non-inverting input terminal of which is coupled to the source of an upper-bridge metal-oxide-semiconductor field-effect transistor, and the output terminal of which controls a clamping metal-oxide-semiconductor field-effect transistor to feedback-control such that the sources of the sensing metal-oxide-semiconductor field-effect transistor and the upper-bridge metal-oxide-semiconductor field-effect transistor have the same voltage, so as to ensure that the operating points of the sensing metal-oxide-semiconductor field-effect transistor and the upper-bridge metal-oxide-semiconductor field-effect transistor are consistent.

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