Encapsulated Circuit Structure and Its Manufacturing Method

Abstract

An encapsulated circuit structure includes a multi-layer circuit substrate, an electronic component, and an insulating layer. The multi-layer circuit substrate includes a metal part, and there is a window on the multi-layer circuit substrate. It is characterized in that the window extends from a first side of the multi-layer circuit substrate towards a second side opposite to the first side, and the metal part is located at the bottom wall of the window; the electronic component is received in the window and bonded to the metal part, and the electronic component is electrically connected to the multi-layer circuit substrate; the insulating layer encapsulates the electronic component in the window. The encapsulated circuit structure is beneficial to reducing the overall thickness. The present application also provides a manufacturing method of the encapsulated circuit structure.

Description

Technical Field

[0001] The present application relates to a circuit board and a manufacturing method thereof, and particularly to a packaged circuit structure and a manufacturing method thereof. Background Art

[0002] In recent years, electronic products have been widely used in daily work and life, and light, thin, and small electronic products have become increasingly popular. As a main component of electronic products, the circuit structure occupies a relatively large space in electronic products. Therefore, the volume of the circuit structure greatly affects the volume of electronic products, and a large-volume circuit structure is bound to be difficult to meet the trend of light, thin, short, and small electronic products. Summary of the Invention

[0003] In view of this, it is necessary to provide a manufacturing method for a packaged circuit structure that solves the above problems.

[0004] There is also provided a packaged circuit structure manufactured by the above manufacturing method.

[0005] A manufacturing method for a packaged circuit structure includes the following steps:

[0006] Provide a multi-layer circuit substrate including a metal part and a window area extending from a first side of the multi-layer circuit substrate in a thickness direction toward a second side opposite to the first side, and the metal part is disposed at a bottom of the window area to carry the window area;

[0007] Remove the window area to form a window, wherein a bottom wall of the window is constituted by the metal part;

[0008] Mount an electronic component in the window and carry it through the metal part, and the electronic component is electrically connected to the multi-layer circuit substrate; and

[0009] Package the electronic component.

[0010] A packaged circuit structure includes a multi-layer circuit substrate, an electronic component, and an insulating layer. The multi-layer circuit substrate includes a metal part, and a window is provided on the multi-layer circuit substrate. The window extends from a first side of the multi-layer circuit substrate toward a second side opposite to the first side, and the metal part is located at a bottom wall of the window; the electronic component is received in the window and adhered to the metal part, and the electronic component is electrically connected to the multi-layer circuit substrate; the insulating layer packages the electronic component in the window.

[0011] Method for manufacturing packaging circuit structure and packaging circuit structure of the present application, which set openings on a multi-layer circuit substrate to accommodate electronic components, is beneficial to reducing the overall thickness of the packaging circuit structure. Among them, the bottom wall of the opening is composed of a metal part, which bears the electronic component when installing the electronic component, is beneficial to improving the bearing strength, and facilitates the installation of the electronic component. Description of the Drawings

[0012] Figure 1 It is a cross-sectional schematic view of a multi-layer circuit substrate according to an embodiment of the present application.

[0013] Figure 2 It is a cross-sectional schematic view of a core board according to an embodiment of the present application.

[0014] Figure 3 It is to Figure 2 The cross-sectional schematic view of manufacturing the core board shown into an inner layer circuit substrate.

[0015] Figure 4 It is at Figure 3 The cross-sectional schematic view of adding layers on the inner layer circuit substrate shown.

[0016] Figure 5 It is at Figure 1 The cross-sectional schematic view of setting an opening on the multi-layer circuit substrate shown.

[0017] Figure 6 It is at Figure 5 The cross-sectional schematic view of installing an electronic component in the opening in

[0018] Figure 7 It is to Figure 6 The cross-sectional schematic view of encapsulating the electronic component in

[0019] Figure 8 It is a cross-sectional schematic view of a packaging circuit structure according to an embodiment of the present application.

[0020] Description of the Main Component Symbols

[0021]

[0022]

[0023] The following specific embodiments will further illustrate the present application in conjunction with the above-mentioned drawings. Specific Embodiments

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of the present application herein are only for the purpose of describing specific embodiments, and are not intended to limit the present application.

[0026] The following will describe in detail some embodiments of the present application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0027] Please refer to Figures 1 to 7 , a method for manufacturing an encapsulation circuit structure according to an embodiment of the present application, which includes the following steps:

[0028] Step S1, please refer to Figure 1 , provide a multi-layer circuit substrate 10, the multi-layer circuit substrate 10 includes a window area 101 extending from the first side 10a of the multi-layer circuit substrate 10 in the thickness direction towards the opposite second side 10b, and a metal part 103 is provided at the bottom of the multi-layer circuit substrate 10 corresponding to the window area 101 to carry the window area 101.

[0029] In some embodiments, no circuit layer is provided in the window area 101. Solder mask layers 18 may be respectively provided on opposite sides of the multi-layer circuit substrate 10 in the thickness direction, wherein the solder mask layer 18 is not provided on the part of the first side 10a corresponding to the window area 101.

[0030] In this embodiment, taking the multi-layer circuit substrate 10 as a circuit substrate with four circuit layers as an example, the multi-layer circuit substrate 10 can be obtained by but not limited to the following methods:

[0031] Step S11, please refer to Figure 2 , provide a core board 11. The core board 11 includes a first metal foil 113, an inner dielectric layer 111, and a second metal foil 115 stacked in sequence in the thickness direction.

[0032] Step S12, please refer to Figure 3, perform circuit manufacturing on the core board 11, so that the first metal foil 113 correspondingly forms a first inner-layer circuit layer 113a, the second metal foil 115 correspondingly forms a second inner-layer circuit layer 115a, and the first inner-layer circuit layer 113a is electrically connected to the second inner-layer circuit layer 115a, thereby obtaining an inner-layer circuit substrate 11a. Among them, the first inner-layer circuit layer 113a includes a metal part 103.

[0033] In this embodiment, the second inner-layer circuit layer 115a may be provided with a first opening 116 corresponding to the metal part 103. Preferably, the size of the first opening 116 may be larger than the size of the metal part 103, so that the orthographic projection of the metal part 103 on the second inner-layer circuit layer 115a is located in the first opening 116.

[0034] Step S13, please refer to Figure 4 , form a first outer-layer circuit substrate 13 by adding layers on the first inner-layer circuit layer 113a, and form a second outer-layer circuit substrate 15 by adding layers on the second inner-layer circuit layer 115a. The first outer-layer circuit substrate 13 includes a first outer-layer dielectric layer 131 combined with the first inner-layer circuit layer 113a and a first outer-layer circuit layer 133 disposed on a side of the first outer-layer dielectric layer 131 away from the inner-layer circuit substrate 11a. The second outer-layer circuit substrate 15 includes a second outer-layer dielectric layer 151 combined with the second inner-layer circuit layer 115a and a second outer-layer circuit layer 153 disposed on a side of the second outer-layer dielectric layer 151 away from the inner-layer circuit substrate 11a.

[0035] In this embodiment, the second outer-layer circuit layer 153 may be provided with a second opening 156 corresponding to the metal part 103. Preferably, the size of the second opening 156 may be larger than the size of the metal part 103, so that the orthographic projection of the metal part 103 on the second outer-layer circuit layer 153 is located in the second opening 156.

[0036] The first outer-layer circuit substrate 13 and the second outer-layer circuit substrate 15 may be electrically connected to the inner-layer circuit substrate 11a respectively.

[0037] Step S14, please refer to Figure 1 , respectively dispose solder mask layers 18 on a side of the first outer-layer circuit substrate 13 away from the inner-layer circuit substrate 11a and on a side of the second outer-layer circuit substrate 15 away from the inner-layer circuit substrate 11a.

[0038] In this embodiment, a solder mask layer 18 provided on the side of the second outer-layer circuit board 15 facing away from the inner-layer circuit board 11a may be provided with a third opening 183 corresponding to the metal part 103. Preferably, the size of the third opening 183 may be larger than the size of the metal part 103, such that the orthographic projection of the metal part 103 on the solder mask layer 18 provided on the side of the second outer-layer circuit board 15 facing away from the inner-layer circuit board 11a is located within the third opening 183.

[0039] In this embodiment, the portion of the second outer-layer dielectric layer 151 corresponding to the metal part 103 and the portion of the inner-layer dielectric layer 111 corresponding to the metal part 103 constitute the window area 101.

[0040] Step S2, please refer to Figure 5 , and remove the window area 101 to form a window 101a, wherein the metal part 103 serves as the bottom wall of the window 101a.

[0041] Preferably, the width of the window 101a may gradually decrease from the first side 10a towards the second side 10b, thereby facilitating ensuring that the entire bottom wall of the window 101a is constituted by the metal part 103. In some embodiments, the width of the window 101a may also remain consistent from the first side 10a towards the second side 10b.

[0042] In some embodiments, the window 101a may be formed by, but not limited to, mechanical depth-controlled cutting, laser cutting, plasma cutting, or sandblasting.

[0043] In some embodiments, before removing the window area 101, a protective film (not shown in the figure) may be provided on the first side 10a and the second side 10b of the multi-layer circuit board 10, wherein the window area 101 is exposed from the protective film. The protective film may reduce the risk of damage to other areas of the multi-layer circuit board 10 when removing the window area 101. The protective film is removed after removing the window area 101 to form the window 101a.

[0044] In this embodiment, removing the portion of the second outer-layer dielectric layer 151 corresponding to the metal part 103 and the portion of the inner-layer dielectric layer 111 corresponding to the metal part 103 forms the window 101a.

[0045] When no circuit layer or solder mask layer is provided in the window area 101, the difference in processing materials during the removal of the window area 101 is reduced, which is conducive to the formation of the window 101a. At the same time, providing the metal part 103 at the bottom of the window area 101 is conducive to determining the cutting depth when removing the window area 101.

[0046] Step S3, please refer to Figure 6 , an electronic component 30 is installed in the opening 101a and carried by the metal part 103, and the electronic component 30 is electrically connected to the multilayer circuit board 10. The metal part 103 carrying the electronic component 30 is beneficial to improving the carrying strength and also facilitating the adhesion of the electronic component 30 to the multilayer circuit board 10.

[0047] Step S4, please refer to Figure 7 , encapsulate the electronic component 30.

[0048] In some embodiments, an insulating layer 60 is provided on the first side 10a of the multilayer circuit board 10, and the insulating layer 60 fills the opening 101a and covers the electronic component 30, thereby encapsulating the electronic component 30.

[0049] The insulating layer 60 can be formed by, but not limited to, injection molding.

[0050] In the present embodiment, a plurality of connection pads 136 are provided on the second side 10b of the multilayer circuit board 10. Step S4 may further include: providing solder balls 40 on the connection pads 136 to facilitate electrical connection with other components.

[0051] Please refer to Figure 8 , the present application also provides a packaged circuit structure 100 of an embodiment. The packaged circuit structure 100 includes a multilayer circuit board 10, an electronic component 30, and an insulating layer 60. The multilayer circuit board 10 includes a metal part 103. An opening 101a is provided on the multilayer circuit board 10, and the opening 101a extends from the first side 10a of the multilayer circuit board 10 to the opposite second side 10b, and the metal part 103 is the bottom wall of the opening 101a. The electronic component 30 is received in the opening 101a and bonded to the metal part 103, and the electronic component 30 is electrically connected to the multilayer circuit board 10. The insulating layer 60 encapsulates the electronic component 30 in the opening 101a.

[0052] Preferably, the width of the opening 101a can gradually decrease from the first side 10a to the second side 10b, which is beneficial to ensuring that the entire bottom wall of the opening 101a is composed of the metal part 103. In some embodiments, the width of the opening 101a can also remain the same from the first side 10a to the second side 10b.

[0053] The packaged circuit structure 100 may further include a plurality of solder balls 40, and each solder ball 40 is provided on the second side 10b of the multilayer circuit board 10 and electrically connected to the multilayer circuit board 10.

[0054] In the present embodiment, the insulating layer 60 is disposed on the first side 10a of the multilayer circuit board 10, fills the opening 101a, and covers the electronic component 30.

[0055] In the present embodiment, the present application will be further described by taking a circuit board with four circuit layers as the multilayer circuit board 10 as an example. The multilayer circuit board 10 may include a dielectric layer 120 and a first circuit layer 121, a second circuit layer 122, a third circuit layer 123, and a fourth circuit layer 124 that are sequentially stacked and spaced apart. The first circuit layer 121 and the fourth circuit layer 124 are respectively located on opposite sides of the dielectric layer 120. The second circuit layer 122 and the third circuit layer 123 are buried in the dielectric layer 120. The multilayer circuit board 10 further includes solder mask layers 18 respectively disposed on the side of the first circuit layer 121 facing away from the fourth circuit layer 124 and the side of the fourth circuit layer 124 facing away from the first circuit layer 121.

[0056] The second circuit layer 122 includes the metal portion 103. The third circuit layer 123 has a first opening 116 corresponding to the metal portion 103, the fourth circuit layer 124 has a second opening 156 corresponding to the metal portion 103, and the solder mask layer 18 on the side of the fourth circuit layer 124 facing away from the first circuit layer 121 has a third opening 183 corresponding to the metal portion 103.

[0057] The opening 101a is opened from the dielectric layer 120 exposed by the third opening 183 and the second opening 156 toward the second circuit layer 122 to expose the metal portion 103.

[0058] The manufacturing method and the packaging circuit structure of the packaging circuit structure of the present application, which set openings on the multilayer circuit board to accommodate electronic components, are beneficial to reducing the overall thickness of the packaging circuit structure. Among them, the bottom wall of the opening is composed of a metal portion, which bears the electronic component when installing the electronic component, is beneficial to improving the bearing strength, and facilitates the installation of the electronic component.

[0059] The above is only a preferred embodiment of the present application and does not impose any formal limitations on the present application. Although the present application has been disclosed as a preferred embodiment above, it is not intended to limit the present application. Any person skilled in the art, without departing from the technical solution scope of the present application, can make some changes or modifications to equivalent embodiments by using the above-disclosed technical content. However, as long as it does not depart from the technical solution content of the present application, any simple modification, equivalent change, and modification made to the above embodiment based on the technical essence of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A manufacturing method of a packaged circuit structure, which comprises the following steps: Providing a multi-layer circuit substrate, including a metal part and a window area extending from the first side of the multi-layer circuit substrate in the thickness direction towards the second side opposite to the first side, wherein the metal part is disposed at the bottom of the window area to carry the window area; Removing the window area to form a window, wherein the bottom walls of the window are all constituted by the metal part, and the width of the window gradually decreases from the first side towards the second side; Mounting an electronic component in the window and carrying it through the metal part, and the electronic component is electrically connected to the multi-layer circuit substrate; and Packaging the electronic component; The preparation of the multi-layer circuit substrate includes the following steps: Providing a core board, including a first metal foil, an inner dielectric layer, and a second metal foil laminated in sequence in the thickness direction; Performing circuit manufacturing on the core board, so that the first metal foil correspondingly forms a first inner circuit layer, the second metal foil correspondingly forms a second inner circuit layer, and the first inner circuit layer is electrically connected to the second inner circuit layer, thereby obtaining an inner circuit substrate; wherein, the first inner circuit layer includes the metal part; the second inner circuit layer is provided with a first opening corresponding to the metal part; Adding a layer on the first inner circuit layer to form a first outer circuit substrate, and adding a layer on the second inner circuit layer to form a second outer circuit substrate. The first outer circuit substrate includes a first outer dielectric layer combined with the first inner circuit layer and a first outer circuit layer disposed on the side of the first outer dielectric layer facing away from the inner circuit substrate. The second outer circuit substrate includes a second outer dielectric layer combined with the second inner circuit layer and a second outer circuit layer disposed on the side of the second outer dielectric layer facing away from the inner circuit substrate.

2. The manufacturing method of the packaged circuit structure as claimed in claim 1, characterized in that, Before removing the window area to form a window, the manufacturing method of the packaged circuit structure further includes: respectively disposing protective films on the first side and the second side of the multi-layer circuit substrate, wherein the window area is exposed from the protective films; After removing the window area to form a window, the manufacturing method of the packaged circuit structure further includes: removing the protective films.

3. The manufacturing method of the packaged circuit structure as claimed in claim 1, characterized in that, The window area does not contain circuits, and solder mask layers are respectively disposed on opposite sides of the multi-layer circuit substrate in the thickness direction, wherein the solder mask layer is not disposed on the part of the first side corresponding to the window area.

4. The manufacturing method of the packaged circuit structure as claimed in claim 3, characterized in that, The preparation of the multi-layer circuit substrate includes the following steps: The second outer circuit layer is provided with a second opening corresponding to the metal part; and Solder mask layers are respectively disposed on the side of the first outer circuit substrate facing away from the inner circuit substrate and on the side of the second outer circuit substrate facing away from the inner circuit substrate, wherein the solder mask layer disposed on the side of the second outer circuit substrate facing away from the inner circuit substrate is provided with a third opening corresponding to the metal part.

5. The manufacturing method of the encapsulated circuit structure as described in claim 4, characterized in that, the sizes of the first opening, the second opening, and the third opening are respectively larger than the size of the metal part.

6. An encapsulated circuit structure, comprising a multi-layer circuit substrate, an electronic component, and an insulating layer. The multi-layer circuit substrate includes a metal part, and a window is provided on the multi-layer circuit substrate. Characterized in that, the window extends from a first side of the multi-layer circuit substrate towards a second side opposite to the first side, the width of the window gradually decreases from the first side towards the second side, and the metal part is located on the bottom wall of the window, and the entire bottom wall of the window is formed by the metal part; the electronic component is received in the window and bonded to the metal part, and the electronic component is electrically connected to the multi-layer circuit substrate; the insulating layer encapsulates the electronic component in the window; the multi-layer circuit substrate includes a dielectric layer, and a first circuit layer, a second circuit layer, a third circuit layer, and a fourth circuit layer that are sequentially stacked and spaced apart. The first circuit layer and the fourth circuit layer are respectively located on opposite sides of the dielectric layer, and the second circuit layer and the third circuit layer are buried in the dielectric layer.

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