A bandgap reference circuit with high temperature compensation function

Abstract

The application relates to a band gap reference circuit with high-temperature compensation function, and belongs to the field of semiconductor integrated circuits. The band gap reference circuit with high-temperature compensation function comprises a band gap reference generation circuit and a high-temperature compensation circuit; the band gap reference generation circuit is connected with the high-temperature compensation circuit; the band gap reference generation circuit is used for generating a band gap reference voltage; and the high-temperature compensation circuit is used for compensating the band gap reference voltage at high temperature. The application solves the problem that the band gap reference voltage is inaccurate due to the increase of reverse saturation leakage current of a parasitic diode of an NPN transistor at high temperature, and realizes the constant of the band gap reference voltage at high temperature.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuits, in particular to a bandgap reference circuit with high-temperature compensation function. BACKGROUND

[0002] As a reference module inside an integrated circuit, a bandgap reference circuit is required to have high stability and temperature insensitivity. In a traditional P-substrate N-well process, the reverse saturation current of a parasitic PN junction increases at high temperature, which causes the collector current of an NPN used in the bandgap reference circuit to be out of proportion, ultimately resulting in inaccurate bandgap reference voltage.

[0003] Currently, in some high-temperature applications, the following methods are commonly used in bandgap reference generation circuits:

[0004] One method is to use a PNP as a bandgap reference unit output. This method requires a large output resistance, so multiple current mirrors need to be stacked. When the supply voltage is low, it cannot meet the demand. Alternatively, an operational amplifier can be used to increase the impedance, but this increases the complexity of the circuit.

[0005] The second method is to use an NPN as a bandgap reference unit output, and then stack NPNs in proportion to the leakage current to ensure that the collector current of the bandgap reference NPN maintains a certain proportion. The disadvantage is that a large area needs to be added, resulting in excessive parasitic capacitance, slow bandgap reference establishment and response time, and is not suitable for high-speed switching applications. SUMMARY

[0006] The purpose of the present application is to provide a bandgap reference circuit with high-temperature compensation function to solve the problem of inaccurate bandgap reference voltage caused by the increase in reverse saturation current of the parasitic diode at high temperature due to the NPN triode process in the prior art.

[0007] To achieve the above purpose, the present application provides the following solutions:

[0008] A bandgap reference circuit with high-temperature compensation function, comprising a bandgap reference generation circuit and a high-temperature compensation circuit; the bandgap reference generation circuit is connected to the high-temperature compensation circuit; the bandgap reference generation circuit is used to generate a bandgap reference voltage; the high-temperature compensation circuit is used to compensate the bandgap reference voltage at high temperature;

[0009] The high-temperature compensation circuit comprises a third NPN triode, a fourth NPN triode, a second current mirror unit and a third current mirror unit.

[0010] The collector of the third NPN transistor and the collector of the fourth NPN transistor are connected with the bandgap reference generating circuit; the base of the third NPN transistor is connected with the collector of the third NPN transistor; the base of the fourth NPN transistor is connected with the collector of the fourth NPN transistor; the emitter of the third NPN transistor and the emitter of the fourth NPN transistor are both connected with one end of the second current mirror unit; one end of the second current mirror unit is connected with one end of the third current mirror unit; the other end of the third current mirror unit is connected with the bandgap reference generating circuit.

[0011] Optionally, the bandgap reference generating circuit comprises a first current mirror unit, a first NPN transistor, a second NPN transistor, a first resistor, a second resistor, a third resistor and a first NMOS transistor.

[0012] The first current mirror unit is connected with the collector of the first NPN transistor, the collector of the second NPN transistor, the collector of the third NPN transistor and the collector of the fourth NPN transistor respectively, and the first current mirror unit is also connected with the gate of the first NMOS transistor; the collector of the second NPN transistor is also connected with the other end of the third current mirror unit; the base of the first NPN transistor, the base of the second NPN transistor and the source of the first NMOS transistor are connected in sequence, and the source of the first NMOS transistor is also connected with one end of the third resistor; the other end of the third resistor is grounded; the emitter of the first NPN transistor is connected with one end of the first resistor; the other end of the first resistor is connected with one end of the second resistor and the emitter of the second NPN transistor; the other end of the second resistor is grounded; the drain of the first NMOS transistor is connected with a direct current voltage source.

[0013] Optionally, the first current mirror unit is used for proportionally mirroring an input current to the second NPN transistor, the third NPN transistor and the fourth NPN transistor; the input current is the current after the difference between the voltage between the base and the emitter of the first NPN transistor and the voltage between the base and the emitter of the second NPN transistor is divided by the resistance value of the first resistor.

[0014] Optionally, the second current mirror unit is used for subtracting the collector current of the fourth NPN transistor from the collector current of the third NPN transistor.

[0015] Optionally, the third current mirror unit is used for proportionally mirroring the output current of the second current mirror unit to the collector of the second NPN transistor; the output current is the difference between the collector current of the third NPN transistor and the collector current of the fourth NPN transistor.

[0016] Optionally, the first NMOS transistor is a common-drain amplifier.

[0017] Optionally, the first current mirror unit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor.

[0018] The source of the first PMOS transistor, the source of the second PMOS transistor, the source of the third PMOS transistor and the source of the fourth PMOS transistor are connected with the direct current source; the gate of the first PMOS transistor is connected with the gate of the second PMOS transistor, the gate of the third PMOS transistor and the gate of the fourth PMOS transistor respectively; the gate of the first PMOS transistor is also connected with the drain of the first PMOS transistor; the drain of the first PMOS transistor is connected with the collector of the first NPN transistor; the drain of the second PMOS transistor is connected with the collector of the second NPN transistor; the drain of the third PMOS transistor is connected with the collector of the third NPN transistor; the drain of the fourth PMOS transistor is connected with the collector of the fourth NPN transistor.

[0019] Optionally, the second current mirror unit comprises a second NMOS transistor and a third NMOS transistor.

[0020] The drain of the second NMOS transistor is connected with the emitter of the third NPN transistor; the gate of the second NMOS transistor is connected with the gate of the third NMOS transistor; the gate of the second NMOS transistor is also connected with the drain of the second NMOS transistor; the drain of the third NMOS transistor is connected with the emitter of the fourth NPN transistor; the source of the second NMOS transistor and the source of the third NMOS transistor are grounded.

[0021] Optionally, the third current mirror unit comprises a fourth NMOS transistor and a fifth NMOS transistor.

[0022] The drain of the fourth NMOS transistor is connected with the drain of the third NMOS transistor; the gate of the fourth NMOS transistor is connected with the gate of the fifth NMOS transistor; the gate of the fourth NMOS transistor is also connected with the drain of the fourth NMOS transistor; the drain of the fifth NMOS transistor is connected with the collector of the second NPN transistor; the source of the fourth NMOS transistor and the source of the fifth NMOS transistor are grounded.

[0023] According to the specific embodiments of the present application, the following technical effects are provided:

[0024] This invention provides a bandgap reference circuit with high-temperature compensation function. When the NPN transistor process causes the parasitic diode to increase the reverse saturation leakage current at high temperature, resulting in inaccurate bandgap reference voltage, the high-temperature compensation circuit compensates for the bandgap reference voltage, improves the stability of the bandgap reference voltage, and achieves constant bandgap reference voltage at high temperature. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A schematic diagram of a bandgap reference circuit with high-temperature compensation function provided by the present invention;

[0027] Figure 2 A circuit schematic diagram of a preferred embodiment of a bandgap reference circuit with high-temperature compensation function provided by the present invention;

[0028] Figure 3 This is a schematic cross-sectional view of a parasitic diode that causes leakage current at high temperatures, provided by the present invention.

[0029] Figure 4 A schematic diagram of the equivalent circuit of the parasitic diode causing leakage at high temperatures, provided by the present invention;

[0030] Figure 5 The bandgap reference temperature drift curve without high-temperature compensation circuitry;

[0031] Figure 6 The bandgap reference temperature drift curve with the addition of a high-temperature compensation circuit.

[0032] Symbol Explanation: 101 - First current mirror unit; 110 - Second current mirror unit; 111 - Third current mirror unit; 102 - First NPN transistor; 103 - Second NPN transistor; 104 - Third NPN transistor; 105 - Fourth NPN transistor; 106 - First NMOS transistor; 107 - First resistor; 108 - Second resistor; 109 - Third resistor; 301 - First PMOS transistor; 302 - Second PMOS transistor; 303 - Third PMOS transistor; 304 - Fourth PMOS transistor; 313 - Second NMOS transistor; 314 - Third NMOS transistor; 315 - Fourth NMOS transistor; 316 - Fifth NMOS transistor. Detailed Implementation

[0033] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0034] The present application aims to provide a bandgap reference circuit with high-temperature compensation function to solve the problem of inaccurate bandgap reference voltage caused by the increase of reverse saturation leakage current of the parasitic diode of NPN transistor at high temperature.

[0035] To make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] Figure 1 As shown in the schematic diagram of the bandgap reference circuit with high-temperature compensation function provided by the present application, Figure 1 The bandgap reference circuit with high-temperature compensation function comprises a bandgap reference generation circuit and a high-temperature compensation circuit; the bandgap reference generation circuit is connected with the high-temperature compensation circuit; the bandgap reference generation circuit is used to generate a bandgap reference voltage; and the high-temperature compensation circuit is used to compensate the bandgap reference voltage at high temperature.

[0037] Further, the bandgap reference generation circuit comprises a first current mirror unit 101, a first NPN transistor 102, a second NPN transistor 103, a first resistor 107, a second resistor 108, a third resistor 109 and a first NMOS transistor 106. The first current mirror unit 101 is used to mirror the input current to the second NPN transistor 103, the third NPN transistor 104 and the fourth NPN transistor 105 in proportion; the input current is the current obtained by dividing the voltage difference between the base and the emitter of the first NPN transistor 102 and the voltage difference between the base and the emitter of the second NPN transistor 103 by the resistance value of the first resistor 107.

[0038] The high-temperature compensation circuit comprises a third NPN transistor 104, a fourth NPN transistor 105, a second current mirror unit 110, and a third current mirror unit 111. The second current mirror unit 110 is configured to subtract the collector current of the third NPN transistor 104 from the collector current of the fourth NPN transistor 105. The third current mirror unit 111 is configured to mirror the output current of the second current mirror unit 110 to the collector of the second NPN transistor 103 in proportion, wherein the output current is the difference between the collector current of the third NPN transistor 104 and the collector current of the fourth NPN transistor 105.

[0039] The first current mirror unit 101 is connected to the collector of the first NPN transistor 102, the collector of the second NPN transistor 103, the collector of the third NPN transistor 104, and the collector of the fourth NPN transistor 105, respectively. The first current mirror unit 101 is also connected to the gate of the first NMOS transistor 106. The collector of the second NPN transistor 103 is also connected to the other end of the third current mirror unit 111. The base of the first NPN transistor 102, the base of the second NPN transistor 103, and the source of the first NMOS transistor 106 are connected in sequence. The source of the first NMOS transistor 106 is also connected to one end of the third resistor 109. The other end of the third resistor 109 is grounded. The emitter of the first NPN transistor 102 is connected to one end of the first resistor 107. The other end of the first resistor 107 is connected to one end of the second resistor 108 and the emitter of the second NPN transistor 103. The other end of the second resistor 108 is grounded. The drain of the first NMOS transistor 106 is connected to a DC voltage source.

[0040] The base of the third NPN transistor 104 is connected to the collector of the third NPN transistor 104. The base of the fourth NPN transistor 105 is connected to the collector of the fourth NPN transistor 105. The emitter of the third NPN transistor 104 and the emitter of the fourth NPN transistor 105 are both connected to one end of the second current mirror unit 110. One end of the second current mirror unit 110 is connected to one end of the third current mirror unit 111.

[0041] In practical applications, the ratio of the first NPN transistor 102, the second NPN transistor 103, the third NPN transistor 104, and the fourth NPN transistor 105 is 2:1:2:1.

[0042] As an optional embodiment, the first NMOS transistor 106 is a common-drain amplifier.

[0043] Figure 2 A preferred scheme of a bandgap reference circuit with high-temperature compensation function provided by the present application is shown in the circuit schematic diagram as Figure 2 The first current mirror unit 101 includes a first PMOS tube 301, a second PMOS tube 302, a third PMOS tube 303 and a fourth PMOS tube 304. In practical application, the ratio of the first PMOS tube 301, the second PMOS tube 302, the third PMOS tube 303 and the fourth PMOS tube 304 is 1:4:1:1.

[0044] The source of the first PMOS tube 301, the source of the second PMOS tube 302, the source of the third PMOS tube 303 and the source of the fourth PMOS tube 304 are connected with the direct current source; the gate of the first PMOS tube 301 is connected with the gate of the second PMOS tube 302, the gate of the third PMOS tube 303 and the gate of the fourth PMOS tube 304 respectively, mirroring the current in the first PMOS tube 301. The gate of the first PMOS tube 301 is also connected with the drain of the first PMOS tube 301; the drain of the first PMOS tube 301 is connected with the collector of the first NPN transistor 102; the drain of the second PMOS tube 302 is connected with the collector of the second NPN transistor 103; the drain of the third PMOS tube 303 is connected with the collector of the third NPN transistor 104; the drain of the fourth PMOS tube 304 is connected with the collector of the fourth NPN transistor 105.

[0045] The second current mirror unit 110 includes a second NMOS tube 313 and a third NMOS tube 314. In practical application, the ratio of the second NMOS tube 313 and the third NMOS tube 314 is 1:1.

[0046] The drain of the second NMOS tube 313 is connected with the emitter of the third NPN transistor 104; the gate of the second NMOS tube 313 is connected with the gate of the third NMOS tube 314; the gate of the second NMOS tube 313 is also connected with the drain of the second NMOS tube 313; the drain of the third NMOS tube 314 is connected with the emitter of the fourth NPN transistor 105; the source of the second NMOS tube 313 and the source of the third NMOS tube 314 are grounded.

[0047] The third current mirror unit 111 includes a fourth NMOS tube 315 and a fifth NMOS tube 316. In practical application, the ratio of the fourth NMOS tube 315 and the fifth NMOS tube 316 is 1:7.

[0048] The drain of the fourth NMOS tube 315 is connected with the drain of the third NMOS tube 314; the gate of the fourth NMOS tube 315 is connected with the gate of the fifth NMOS tube 316; the gate of the fourth NMOS tube 315 is also connected with the drain of the fourth NMOS tube 315; the drain of the fifth NMOS tube 316 is connected with the collector of the second NPN transistor 103; the source of the fourth NMOS tube 315 and the source of the fifth NMOS tube 316 are both grounded.

[0049] The base voltage of the first NPN transistor 102 and the second NPN transistor 103 is the VBG voltage. The working principle is analyzed as follows:

[0050] At low temperature or normal temperature, since the leakage current of the NPN transistor is small relative to the reference current in the circuit and can be ignored, the parasitic diode reverse saturation leakage current flowing through Q1, Q2, Q3 and Q4 can be ignored compared with the current mirror current, so the current flowing through Q3 and Q4 is equal, the current in the fourth NMOS tube 315 of the third current mirror unit 111 is 0, the Icomp current is 0, and the collector current flowing through Q1 and Q2 maintains a 4-fold relationship, and the emitter current flowing through Q1 and Q2 maintains a 4-fold relationship. Figure 2 Q1, Q2, Q3 and Q4 in the formula respectively represent the first NPN transistor, the second NPN transistor, the third NPN transistor and the fourth NPN transistor, and R1, R2 and R3 respectively represent the first resistor, the second resistor and the third resistor.

[0051] At this time, the VBG voltage is calculated as follows:

[0052]

[0053] In the formula, Vt is the thermal voltage, about 26mV, Vbe_Q2 is the voltage between the base and the emitter of Q2, A1 and A2 are the emitter areas of Q1 and Q2 respectively, 5 is the total current multiple flowing through the resistor R2, and I Q1c , I Q2c is the current flowing through the collectors of Q1 and Q2, and by adjusting the ratio of R1 and R2, an ideal temperature characteristic curve can be obtained.

[0054] The existing NPN structure in P-substrate N-well process is as shown in Figure 3 There is a parasitic diode between the collector and the substrate, and the equivalent circuit diagram is as shown in Figure 4As shown, under normal operating conditions, this parasitic diode is in reverse bias. The reverse saturation leakage current is negligible compared to the collector current at low temperatures. However, as the temperature rises, this current will increase exponentially. At high temperatures, this current causes the actual collector current flowing through the NPN transistor to decrease. The reverse leakage saturation current of the parasitic diode is proportional to the area of ​​the NPN transistor.

[0055] If, without the addition of Icomp compensation current, the reverse saturation leakage current of the parasitic diode increases under high temperature conditions, then the influence of the leakage current cannot be ignored. Let the current flowing through the emitter of Q1 be I... Q1e Let the leakage current of the parasitic diode per unit area be Is. Since the area of ​​Q1 is twice that of Q2, the leakage current of Q1 is 2Is. Let the current in the first PMOS transistor 301 be I1. Then we have the following formula:

[0056] I1=I Q1e +2Is (2)

[0057] After this current is mirrored by the first current mirror unit 101, let the current flowing through the second PMOS transistor 302 be I2. Then, the following formula applies:

[0058] I2 = 4I Q1e +8Is (3)

[0059] From equations (2) and (3) and the characteristics of the NPN transistor, we can see that:

[0060] I Q1c =I Q1e (4)

[0061] I Q2c =4I Q1c +7Is (5)

[0062] The VBG expression at this point is as follows:

[0063]

[0064] Substituting equations (4) and (5) into equation (6), we get:

[0065]

[0066] Comparing equation (7) and equation (1), it can be seen that VBG will increase under high temperature conditions without the addition of a compensation current, such as Figure 5 The curve of VBG voltage versus temperature without high-temperature compensation circuit is shown. As the temperature increases, the VBG voltage will rise at high temperatures. The magnitude of the rise is related to the Is current. Since Is changes exponentially with temperature, VBG also increases exponentially at high temperatures.

[0067] Now consider adding high temperature compensation circuit, the current flowing through the emitter of Q3 under high temperature condition is:

[0068] I Q3e =I Q1e (8)

[0069] The current flowing through the emitter of Q4 under high temperature condition is:

[0070] I Q4e =I Q1e +Is (9)

[0071] From (8), (9) can be known that under high temperature condition, Idif current is exactly a parasitic diode reverse saturation current Is, through the third current mirror unit 111 mirror, Icomp is equal to 7Is, and the current is introduced into the drain of the second PMOS tube 302, at this time, the actual current flowing into the collector of Q2 is as follows:

[0072] I Q2c =4I Q1c (10)

[0073] Therefore, the expression of VBG will continue to maintain (1) formula, and is not related to the reverse saturation current of the parasitic diode, and VBG can remain constant, as shown in Figure 6 The VBG temperature change curve after adding high temperature compensation can also maintain the stability of VBG under high temperature state.

[0074] The bandgap reference circuit with high temperature compensation function provided by the application solves the problem that the bandgap reference voltage is inaccurate due to the increase of the reverse saturation current of the parasitic diode under high temperature caused by the NPN transistor process, and realizes the constant of the bandgap reference voltage under high temperature.

[0075] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between each embodiment can be referred to each other.

[0076] The principles and implementation modes of the application are described by applying specific examples in this paper, and the above embodiment description is only used to help understand the method and core idea of the application; at the same time, for those skilled in the art, according to the idea of the application, the specific implementation mode and application range will be changed. In view of the above, the content of the specification should not be understood as the limitation of the application.

Claims

1. A bandgap reference circuit with high temperature compensation function, characterized in that, The band gap reference generating circuit and the high temperature compensation circuit are connected; the band gap reference generating circuit is used for generating a band gap reference voltage; and the high temperature compensation circuit is used for compensating the band gap reference voltage at high temperature. The band gap reference generating circuit comprises a first current mirror unit, a first NPN transistor, a second NPN transistor, a first resistor, a second resistor, a third resistor and a first NMOS transistor. The high temperature compensation circuit comprises a third NPN transistor, a fourth NPN transistor, a second current mirror unit and a third current mirror unit. The first current mirror unit is connected with the collectors of the first NPN transistor, the second NPN transistor, the third NPN transistor and the fourth NPN transistor respectively, and is also connected with the gate of the first NMOS transistor; the collector of the second NPN transistor is also connected with the other end of the third current mirror unit; the base of the first NPN transistor, the base of the second NPN transistor and the source of the first NMOS transistor are connected in sequence, and the source of the first NMOS transistor is also connected with one end of the third resistor; the other end of the third resistor is grounded; the emitter of the first NPN transistor is connected with one end of the first resistor; the other end of the first resistor is connected with one end of the second resistor and the emitter of the second NPN transistor; the other end of the second resistor is grounded; and the drain of the first NMOS transistor is connected with a DC voltage source. The collectors of the third NPN transistor and the fourth NPN transistor are connected with the band gap reference generating circuit; the base of the third NPN transistor is connected with the collector of the third NPN transistor; the base of the fourth NPN transistor is connected with the collector of the fourth NPN transistor; the emitters of the third NPN transistor and the fourth NPN transistor are both connected with one end of the second current mirror unit; one end of the second current mirror unit is connected with one end of the third current mirror unit; and the other end of the third current mirror unit is connected with the band gap reference generating circuit. The second current mirror unit is used for subtracting the collector current of the third NPN transistor from the collector current of the fourth NPN transistor. The second current mirror unit comprises a second NMOS transistor and a third NMOS transistor. The drain of the second NMOS transistor is connected with the emitter of the third NPN transistor; the gate of the second NMOS transistor is connected with the gate of the third NMOS transistor; the gate of the second NMOS transistor is also connected with the drain of the second NMOS transistor; the drain of the third NMOS transistor is connected with the emitter of the fourth NPN transistor; and the source of the second NMOS transistor and the source of the third NMOS transistor are both grounded. The third current mirror unit is configured to mirror an output current of the second current mirror unit to a collector of the second NPN triode in proportion; the output current is a difference between a collector current of the third NPN triode and a collector current of the fourth NPN triode. The third current mirror unit comprises a fourth NMOS tube and a fifth NMOS tube. The drain of the fourth NMOS tube is connected to the drain of the third NMOS tube; the gate of the fourth NMOS tube is connected to the gate of the fifth NMOS tube; the gate of the fourth NMOS tube is also connected to the drain of the fourth NMOS tube; the drain of the fifth NMOS tube is connected to the collector of the second NPN triode; the source of the fourth NMOS tube and the source of the fifth NMOS tube are both grounded.

2. The bandgap reference circuit with high temperature compensation function according to claim 1, characterized in that, The first current mirror unit is configured to mirror an input current to the second NPN triode, the third NPN triode and the fourth NPN triode in proportion; the input current is a current obtained by dividing a difference between a voltage between the base and the emitter of the first NPN triode and a voltage between the base and the emitter of the second NPN triode by a resistance value of the first resistor.

3. The bandgap reference circuit with high temperature compensation function according to claim 1, characterized in that, The first NMOS tube is a common-drain amplifier.

4. The bandgap reference circuit with high temperature compensation function according to claim 1, characterized in that, The first current mirror unit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube. The source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube and the source of the fourth PMOS tube are all connected to a direct current source; the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the gate of the third PMOS tube and the gate of the fourth PMOS tube respectively; the gate of the first PMOS tube is also connected to the drain of the first PMOS tube; the drain of the first PMOS tube is connected to the collector of the first NPN triode; the drain of the second PMOS tube is connected to the collector of the second NPN triode; the drain of the third PMOS tube is connected to the collector of the third NPN triode; and the drain of the fourth PMOS tube is connected to the collector of the fourth NPN triode.

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