A method and device for constructing a knowledge graph for semiconductor manufacturing yield analysis

Abstract

The present invention provides a method for constructing a knowledge graph for semiconductor manufacturing yield analysis, including: obtaining target data related to semiconductor manufacturing; performing knowledge extraction on the target data to obtain entities related to semiconductor manufacturing and the relationships therebetween; constructing a target knowledge graph related to semiconductor manufacturing with the entities as nodes and the relationships as connecting edges; the target knowledge graph is used for analyzing the semiconductor yield and / or determining the decision corresponding to the semiconductor yield. Through the constructed target knowledge graph, the present invention realizes the intelligence of semiconductor yield analysis and / or improvement decision-making in the field of semiconductor manufacturing.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technologies, and particularly to a method and device for constructing a knowledge graph for semiconductor manufacturing yield analysis. Background Art

[0002] In the field of semiconductor integrated circuit manufacturing, the yield of chips is of crucial importance. When there are yield problems on the production line, it is necessary to quickly investigate the root causes of the problems and solve them in a timely manner to ensure the normal operation of the production line 7×24 hours.

[0003] When there are yield problems with products, professional yield analysis engineers (YA: Yield Analyst) are often required to perform real-time analysis on the generated wafer defect data and retrospective analysis on the historical data generated by the machines. Based on past experience, they discover the defects of wafers and / or the failure characteristics of dies, as well as the root causes corresponding to the defects of wafers and / or the failure characteristics of dies. However, this requires yield analysis engineers to manually analyze the data generated by the machines, resulting in a large workload. Moreover, due to the different levels of experience accumulation of yield analysis engineers, different analysis results may be produced. Summary of the Invention

[0004] An embodiment of the present invention provides a method for constructing a knowledge graph for semiconductor manufacturing yield analysis. By performing knowledge extraction on the experience documents formed by past engineers' analysis of semiconductor data, a knowledge graph is formed, and reasoning on the knowledge graph realizes the intelligence of semiconductor yield analysis and / or improvement decision-making in the field of semiconductor manufacturing.

[0005] In a first aspect, the present invention provides a method for constructing a knowledge graph for semiconductor manufacturing yield analysis, including:

[0006] Obtaining target data related to wafer manufacturing;

[0007] Performing knowledge extraction on the target data to obtain entities related to semiconductor manufacturing and the relationships therebetween;

[0008] Constructing a target knowledge graph related to semiconductor manufacturing with the entities as nodes and the relationships as connecting edges; the target knowledge graph is used for analyzing the semiconductor yield and / or determining the decision corresponding to the semiconductor yield.

[0009] In a possible implementation, the target data includes a first type of data, and the first type of data is structured data, including numerical sequences related to the manufacturing equipment of the semiconductor and / or related to the semiconductor;

[0010] For example, the numerical sequence related to semiconductor manufacturing equipment may include: data on the state of the equipment obtained by sensors during the production process, such as, but not limited to, temperature, humidity, pressure, voltage, current, etc.; and the utilization rate of the equipment, etc.; the numerical sequence related to semiconductors may include: data obtained through defect detection during the semiconductor production process (such as semiconductor defect data), data obtained through electrical testing of the semiconductor (such as when the semiconductor is a wafer, the failure type data of die, including calculation unit interval failure, Cache interval failure, storage interval failure, etc.), and pure numerical data such as two columns of numbers of the semiconductor.

[0011] Before extracting knowledge from the target data to obtain entities related to semiconductor manufacturing and the relationships therebetween, it further includes:

[0012] Performing semantic recognition on the numerical sequence to obtain a description text corresponding to the numerical sequence, where the description text describes the abnormal information corresponding to the numerical sequence.

[0013] In a possible implementation, performing semantic recognition on the numerical sequence to obtain a description text corresponding to the numerical sequence includes:

[0014] Matching a corresponding description text for the numerical sequence according to a preset rule template.

[0015] In another possible implementation, performing semantic recognition on the numerical sequence to obtain a description text corresponding to the numerical sequence includes:

[0016] Inputting the numerical sequence into a trained semantic recognition model to obtain a description text corresponding to the numerical sequence.

[0017] In another possible implementation, the target data further includes second type data and / or third type data,

[0018] The second type data includes experience documents generated by engineers analyzing the data generated during the semiconductor production process;

[0019] The third type data is documents related to the semiconductor manufacturing equipment, including one or more of the usage instruction information, fault information, and repair information corresponding to the fault of the manufacturing equipment.

[0020] In another possible implementation, the target knowledge graph is updated at a preset period to update the nodes and connection edges in the target knowledge graph.

[0021] In an example, the entities include event - type entities and object - type entities,

[0022] The event - type entities include one or more of the following: device events, failure - type events, production - step events, yield events, and statistical process control events;

[0023] The object - type entities include one or more of the following: defect - detection - layer objects, device objects, defect objects, failure - type objects, and production - step objects.

[0024] In a second aspect, the present invention provides a semiconductor manufacturing yield analysis method based on a knowledge graph, including:

[0025] Obtaining original data related to semiconductor manufacturing, where the original data includes data related to the manufacturing of semiconductors;

[0026] Based on the original data and the target knowledge graph constructed in advance as described in the first aspect, determining the yield analysis result of the semiconductor and / or determining the decision corresponding to the yield of the semiconductor, where the yield analysis result of the semiconductor includes one or more of the defect information of the wafer, the failure information of the die, and the root cause corresponding to the defect and / or die failure information of the wafer.

[0027] In a third aspect, the present invention provides an apparatus for constructing a knowledge graph for semiconductor manufacturing yield analysis, including:

[0028] An acquisition device, configured to acquire target data related to semiconductor manufacturing;

[0029] An extraction device, configured to perform knowledge extraction on the target data to obtain entities related to semiconductor manufacturing and the relationships therebetween;

[0030] A construction device, configured to construct a target knowledge graph related to semiconductor manufacturing with the entities as nodes and the relationships as connection edges; the target knowledge graph is used for analyzing the semiconductor yield and / or determining the decision corresponding to the semiconductor yield.

[0031] In a fourth aspect, the present invention provides a computer - readable storage medium, on which a computer program is stored. When the computer program is executed on a computer, it causes the computer to execute the methods described in the first aspect and / or the second aspect.

[0032] In a fifth aspect, the present invention further provides a computing device, including a memory and a processor. Instructions are stored in the memory. When the instructions are executed by the processor, the methods described in the first aspect and / or the second aspect are implemented.

[0033] Sixth aspect, the present invention provides a computer program or a computer program product, which includes instructions that, when executed, cause a computer to execute the method described in the first aspect and / or the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 FIG. 6 is a schematic structural diagram of an apparatus for constructing a knowledge graph for semiconductor manufacturing yield analysis provided by an embodiment of the present invention;

[0035] Figure 2 FIG. 10 is a schematic diagram of an application scenario of a semiconductor manufacturing yield analysis apparatus based on a knowledge graph;

[0036] Figure 3 FIG. 14 is a flowchart of a method for constructing a knowledge graph for semiconductor manufacturing yield analysis provided by an embodiment of the present invention;

[0037] Figure 4 FIG. 18 is a schematic diagram of a rule template;

[0038] Figure 5 FIG. 22 is a schematic diagram of a target knowledge graph constructed according to the method provided by an embodiment of the present invention;

[0039] Figure 6 FIG. 26 is a schematic structural diagram of an apparatus for constructing a knowledge graph for semiconductor manufacturing yield analysis provided by an embodiment of the present invention;

[0040] Figure 7 FIG. 30 is a flowchart of a semiconductor manufacturing yield analysis method based on a knowledge graph provided by an embodiment of the invention;

[0041] Figure 8 FIG. 34 is a schematic structural diagram of a computing device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] The technical solutions of the present invention will be further described in detail below with reference to the drawings and embodiments.

[0043] To better understand the solutions of the following embodiments, the following briefly introduces the professional terms involved below:

[0044] A knowledge graph is designed to describe the entities in the objective world and the relationships between the entities, and constitutes a huge semantic network graph.

[0045] An entity refers to something that is distinguishable and exists independently. Entities include object - type entities and event - type entities. Object - type entities can be, for example, a certain person, a certain city, a certain plant, a certain chip, a certain device, etc. Event - type entities are descriptions of an event that has occurred, such as using a certain device in manufacturing production, adopting production steps, etc.

[0046] Entities are the most basic elements in a knowledge graph, and there are relationships between different entities.

[0047] A relationship can be understood as a function representing the relationship between entities.

[0048] Entities are represented in the form of nodes in the knowledge graph, and relationships are represented in the form of edges. Therefore, a knowledge graph includes multiple nodes and the edges connecting the nodes.

[0049] In the field of semiconductor integrated circuit manufacturing, during yield analysis, yield analysis engineers often need to analyze the numerical sequences generated by machines, that is, structured data, and rely on past experience and subjective judgment to discover defects and the root causes corresponding to the defects. Such a yield analysis method is very time - consuming and labor - intensive on the one hand. On the other hand, due to the different experience accumulations of yield analysis engineers, different analysis results may be produced.

[0050] In view of this, the present invention proposes a device for constructing a knowledge graph for semiconductor manufacturing yield analysis, and a semiconductor manufacturing yield analysis device based on a knowledge graph. A device for constructing a knowledge graph for semiconductor manufacturing yield analysis can perform knowledge extraction on the engineer experience documents accumulated in the past, extract the engineer's experience knowledge, and then represent the extracted engineer's experience knowledge to generate a target knowledge graph containing the engineer's experience knowledge. A semiconductor manufacturing yield analysis device based on a knowledge graph has a pre - set target knowledge graph containing the engineer's experience knowledge. Just input the data generated by each machine during the semiconductor manufacturing process into the semiconductor yield analysis device based on the knowledge graph, and the yield analysis result of the semiconductor and / or the decision corresponding to the yield of the semiconductor can be output, including the defect information of the wafer, the failure information of the die, and the root cause corresponding to the defect and / or failure information of the wafer and / or die. It realizes the intelligence of semiconductor yield analysis, ensures the consistency of the analysis results, and liberates the time of yield analysis engineers.

[0051] Wafer manufacturing is a typical scenario in semiconductor manufacturing. The following takes wafer manufacturing as an example to introduce the specific solution of the present invention.

[0052] Figure 1 It is a schematic diagram of the architecture of a device for constructing a knowledge graph for semiconductor manufacturing yield analysis provided by an embodiment of the present invention. As Figure 1As described above, it includes a data layer, a knowledge extraction layer, and a knowledge representation layer.

[0053] The data layer is used to obtain multi-source heterogeneous data. For example, it includes structured data related to the manufacturing (production) of wafers, that is, the data generated by each machine tool during the wafer manufacturing process and the data generated by testing the wafers. The empirical documents formed by engineers' analysis of this structured data are usually semi-structured data. In the data layer, preprocessing is performed on the multi-source heterogeneous data. For example, semantic analysis is performed on the structured data to convert the structured data into text data.

[0054] In the knowledge extraction layer, knowledge extraction is performed on the preprocessed multi-source heterogeneous data to extract entities related to wafer manufacturing and the association relationships between entities.

[0055] In the knowledge representation layer, according to the extracted entities and the relationships between entities, a target knowledge graph is generated. For example, a target manufacturing graph related to wafer manufacturing is constructed with entities as nodes and relationships as connecting edges.

[0056] Figure 2 It is a schematic diagram of an application scenario of a semiconductor manufacturing yield analysis device based on a knowledge graph. As Figure 2 shown, the structured data generated by each machine tool during the semiconductor manufacturing process is input into device 20, and device 20 can output the yield analysis result of the wafer and / or determine the decision corresponding to the yield of the wafer. Among them, the yield analysis result of the wafer includes defect information of the wafer, failure information of the die, or the root cause corresponding to the defect of the wafer and / or the failure of the die.

[0057] Among them, a semiconductor yield analysis device based on a knowledge graph is deployed in device 20. Device 20 can select a suitable computing device according to needs. For example, various server devices, including dedicated server computers (such as personal computer servers, UNIX servers, terminal servers), blade servers, mainframes, server clusters, or any other appropriate arrangement or combination; various terminal devices, including various types of computer devices, such as portable handheld devices, general-purpose computers (such as personal computers or laptop computers), workstation computers, wearable devices, etc. The specific type of computing device of device 20 is not limited in the embodiments of the present invention.

[0058] Figure 3 It is a flowchart of a method for constructing a knowledge graph for semiconductor manufacturing yield analysis provided by an embodiment of the present invention. This method can be applied to Figure 1 the device shown. As Figure 3 shown, a method for constructing a knowledge graph for semiconductor manufacturing yield analysis provided by an embodiment of the present invention includes at least steps S301 - S303.

[0059] In step S301, target data related to wafer manufacturing is obtained.

[0060] In one example, the target data includes a first type of data, and the first type of data includes data related to wafer production.

[0061] The data related to wafer production may include a numerical sequence related to wafer manufacturing equipment. For example, the data including the state of the equipment obtained by sensors during the production of the wafer manufacturing equipment (which can also be called a machine tool) includes, for example, but is not limited to: temperature, humidity, pressure, voltage, current, etc.; and the utilization rate of the wafer manufacturing equipment, etc.

[0062] And / or, data related to the wafer, for example, data obtained by defect detection during the production process of the wafer (such as wafer defect data); data obtained by electrical testing during the production process of the wafer (such as failure type data of die, including calculation unit interval failure, Cache interval failure, storage interval failure, etc.); pure numerical data such as the yield data of the wafer.

[0063] In another example, the target data includes a second type of data, and the second type of data is an experience document generated by engineers analyzing the data (including the first type of data) generated during the wafer production process. This experience document mainly expresses the abnormal data analyzed from the structural data, analyzes these abnormal data, speculates on the wafer defects caused by the abnormal data, and the root causes corresponding to the wafer defects. The experience document of the engineer is usually semi-structured data.

[0064] For example, during the production process, there are some conventional ppt templates to help engineers better summarize and report problems. The common format is:

[0065] i. Description of the problem

[0066] ii. Means of inspection

[0067] iii. Attribution

[0068] iv. Next correction plan

[0069] In other words, the target data is multi-source heterogeneous data, including structured data generated by each machine tool during wafer manufacturing, and semi-structured experience document data formed by engineers analyzing the structured data.

[0070] The target data can be obtained in various ways. For example, the first type of data can be directly obtained from the acquisition devices of each machine in the semiconductor manufacturing process, that is, the acquisition devices that collect the real-time data of each machine directly send the collected data to the device for constructing a knowledge graph for wafer yield analysis. Or, the first type of data can be retrieved from a database that stores the data of each machine in the semiconductor manufacturing process.

[0071] Retrieve the second type of data from the database, where the database stores the experience documents of engineers, or receive the second type of data uploaded by users.

[0072] In practical applications, an appropriate way to obtain the target data can be selected, and the embodiments of the present invention do not limit the way to obtain the target data.

[0073] In another example, the target data includes a third type of data, which is a document related to the manufacturing equipment of the wafer, including one or more of the usage instruction information, fault information, and repair information corresponding to the fault of the manufacturing equipment.

[0074] For example, the document related to the manufacturing of the wafer can be the product manual of the equipment, and the content included therein includes but is not limited to the description of the equipment, each small module of the equipment, common failures, and solutions.

[0075] In another example, the target data can also include multiple types of data among the above-mentioned first type of data, second type of data, and third type of data. That is to say, the target data is multi-source heterogeneous data, including the first type of structured data, the second type of semi-structured data, and the third type of unstructured data.

[0076] In step 302, perform knowledge extraction on the target data to obtain entities related to wafer manufacturing and the relationships therebetween.

[0077] Since the first type of data is structured data, that is, a numerical sequence related to wafer production, it is necessary to convert the structured data into text data that is easy to recognize in order to extract the corresponding entities therefrom.

[0078] Exemplarily, perform semantic recognition on the numerical sequence to obtain a description text of the numerical sequence to describe the abnormal information corresponding to the numerical sequence.

[0079] Semantic recognition of the numerical sequence can be achieved in various ways. For example, according to a preset rule template, match a corresponding description text for the numerical sequence. Exemplarily, it can be based on Figure 4Match according to the shown rule template. For example, when the distribution feature of the numerical sequence is "1 point is outside the control limits", that is, "one point falls outside area A", the description text matched for this numerical sequence according to the rule template is "A large shift", that is, "there is a large deviation".

[0080] It can also be achieved by inputting the numerical sequence into the trained semantic recognition model to obtain the description text corresponding to the numerical sequence for semantic recognition of the numerical sequence. Exemplarily, the framework of the semantic recognition model can be seq2seq. The seq2seq framework includes an encoder and a decoder. The seq2seq framework is trained with a training dataset to establish a mapping relationship between the numerical sequence and the text, and finally a Data-To-Text model, that is, a semantic recognition model that meets the requirements, is obtained.

[0081] Extracting entities from the target data includes event entities and object entities. For example, event entities can include one or more of equipment events, failure type events, production step events, yield events, statistical process control events; object entities can include one or more of defect detection layer objects, equipment objects, defect objects, electrical failure objects, failure type objects, production step objects.

[0082] And the relationships between each of the extracted entities.

[0083] In step S303, a target knowledge graph related to wafer manufacturing is constructed with entities as nodes and relationships as connection edges.

[0084] Taking the entities extracted in step S302 as nodes and the relationships between each entity as connection edges, a target knowledge graph is constructed. This target knowledge graph is used for wafer yield analysis.

[0085] Figure 5 Shows a schematic diagram of a target knowledge graph constructed by the method according to the embodiment of the present invention. Figure 5The square nodes in it represent event - type entities, the circular nodes represent object - type entities, and the connecting edges represent the relationships between various nodes, including multiple types. For example, the connecting edge of the object - type entity and the event - type entity (Entity - Event, En - Ev) type, such as the En - Ev connecting edge in the figure; the connecting edge of the object - type entity and the object - type entity (Entity - Entity, En - En) type, such as the Layer - Tool, Layer - Step, Defect - Layer, Bin–Defect, SPC - Tool, Step - Tool connecting edges in Figure 5; the connecting edge of the event - type entity and the event - type entity (Event - Event, Ev - Ev) type, such as Figure 5 the caused by, leadto, containment, operation, next step connecting edges in

[0086] In another example, the knowledge graph constructed based on the method provided in the invention embodiment can also be updated according to a preset period in practical applications to update the nodes and connecting edges in the target knowledge graph. For example, taking one month as the preset period, every month it is detected whether new knowledge is found in the semiconductor production process. For example, new defect discoveries and root causes are found in the engineer's experience documents, that is, new experience is formed, and the new experience knowledge is supplemented into the target knowledge graph to complete the target knowledge graph.

[0087] Based on the same concept as the foregoing method embodiment, an apparatus 600 for constructing a knowledge graph for semiconductor manufacturing yield analysis is also provided in the embodiment of the present invention. The apparatus 600 for constructing a knowledge graph for semiconductor manufacturing yield analysis includes units or modules for implementing Figures 3 - 5 each step in the method shown.

[0088] Figure 6 It is a schematic structural diagram of an apparatus for constructing a knowledge graph for semiconductor manufacturing yield analysis provided by the embodiment of the present invention. As Figure 6 shown, the apparatus 600 for constructing a knowledge graph for semiconductor manufacturing yield analysis at least includes:

[0089] An acquisition device 601, configured to acquire target data related to wafer manufacturing;

[0090] An extraction device 602, configured to perform knowledge extraction on the target data to obtain entities related to wafer manufacturing and the relationships therebetween;

[0091] A construction device 603, configured to construct a target knowledge graph related to wafer manufacturing with the entities as nodes and the relationships as connection edges; the target knowledge graph is used for analyzing the wafer yield and / or determining the decision corresponding to the wafer yield.

[0092] Among them, the target data related to wafer manufacturing is similar to the target data in the above text, and may include the first type of data, and / or the second type of data, and / or the third type of data mentioned above.

[0093] The device 600 for constructing a knowledge graph for semiconductor manufacturing yield analysis provided by an embodiment of the present invention may correspond to executing the method described in the embodiment of the present invention, and the above and other operations and / or functions of each module in a device 600 for constructing a knowledge graph for wafer yield analysis are respectively for implementing Figures 3 - 5 the corresponding processes of the respective methods in, and the specific implementation can be seen in the above description. For the sake of brevity, it will not be repeated here.

[0094] An embodiment of the present invention also provides a method for semiconductor manufacturing yield analysis based on a knowledge graph, as Figure 7 shown, this method can be applied to Figure 2 the device 20 shown. As Figure 7 shown, a method for semiconductor manufacturing yield analysis based on a knowledge graph provided by an embodiment of the present invention at least includes steps S701 - S702.

[0095] In step S701, obtain the original data related to wafer manufacturing.

[0096] This original data includes a numerical sequence related to manufacturing equipment. For example, the data including the state of the equipment obtained by sensors during the production of wafer manufacturing equipment (which can also be called a machine tool), such as including but not limited to: temperature, humidity, pressure, voltage, current, etc.; and the utilization rate of wafer manufacturing equipment, etc.

[0097] And / or, data related to wafers, such as data obtained through defect detection during the production process of wafers (such as wafer defect data); data obtained through electrical tests during the production process of wafers (such as failure type data of die, including calculation unit interval failure, Cache interval failure, storage interval failure, etc.); pure numerical data such as wafer yield data.

[0098] The method for obtaining the original data is similar to the method for obtaining the first type of data in the above text, and can be seen in the above description. For the sake of brevity, it will not be repeated here.

[0099] In step S702, based on the original data and the pre - constructed target knowledge graph, determine the wafer yield analysis result and / or the decision corresponding to the wafer yield.

[0100] The pre - constructed target knowledge graph is constructed based on the construction method of the target knowledge graph described above. For the specific construction method, please refer to the above description. For the sake of brevity, it will not be elaborated here.

[0101] The yield analysis result of the wafer includes information, the failure information of the die, or the root cause corresponding to the defect of the wafer and / or the failure information of the die.

[0102] The raw data may include data on the state of the equipment obtained by sensors during production, such as but not limited to: temperature, humidity, pressure, voltage, current, etc.; data obtained by defect detection of the wafer during the production process; data obtained by electrical testing of the wafer during the production process; data on the failure type (bin) obtained by the final yield detection of the wafer, which may include failure types such as calculation unit interval failure, Cache interval failure, storage interval failure, etc.

[0103] The raw data is a structured numerical sequence. Semantic recognition is performed on it to obtain the corresponding descriptive text. For the specific semantic recognition method, please refer to the above description. For the sake of brevity, it will not be elaborated here.

[0104] Extract the entities in the descriptive text. Based on the entity and the target knowledge graph, predict the defects of the wafer and the root cause corresponding to the defect.

[0105] For example, if the extracted entity is "SNR has a large shift", then according to the target knowledge graph, it can be predicted that the corresponding defect is TiN Paricle, the failure category is IB20, and the root cause is that the equipment TAD is offline due to the stepprocess delay of Step1 of the equipment TAD.

[0106] It can be understood that the meaning of the decision corresponding to the wafer yield mentioned in the embodiments of the present invention is the operation made for the wafer yield problem. For example, when the wafer yield meets the requirements, the wafer production is carried out according to the existing process. When the wafer yield is lower than the requirements, the existing process is improved, such as changing the manufacturing steps of the wafer, changing the temperature or humidity of the wafer manufacturing, etc., so as to improve the wafer yield to meet the requirements.

[0107] That is to say, according to the semiconductor manufacturing yield analysis method based on the knowledge graph proposed by the present invention, the root cause of the wafer yield and the next decision can also be inferred based on the target knowledge graph. For example, Figure 5Among them, the entity discovered through raw data extraction is "SNR has large shift", which causes "SNR defect" and "IB20 failure category". To solve this defect and failure, the next decision, that is, the operation, is: "QnR dispo this lot" and "Set up the model and prevent action".

[0108] An embodiment of the present invention further provides a computing device, including at least one processor, a memory, and a communication interface, where the processor is configured to execute Figure 3 the method described in item 6 or 7. This computing device can be a server or a terminal device.

[0109] Figure 8 It is a schematic structural diagram of the computing device provided by the embodiment of the present invention.

[0110] As Figure 8 shown, the computing device 800 includes at least one processor 801, a memory 802, and a communication interface 803. Among them, the processor 801, the memory 802, and the communication interface 803 are communicatively connected and can be communicatively implemented by wireless or wired means. The communication interface 803 is configured to receive user instructions or information sent by the acquisition device; the memory 802 stores computer instructions, and the processor 801 executes the computer instructions to execute the method in the foregoing method embodiment.

[0111] It should be understood that in the embodiment of the present invention, the processor 801 may be a central processing unit CPU, and the processor 801 may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0112] The memory 802 may include a read-only memory and a random access memory and provide instructions and data to the processor 801. The memory 802 may also include a non-volatile random access memory.

[0113] The memory 802 can be a volatile memory, a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0114] It should be understood that the computing device 800 according to an embodiment of the present invention can execute to implement the embodiments of the present invention Figure 3 or the method shown in FIG. 7. For a detailed description of the implementation of this method, please refer to the above. For the sake of brevity, it will not be repeated here.

[0115] An embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer instructions are executed by a processor, the method mentioned above is implemented.

[0116] An embodiment of the present invention provides a computer program or a computer program product. The computer program or the computer program product includes instructions. When the instructions are executed, the computer is made to execute the method mentioned above.

[0117] Those of ordinary skill in the art should also be further aware that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0118] The steps of the methods or algorithms described in combination with the embodiments disclosed herein can be implemented by hardware, software modules executed by a processor, or a combination of the two. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0119] The specific embodiments described above further elaborate on the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for constructing a knowledge graph for semiconductor manufacturing yield analysis, characterized in that, Including: Obtain target data related to semiconductor manufacturing; the target data includes at least one of first-class data, second-class data, and third-class data. The first-class data includes a numerical sequence related to the manufacturing equipment of the semiconductor and / or related to the semiconductor. The second-class data includes experience documents generated by engineers analyzing the data generated during the semiconductor production process. The third-class data is a document related to the manufacturing equipment of the semiconductor, including one or more of the usage instruction information, fault information, and repair information corresponding to the fault of the manufacturing equipment. Perform knowledge extraction on the target data to obtain entities related to semiconductor manufacturing and the relationships therebetween. Construct a target knowledge graph related to semiconductor manufacturing with the entities as nodes and the relationships as connecting edges. The target knowledge graph is used to analyze the semiconductor yield and / or determine the decision corresponding to the semiconductor yield.

2. The method according to claim 1, characterized in that, The first-class data is structured data. Before performing the knowledge extraction on the target data to obtain entities related to semiconductor manufacturing and the relationships therebetween, it further includes: Perform semantic recognition on the numerical sequence to obtain a description text corresponding to the numerical sequence, and the description text describes the abnormal information corresponding to the numerical sequence.

3. The method according to claim 2, characterized in that, Performing semantic recognition on the numerical sequence to obtain a description text corresponding to the numerical sequence includes: Match a corresponding description text for the numerical sequence according to a preset rule template.

4. The method according to claim 2, characterized in that, Performing semantic recognition on the numerical sequence to obtain a description text corresponding to the numerical sequence includes: Input the numerical sequence into a trained semantic recognition model to obtain a description text corresponding to the numerical sequence.

5. The method according to any one of claims 1-4, characterized in that, The target knowledge graph is updated at a preset period to update the nodes and connecting edges in the target knowledge graph.

6. The method according to any one of claims 1-4, characterized in that, The entities include event-type entities and object-type entities. The event-type entities include one or more of the following: equipment event, failure type event, production step event, yield event, statistical process control event. The object-type entities include one or more of the following: defect detection layer object, equipment object, defect object, failure type object, production step object.

7. A semiconductor manufacturing yield analysis method based on a knowledge graph, characterized in that, Including: Obtain raw data related to semiconductor manufacturing, and the raw data includes data related to the manufacturing of the semiconductor. Based on the raw data and the target knowledge graph as described in any one of claims 1-6 pre-constructed, determine the yield analysis result of the semiconductor and / or the decision corresponding to the yield of the semiconductor. The yield analysis result of the semiconductor includes one or more of the defect information of the wafer, the failure information of the die, and the root cause corresponding to the defect and / or failure information of the wafer and / or die.

8. An apparatus for constructing a knowledge graph for semiconductor manufacturing yield analysis, characterized in that, Including: An acquisition device, configured to acquire target data related to semiconductor manufacturing; the target data includes at least one of a first type of data, a second type of data, and a third type of data, the first type of data includes a numerical sequence related to the manufacturing equipment of the semiconductor and / or related to the semiconductor; the second type of data includes an experience document generated by an engineer analyzing the data generated during the semiconductor production process, and the third type of data is a document related to the manufacturing equipment of the semiconductor, including one or more of usage instruction information, fault information, and repair information corresponding to the fault of the manufacturing equipment; An extraction device, configured to perform knowledge extraction on the target data to obtain entities related to semiconductor manufacturing and the relationships therebetween; A construction device, configured to construct a target knowledge graph related to semiconductor manufacturing with the entities as nodes and the relationships as connection edges; The target knowledge graph is used to analyze the semiconductor yield and / or determine the decision corresponding to the semiconductor yield.

9. A computer-readable storage medium, on which a computer program is stored, characterized in that, When the computer program is executed on a computer, the computer is caused to execute the method according to any one of claims 1-7.

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