Semiconductor memory device and method of operating a semiconductor memory device

Abstract

Semiconductor memory devices and methods of operating semiconductor memory devices are provided herein. A semiconductor memory device can include an array of memory cells, a peripheral circuit, and control logic. The array of memory cells can include a plurality of memory cells. The peripheral circuit can perform a program operation on selected memory cells among the plurality of memory cells coupled with a selected word line. The control logic can control the program operation of the peripheral circuit. The program operation can include a plurality of program loops. Each program loop of the plurality of program loops can include a program phase and a verify phase. The verify phase can include one or more verify operations. The control logic can also be configured to count, during the program operation, a number of verify operations performed by the peripheral circuit in the verify phase included in one of the plurality of program loops.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0007394, filed on January 19, 2021, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] Various embodiments of the present disclosure generally relate to electronic devices, and more particularly to semiconductor memory devices and methods of operating semiconductor memory devices. BACKGROUND

[0004] Semiconductor memory devices can have a two-dimensional (2D) structure in which strings are arranged horizontally on a semiconductor substrate. Alternatively, semiconductor memory devices can have a three-dimensional (3D) structure in which strings are vertically stacked on a semiconductor substrate. As memory devices having a 2D structure are reaching their physical scaling limit (i.e., limit of integration), 3D memory devices including a plurality of memory cells vertically stacked on a semiconductor substrate have been produced. SUMMARY

[0005] Various embodiments of the present disclosure relate to semiconductor memory devices and methods of operating semiconductor memory devices that can enhance reliability of a program operation.

[0006] One embodiment of the present disclosure can provide a semiconductor memory device. The semiconductor memory device can include a memory cell array, a peripheral circuit, and a control logic. The memory cell array can include a plurality of memory cells. The peripheral circuit can be configured to perform a program operation on a selected memory cell among the plurality of memory cells coupled with a selected word line. The control logic can be configured to control the program operation of the peripheral circuit. The program operation can include a plurality of program loops. Each program loop of the plurality of program loops can include a program phase and a verify phase. The verify phase can include one or more verify operations. The control logic can be further configured to count a number of the verify operations performed by the peripheral circuit in the verify phase included in one program loop of the plurality of program loops during the program operation.

[0007] One embodiment of the present disclosure can provide a method of operating a semiconductor memory device including a plurality of memory cells. The method can include performing a program operation to program memory cells among the plurality of memory cells coupled with a selected word line. The program operation includes a plurality of program loops, and each program loop of the plurality of program loops can include applying a program voltage to the selected word line, performing one or more verify operations corresponding to one or more program states, respectively, on the memory cells coupled with the selected word line, and counting a number of the performed verify operations.

[0008] One embodiment of the present disclosure can provide a semiconductor memory device. The semiconductor memory device can include a memory cell array, a peripheral circuit, and a control logic. The memory cell array can include a plurality of memory cells. The peripheral circuit can be configured to perform a program operation on a selected memory cell coupled with a selected word line among the plurality of memory cells. The control logic can be configured to control the program operation of the peripheral circuit. The program operation can include a plurality of program loops. Each program loop of the plurality of program loops can include a program phase and a verify phase. The verify phase can include one or more verify operations. The control logic can include a verify operation counter, a maximum verify operation number storage, and an over-verify operation detector. The verify operation counter can be configured to count a number of verify operations performed by the peripheral circuit in one program loop of the plurality of program loops during the program operation. The maximum verify operation number storage can be configured to store a maximum verify operation number. The over-verify operation detector can be configured to compare the number of verify operations performed in the program loop with the maximum verify operation number and determine whether the program operation has succeeded based on a result of the comparison.

[0009] One embodiment of the present disclosure can provide a method of operating a semiconductor memory device. The method can include performing a program operation of one or more loop operations on a selected memory cell, each loop operation of the loop operations being configured by a program voltage application operation and one or more verify operations for one or more target program states, respectively, and determining the program operation as failed when a number of verify operations within one loop operation of the loop operations becomes greater than a threshold value. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a block diagram illustrating a semiconductor memory device according to one embodiment of the present disclosure.

[0011] Figure 2 is a block diagram illustrating a memory cell array of Figure 1 according to one embodiment of the present disclosure.

[0012] Figure 3 is a circuit diagram illustrating a memory block BLKa in the memory blocks BLK1 to BLKz of Figure 2 according to one embodiment of the present disclosure.

[0013] Figure 4 is a circuit diagram illustrating one example of a memory block BLKb in the memory blocks BLK1 to BLKz of Figure 2 according to one embodiment of the present disclosure.

[0014] Figure 5is a circuit diagram illustrating one example of a memory block BLKc among memory blocks BLK1 to BLKz included in the memory cell array 110 according to one embodiment of the present disclosure. Figure 1

[0015] Figure 6 is a diagram illustrating a plurality of program loops included in a program operation and a program phase and a verify phase included in each program loop according to one embodiment of the present disclosure.

[0016] Figure 7 is a graph illustrating a threshold voltage distribution of a multi-level cell (MLC).

[0017] Figure 8 is a graph illustrating a threshold voltage distribution of a triple-level cell (TLC).

[0018] Figure 9 is a diagram illustrating a program voltage applied in a program phase and a verify voltage applied in a verify phase according to one embodiment of the present disclosure.

[0019] Figure 10 is a diagram illustrating a program voltage and a verify voltage of Figure 9 according to one embodiment of the present disclosure.

[0020] Figure 11 is a diagram illustrating the control logic 140 illustrated in Figure 1 according to one embodiment of the present disclosure.

[0021] Figure 12 is a flowchart illustrating a method of operating a semiconductor memory device according to one embodiment of the present disclosure.

[0022] Figure 13A and Figure 13B is a diagram illustrating a method of operating a semiconductor memory device according to one embodiment of the present disclosure.

[0023] Figure 14A and Figure 14B is a diagram illustrating a method of operating a semiconductor memory device according to one embodiment of the present disclosure.

[0024] Figure 15 is a block diagram illustrating a memory system of a semiconductor memory device including Figure 1 according to one embodiment of the present disclosure.

[0025] Figure 16 is a block diagram illustrating an example of an application of the memory system of Figure 15 according to one embodiment of the present disclosure.

[0026] Figure 17 ​is a block diagram illustrating a semiconductor memory device including a reference Figure 16 a block diagram of a computing system of the memory system described. DETAILED DESCRIPTION

[0027] The specific configurations or functional descriptions of the embodiments of the disclosure introduced in the present specification or application are disclosed to describe the embodiments according to the concept of the disclosure. The embodiments according to the concept of the disclosure can be practiced in various forms, and should not be interpreted as being limited to the embodiments described in the specification.

[0028] Figure 1 is a block diagram illustrating a semiconductor memory device according to one embodiment of the disclosure.

[0029] Referring to Figure 1 , the semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read and write circuit 130, control logic 140, a voltage generator 150, and a current sensing circuit 160.

[0030] The memory cell array 110 can include a plurality of memory blocks BLK1 to BLKz. The memory blocks BLK1 to BLKz are coupled to the address decoder 120 through word lines WL. The memory blocks BLK1 to BLKz are coupled to the read and write circuit 130 through bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz includes a plurality of memory cells. In one embodiment, the plurality of memory cells can be non-volatile memory cells, and can be implemented as non-volatile memory cells having a vertical channel structure. The memory cell array 110 can be implemented as a memory cell array having a two-dimensional (2D) structure. In one embodiment, the memory cell array 110 can be implemented as a memory cell array having a three-dimensional (3D) structure. Further, each memory cell included in the memory cell array can store at least one bit of data. In one embodiment, each memory cell included in the memory cell array 110 can be a single-level cell (SLC) storing 1 bit of data. In one embodiment, each memory cell included in the memory cell array 110 can be a multi-level cell (MLC) storing 2 bits of data. In one embodiment, each memory cell included in the memory cell array 110 can be a triple-level cell (TLC) storing 3 bits of data. In one embodiment, each memory cell included in the memory cell array 110 can be a quad-level cell (QLC) storing 4 bits of data. According to one embodiment, the memory cell array 110 can include a plurality of memory cells each of which stores 5 bits or more of data.

[0031] The address encoder 120 is coupled to the memory cell array 110 via word lines WL. The address decoder 120 can operate under the control of control logic 140. The address decoder 120 receives addresses via input / output buffers (not shown) provided in the semiconductor memory device 100.

[0032] Address decoder 120 can decode the block address in the received address. Address decoder 120 selects at least one memory block based on the decoded block address. Furthermore, when a read voltage application operation is performed during a read operation, address decoder 120 can apply the read voltage Vread generated by voltage generator 150 to the selected word line of the selected memory block, and can apply the pass voltage Vpass to the remaining word lines, i.e., the unselected word lines. Additionally, during a program verification operation, address decoder 120 can apply the verification voltage generated by voltage generator 150 to the selected word line of the selected memory block, and can apply the pass voltage Vpass to the remaining word lines, i.e., the unselected word lines.

[0033] Address decoder 120 can decode the column address in the received address. Address decoder 120 can transmit the decoded column address to read and write circuit 130.

[0034] Read and programming operations of the semiconductor memory device 100 are each performed on a page basis. Addresses received in response to requests for read and programming operations may include block addresses, row addresses, and column addresses. Address decoder 120 can select a memory block and a word line based on the block address and row address. The column address can be decoded by address decoder 120 and then provided to read and write circuitry 130. In this specification, a memory cell coupled to a word line may be referred to as a "physical page".

[0035] The read and write circuit 130 includes multiple page buffers PB1 to PBm. The read and write circuit 130 can be operated as a "read circuit" during a read operation of the memory cell array 110 and as a "write circuit" during its write operation. The multiple page buffers PB1 to PBm are coupled to the memory cell array 110 via bit lines BL1 to BLm. To sense the threshold voltage of the memory cell during read and program verification operations, each page buffer PB1 to PBm can sense changes in the amount of current flowing relative to the programming state of the corresponding memory cell via a sensing node, and latches the sensed changes as sensed data while continuously providing a sensed current to the bit line coupled to the memory cell. The read and write circuit 130 operates in response to a page buffer control signal output from control logic 140. In this specification, the write operation of the write circuit can be used to have the same meaning as a programming operation performed on a selected memory cell.

[0036] During a read operation, the read and write circuitry 130 can sense the data stored in the memory cell and temporarily store the read data, and then output the data DATA to the input / output buffer (not shown) of the semiconductor memory device 100. In one embodiment, the read and write circuitry 130 may include column select circuitry, a page buffer (or page register), etc.

[0037] Control logic 140 can be coupled to address decoder 120, read and write circuitry 130, and current sensing circuitry 160. Control logic 140 can receive commands CMD and control signals CTRL via input / output buffers (not shown) of semiconductor memory device 100. Control logic 140 can control the overall operation of semiconductor memory device 100 in response to control signal CTRL. Control logic 140 can output control signals for controlling the precharge potential levels at sensing nodes of multiple page buffers PB1 to PBm. Control logic 140 can control read and write circuitry 130 to perform read operations on memory cell array 110.

[0038] In addition, control logic 140 can determine whether a verification operation corresponding to a specific target programming state has passed or failed in response to a pass or fail signal PASS or FAIL received from current sensing circuit 160.

[0039] Voltage generator 150 can generate a read voltage Vread and a pass voltage Vpass for a read operation in response to a control signal output from control logic 140. Voltage generator 150 may include a plurality of pump capacitors for receiving an internal supply voltage to generate a plurality of voltages having various voltage levels, and voltage generator 150 can generate a plurality of voltages by selectively activating the plurality of pump capacitors under the control of control logic 140.

[0040] During the verification operation, the current sensing circuit 160 can generate a reference current in response to the enable bit VRY_BIT<#> received from the control logic 140, and can compare the reference voltage generated by the reference current with the sensed voltage VPB received from the page buffers PB1 to PBm included in the read and write circuit 130, and then output a pass signal PASS or a failure signal FAIL.

[0041] The address decoder 120, read and write circuitry 130, voltage generator 150, and current sensing circuitry 160 can be used as peripheral circuitry to perform read, write, and erase operations on the memory cell array 110. The peripheral circuitry can perform read, write, and erase operations on the memory cell array 110 under the control of control logic 140.

[0042] According to one embodiment of this disclosure, during programming operations of a semiconductor memory device 100, control logic 140 can count the number of verification operations performed in each programming cycle (i.e., verification operation count) and compare the counted number with a set maximum number of verification operations (i.e., a set maximum verification operation count). When the number of verification operations performed in a programming cycle is greater than the maximum number of verification operations, control logic 140 can determine that programming has failed. Conversely, when the number of verification operations performed in a programming cycle is less than or equal to the maximum number of verification operations, control logic 140 can control the peripheral circuitry to proceed to a subsequent programming cycle. Therefore, it is expected that programming failures due to defects in the selected word lines can be detected, which may result in a higher-than-expected increase in the threshold voltage.

[0043] Figure 2 The illustration shows an embodiment according to the present disclosure. Figure 1 Block diagram of memory cell array 110.

[0044] refer to Figure 2The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. Each memory block has a three-dimensional (3D) structure. Each memory block may include multiple memory cells stacked on a substrate. The multiple memory cells are arranged in the +X, +Y, and +Z directions. Reference will be made below. Figure 3 and Figure 4 To describe the structure of each memory block in more detail.

[0045] Figure 3 The illustration shows an embodiment according to the present disclosure. Figure 2 The circuit diagram of memory block BLKa in memory blocks BLK1 to BLKz.

[0046] refer to Figure 3 The memory block BLKa may include multiple cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings may be arranged in the row direction (i.e., the positive (+)X direction). Figure 3 In the diagram, two unit strings are illustrated as being arranged in the column direction (i.e., the positive (+) Y direction). However, this illustration is for ease of description, and it can be understood that three or more unit strings can be arranged in the column direction.

[0047] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0048] The select transistors SST and DST, and the memory cells MC1 to MCn, can have similar structures. In one embodiment, each of the select transistors SST and DST, and the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. In one embodiment, pillars for providing the channel layer may be provided in each cell string. In another embodiment, pillars for providing at least one of the channel layer, tunneling insulating layer, charge storage layer, and barrier insulating layer may be provided in each cell string.

[0049] The source selection transistor SST of each cell string is coupled between the common source line CSL and the memory cells MC1 to MCp.

[0050] In one embodiment, source-select transistors of cell strings arranged in the same row are coupled to source-select lines extending in the row direction, and source-select transistors of cell strings arranged in different rows are coupled to different source-select lines. Figure 3 In the first row, the source selection transistors of cell strings CS11 to CS1m are coupled to the first source selection line SSL1. In the second row, the source selection transistors of cell strings CS21 to CS2m are coupled to the second source selection line SSL2.

[0051] In one embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be co-coupled to a single source selection line.

[0052] The first to nth memory cells MC1 to MCn in each cell string are coupled between the source selection transistor SST and the drain selection transistor DST.

[0053] The first to nth memory cells MC1 to MCn can be divided into the first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp are arranged sequentially in the direction opposite to the positive (+)Z direction and are coupled in series between the source selection transistor SST and the channel transistor PT. The (p+1)th to nth memory cells MCp+1 to MCn are arranged sequentially in the +Z direction and are coupled in series between the channel transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn are coupled to each other through the channel transistor PT. The gates of the first to nth memory cells MC1 to MCn in each cell string are respectively coupled to the first to nth word lines WL1 to WLn.

[0054] The gate of the pipe transistor PT in each unit string is coupled to the pipe PL.

[0055] The drain select transistor (DST) of each cell string is coupled between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged in the row direction are coupled to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are coupled to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are coupled to the second drain select line DSL2.

[0056] A string of cells arranged in the column direction can be coupled to a bit line extending in the column direction. Figure 3In the first column, the cell strings CS11 and CS21 are coupled to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column are coupled to the m-th bit line BLm.

[0057] In a row-oriented cell string, memory cells coupled to the same word line form a single page. For example, in the cell strings CS11 to CS1m in the first row, memory cells coupled to the first word line WL1 form a single page. In the cell strings CS21 to CS2m in the second row, memory cells coupled to the first word line WL1 form another single page. Cell strings arranged in a single row direction can be selected by choosing one of the drain select lines DSL1 and DSL2. A page can be selected from the selected cell string by selecting one of the word lines WL1 to WLn.

[0058] In one embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first to m-th bit lines BL1 to BLm. Even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be coupled to the corresponding even-numbered bit lines. Odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be coupled to the corresponding odd-numbered bit lines.

[0059] In one embodiment, one or more memory cells from the first to the nth memory cells MC1 to MCn can be used as dummy memory cells. For example, one or more dummy memory cells are provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, one or more dummy memory cells are provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. As the number of dummy memory cells provided increases, the operational reliability of the memory block BLKa can be improved, while the size of the memory block BLKa may be increased. As the number of dummy memory cells provided decreases, the size of the memory block BLKa can be reduced, while the operational reliability of the memory block BLKa may deteriorate.

[0060] To efficiently control one or more dummy memory cells, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation is performed on the memory block BLKa. When an erase operation is performed after a programming operation has been performed, the dummy memory cell can have a desired threshold voltage by controlling the voltage applied to the dummy word line coupled to the dummy memory cell.

[0061] Figure 4 The illustration shows an embodiment according to the present disclosure. Figure 2A circuit diagram of an example memory block BLKb in memory blocks BLK1 to BLKz.

[0062] refer to Figure 4 The memory block BLKb may include multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' extends along the positive Z (+Z) direction. Each of the cell strings CS11' to CS1m' and CS21' to CS2m' may include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) below the memory block BLKb.

[0063] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. Source select transistors of cell strings arranged in the same row are coupled to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are coupled to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are coupled to the second source select line SSL2. In one embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' may be commonly coupled to a single source select line.

[0064] The first to nth memory cells MC1 to MCn in each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first to nth memory cells MC1 to MCn are respectively coupled to the first to nth word lines WL1 to WLn.

[0065] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged in the row direction are coupled to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are coupled to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are coupled to the second drain select line DSL2.

[0066] As a result, in addition to the pipe transistor PT being removed from each cell string, Figure 4 The memory block BLKb has similar characteristics to Figure 3 The equivalent circuit of the memory block BLKa.

[0067] In one embodiment, even-numbered bit lines and odd-numbered bit lines can be provided in place of the first to m-th bit lines BL1 to BLm. Furthermore, even-numbered cell strings in the row-direction cell strings CS11' to CS1m' or CS21' to CS2m' can be coupled to even-numbered bit lines, while odd-numbered cell strings in the row-direction cell strings CS11' to CS1m' or CS21' to CS2m' can be coupled to odd-numbered bit lines.

[0068] In one embodiment, one or more of the first to nth memory cells MC1 to MCn can be used as dummy memory cells. For example, one or more dummy memory cells are provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, one or more dummy memory cells are provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. With more dummy memory cells provided, the operational reliability of the memory block BLKb is improved, but the size of the memory block BLKb increases. With fewer memory cells provided, the size of the memory block BLKb decreases, but the operational reliability of the memory block BLKb may deteriorate.

[0069] To efficiently control one or more dummy memory cells, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after the erase operation of memory block BLKb. When the erase operation is performed after the programming operation has been performed, the dummy memory cells can have the desired threshold voltage by controlling the voltage to be applied to the dummy word line coupled to the corresponding dummy memory cell.

[0070] Figure 5 The illustration shows an embodiment of the present disclosure. Figure 1 A circuit diagram of an example memory block BLKc among memory blocks BLK1 to BLKz included in the memory cell array 110.

[0071] refer to Figure 5 The memory block BLKc may include multiple cell strings CS1 to CSm. The multiple cell strings CS1 to CSm may be coupled to multiple bit lines BL1 to BLm respectively. Each cell string CS1 to CSm includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn and at least one drain selection transistor DST.

[0072] The select transistors SST and DST, and the memory cells MC1 to MCn, can have similar structures. In one embodiment, each of the select transistors SST and DST, and the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. In one embodiment, pillars for providing the channel layer may be provided in each cell string. In another embodiment, pillars for providing at least one of the channel layer, tunneling insulating layer, charge storage layer, and barrier insulating layer may be provided in each cell string.

[0073] The source selection transistor SST of each cell string is coupled between the common source line CSL and the memory cells MC1 to MCn.

[0074] The first to nth memory cells MC1 to MCn in each cell string are coupled between the source selection transistor SST and the drain selection transistor DST.

[0075] The drain selection transistor (DST) of each cell string is coupled between the corresponding bit line and the memory cells MC1 to MCn.

[0076] Memory cells coupled to the same word line can form a single page. Cell strings CS1 to CSm can be selected by selecting the drain select line DSL. A page can be selected from the selected cell string by selecting one of the word lines WL1 to WLn.

[0077] In other embodiments, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first to m-th bit lines BL1 to BLm. Among the unit strings CS1 to CSm, even-numbered unit strings can be coupled to even-numbered bit lines respectively, and odd-numbered unit strings can be coupled to odd-numbered bit lines respectively.

[0078] As described above, a memory cell coupled to a word line can form a physical page. Figure 5 In the example, within the memory cells belonging to memory block BLKc, m memory cells coupled to one of the multiple word lines WL1 to WLn form a physical page.

[0079] The memory cell array 110 of the semiconductor memory device 100 can be configured as follows: Figure 2 to Figure 4 The 3D structure shown can be configured as follows: Figure 5 The 2D structure shown.

[0080] Figure 6 This is a diagram illustrating a plurality of programming loops included in a programming operation according to an embodiment of the present disclosure, and a programming phase and a verification phase included in each programming loop.

[0081] refer toFigure 6 Programming operations can include multiple programming loops. For example... Figure 6 As shown, programming operations can be performed by executing the first programming loop (1 st The PGM Loop is started. Even if the first programming loop (1) is started. st When the PGM Loop has been executed and the programming operation performed on the selected memory cell has not been completed, the second programming loop (2) will begin. nd The PGM Loop can be executed. Even if the second programming loop (2) nd When the PGM Loop has been executed and the programming operation on the selected memory cell has not been completed, the third programming loop (3) is executed. rd The PGM Loop can be executed. In this way, the programming loop can be repeated until the programming operation is complete.

[0082] However, if the programming operation has not been completed even after the same number of programming loops as the maximum number of programming loops set has been repeated, it can be determined that the programming operation has failed.

[0083] Figure 7 This is a graph illustrating the threshold voltage distribution of a multi-level cell (MLC) according to an embodiment of the present disclosure. In one embodiment of the present disclosure, in Figure 1 The memory cells included in the memory cell array 110 may include those having Figure 7 The threshold voltage distribution shown is a multi-level unit.

[0084] refer to Figure 7 The diagram illustrates the threshold voltage distribution of a multi-level cell, where each cell stores 2 bits of data. Each multi-level cell can have a threshold voltage corresponding to one of the erase state E, the first programming state P1, the second programming state P2, and the third programming state P3. Therefore, to read the data stored in the multi-level cell, a first read voltage R1, a second read voltage R2, and a third read voltage R3 can be used.

[0085] During the programming operation, a first verification voltage VR1 can be used to verify the threshold voltage of the memory cell to be programmed to the first programming state P1. Furthermore, a second verification voltage VR2 can be used to verify the threshold voltage of the memory cell to be programmed to the second programming state P2. Finally, a third verification voltage VR3 can be used to verify the threshold voltage of the memory cell to be programmed to the third programming state P3.

[0086] Figure 8 This is a graph illustrating the threshold voltage distribution of a three-level cell (TLC) according to one embodiment of the present disclosure. In one embodiment of the present disclosure,Figure 1 The memory cells included in the memory cell array 110 may include those having Figure 8 The three-level unit of the threshold voltage distribution is shown.

[0087] refer to Figure 8 The three-level cell (TLC) has eight threshold voltage states. The threshold voltage states of the three-level cell (TLC) include the erase state E and the first to seventh target programming states P1 to P7.

[0088] like Figure 8 As shown, the corresponding threshold voltage states can be identified based on the first to seventh read voltages R1 to R7. Furthermore, during the programming operation, the first to seventh verification voltages VR1 to VR7 can be used to determine whether the programming of the memory cells corresponding to programming states P1 to P7 has been completed.

[0089] exist Figure 7 and Figure 8 The diagram illustrates the target programming states for multi-level and three-level cells. However, this is only an example, and in other embodiments of this disclosure, the memory cell array 110 may include a four-level cell (QLC). Hereinafter, this disclosure will be described based on programming operations performed on a three-level cell (TLC). However, this disclosure is not limited thereto, and it can also be applied to programming multi-level cells, four-level cells, or memory cells storing 5 or more bits of data.

[0090] Figure 9 This is a diagram illustrating a programming voltage applied during the programming phase and a verification voltage applied during the verification phase, according to an embodiment of the present disclosure.

[0091] refer to Figure 9 The diagram illustrates the voltage applied to a selected word line in one of a plurality of programming cycles. During the programming phase included in the programming cycle, a programming voltage VP is applied to the selected word line. During the verification phase included in the programming cycle, at least one verification voltage may be applied to the selected word line. Figure 9 The illustration shows an embodiment in which a first verification voltage VR1 and a second verification voltage VR2 are sequentially applied to selected word lines during the verification phase. Figure 9 The illustration shows an embodiment where the first verification voltage VR1 and the second verification voltage VR2 are negative voltages. However, this is only an example, and the first verification voltage VR1 and the second verification voltage VR2 can be positive voltages.

[0092] exist Figure 9 The diagram only depicts the voltage applied to the selected word lines, and omits illustrations of the voltage applied to the unselected word lines. Although Figure 9Not illustrated, but a programming pass voltage can be applied to an unselected word line during the programming phase, and a verification pass voltage can be applied to an unselected word line during the verification phase. The programming pass voltage can be a voltage less than the programming voltage VP. The verification pass voltage can be a voltage greater than the first verification voltage VR1 and the second verification voltage VR2.

[0093] Figure 10 A detailed illustration is provided of an embodiment according to this disclosure. Figure 9 The diagram shows the programming voltage and the verification voltage.

[0094] refer to Figure 10 Under normal circumstances, the voltage applied to the selected word line is represented by a solid line, while under defective circumstances, the voltage applied to the selected word line is represented by a dashed line. First, the programming operations performed under normal circumstances will be described below.

[0095] At time t1, the programming pass voltage Vpass can be applied to the selected word line. At this time, the programming pass voltage Vpass can also be applied to the unselected word line. Subsequently, at time t2, the programming voltage VP can be applied to the selected word line. At this time, the voltage of the unselected word line can be maintained at the programming pass voltage Vpass. Until time t3, the programming voltage VP applied to the selected word line can be maintained. Therefore, during the period from time t2 to time t3, the threshold voltage of the memory cell coupled to the bit line to which the programming enable voltage is applied can increase among the memory cells coupled to the selected word line. During the period from time t2 to time t3, the threshold voltage of the memory cell coupled to the bit line to which the programming disable voltage is applied among the memory cells coupled to the selected word line can not increase.

[0096] At time t3, the voltage of the selected word line begins to decrease. Further, at time t4, the decrease in the voltage of the selected word line can end. Therefore, the programming phase of one programming cycle is complete. That is, as... Figure 10 As shown, the time period from time t1 to time t4 can correspond to Figure 6 The programming stage is shown.

[0097] Subsequently, at time t5, the verification phase is initiated. Therefore, at time t5, the voltage of the selected word line can be reduced to the first verification voltage VR1. During the period from time t5 to time t6, the verification operation can be performed on the memory cell to be programmed to the first programming state P1. Subsequently, at time t6, the voltage of the selected word line can be increased to the second verification voltage VR2. During the period from time t6 to time t7, the verification operation can be performed on the memory cell to be programmed to the second programming state P2. Subsequently, the voltage of the selected word line begins to increase at time t7 and can be increased to a reference voltage, such as ground voltage (0V), at time t8. Therefore, at time t8, the verification phase terminates.

[0098] exist Figure 10 The diagram illustrates an embodiment in which verification operations corresponding to the first programming state P1 and the second programming state P2 are performed, respectively, using only the first and second verification voltages VR1 and VR2, within a programming cycle. However, as the programming cycle repeats, the target of the verification operations to be performed during the verification phase may change. When the verification operation corresponding to the first programming state P1 has been completed in a particular programming cycle, the verification operation corresponding to the first programming state P1 may not be performed in subsequent programming cycles. When the set programming cycle is reached, the verification operation corresponding to the third programming state P3 can be re-executed. The programming cycle in which the verification operation corresponding to the corresponding programming state is to be performed can be set. This will be referred to later. Figure 14A and Figure 14B Let me describe it in detail.

[0099] like Figure 10 As shown by the solid line, under normal conditions, the voltage of the selected word line changes rapidly, and therefore programming operations can be performed as expected. However, in defective cases, the resistance of the word line increases, and therefore programming operations may not be performed as expected. That is, when the resistance of the selected word line increases due to a resistance defect in the selected word line, as... Figure 10 As shown by the dashed line, the rise rate of the selected word line voltage decreases. Therefore, the rise rate of the threshold voltage of the selected memory cell may decrease, and consequently, the number of programming loop repetitions may increase. This could be the reason for the reduced overall programming speed.

[0100] Furthermore, in the first programming state P1, which is a lower state corresponding to the negative verification voltage, the time required to stabilize the word line voltage is insufficient, and therefore the level of the actually applied verification voltage may increase. It can be seen that in... Figure 10During the time interval t5 to t6, the verification voltage actually applied under defective conditions is greater than the verification voltage under normal conditions. This indicates that the verification of memory cells that have successfully completed programming operations based on the first verification voltage VR1 is determined to have failed. Therefore, the total number of programming cycle repetitions may increase. Typically, when programming of a memory cell to be programmed to the highest programming state (i.e., the seventh programming state P7 in the TLC case) has been completed, the entire programming operation can be determined to have passed.

[0101] Therefore, based on the seventh programming state P7, the programming operation is identified as successful. However, due to the increase in the first verification voltage VR1, the threshold voltage of the memory cell corresponding to the first programming state P1 may also increase, which may lead to read failure in subsequent read operations.

[0102] According to embodiments of the semiconductor memory device 100 and the method of operating the semiconductor memory device 100 of the present disclosure, during programming operations, control logic 140 can count the number of verification operations performed in each programming cycle and compare the counted number with a set maximum number of verification operations. When the number of verification operations in each programming cycle is greater than the maximum number of verification operations, control logic 140 can determine that the programming operation has failed. Conversely, when the number of verification operations in a programming cycle is less than or equal to the maximum number of verification operations, control logic 140 can control the peripheral circuitry to proceed to a subsequent programming cycle. Therefore, it is expected that a programming failure due to a defect in the selected word line can be detected, which may result in a higher-than-expected increase in the threshold voltage.

[0103] Figure 11 The illustration shows an embodiment according to the present disclosure. Figure 1 The diagram shows the control logic 140.

[0104] refer to Figure 11 The control logic 140 may include a verification operation counter 141, a maximum number of verification operations storage device 143, and an over-verification operation detector 145. The verification operation counter 141 can store the number N of verification operations executed in each programming loop. VP The count is performed. The verification operation counter 141 can count the number N verification operations executed in each programming loop. VP The data is transmitted to the overvalidation operation detector 145. The maximum number of validation operations storage device 143 can store the set maximum number of validation operations MAX. VP (That is, the maximum number of verification operations). The maximum number of verification operations storage device 143 can store the maximum number of verification operations MAX. VPThe data is transmitted to the overvalidation operation detector 145. The overvalidation operation detector 145 will record the number N of validation operations executed in each programming loop. VP MAX with maximum number of verification operations VP Compare the number N of verification operations performed in the current programming loop. VP Greater than the maximum number of verification operations (MAX) VP When the number N verification operations performed in the current programming loop has failed, the overvalidation operation detector 145 can determine that the programming operation has failed. VP Less than the maximum number of verification operations (MAX) VP At that time, the overvalidation operation detector 145 can determine that the subsequent programming loop should be executed.

[0105] Figure 12 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0106] refer to Figure 12 By means of operating a semiconductor memory device according to embodiments of the present disclosure, memory cells coupled to selected word lines can be programmed.

[0107] At operation S110, a programming voltage VP can be applied to the selected word line. Therefore, among the memory cells coupled to the selected word line, the threshold voltage of the memory cell coupled to the bit line to which the programming enable voltage is applied may increase. That is, operation S110 can correspond to... Figure 10 The programming phase shown is executed during the time period from time t1 to time t4.

[0108] At operation S120, the value of the verification operation counter 141 can be initialized. This corresponds to initializing the value counted in the previous programming loop to count the number of verification operations performed in each programming loop. In one embodiment, operation S120 can be performed before operation S110. In other embodiments, operation S120 can be performed after operation S140 has been performed.

[0109] At operation S130, the verification operation corresponding to the programming state can be executed, and the number N of verification operations executed in the current programming loop is... VP It can be counted. According to Figure 10 In the illustrated embodiment, the verification operation using the first verification voltage VR1 and the second verification voltage VR2 is performed during the time period from time t5 to time t8. Therefore, at operation S130, the verification operation corresponding to the first programming state P1 and the second programming state P2 can be performed. The number N of verification operations counted at operation S130 is... VPIt can be 2. The number N of verification operations performed in the current programming loop at operation S130. VP It can be by Figure 11 The verification operation counter 141 is used to count.

[0110] At operation S140, the number N of verification operations to be performed in the current programming loop can be determined. VP Is it greater than the maximum number of verification operations (MAX)? VP Operation S140 can be performed by Figure 11 The overvalidation operation detector 145 is used to perform this. This is based on the number N of validation operations performed in the current programming loop. VP Greater than the maximum number of verification operations (MAX) VP This means that, in conjunction with the maximum number of verification operations (MAX), VP Compared to the normal situation, too many verification operations have been performed in the current programming loop. Therefore, the process can proceed to operation S170, where it can be determined that the currently executing programming operation has failed.

[0111] If the number N of verification operations to be performed in the current programming loop is determined at operation S140. VP Less than or equal to the maximum number of verification operations (MAX) VP If so, the verification operation can be considered to correspond to the verification operation in the normal case. In this case, the process proceeds to operation S150. At operation S150, it can be determined whether the verification operation corresponding to all programming states P1 to P7 has passed. When it is determined that the verification operation corresponding to all programming states P1 to P7 has passed, the process can proceed to operation S180, where it is determined that the programming operation has been successful.

[0112] When it is determined at operation S150 that the verification operation corresponding to all programming states P1 to P7 has not yet passed, the process proceeds to operation S160.

[0113] At operation S160, it is determined whether the current number of programming loops (i.e., the current programming loop count) has reached the maximum number of programming loops (i.e., the maximum programming loop count). When the current programming loop count has reached the maximum programming loop count, the process proceeds to operation S170, where it is determined that the programming operation has failed.

[0114] If it is determined at operation S160 that the current programming loop count has not reached the maximum programming loop count, a subsequent programming loop needs to be executed. Therefore, the process returns to operation S110, where the subsequent programming loop is executed. Here, the number of programming loops (programming loop count) can be incremented by 1. (See reference...) Figure 12 As can be seen, operations S110 to S160 can form a single programming loop.

[0115] like Figure 12 As shown, a method for operating a semiconductor memory device according to an embodiment of this disclosure may include: calculating the number N of verification operations to be performed in the current programming loop within a programming loop. VP MAX with maximum number of verification operations VP The comparison operation S140. Therefore, when determining the number N of verification operations to be performed in the current programming loop... VP Greater than the maximum number of verification operations (MAX) VP When (in the case of "Yes" at operation S140), it is determined that the currently executing programming operation has failed. Therefore, it is expected that a programming failure due to a defect in the selected word line can be detected, which may cause the threshold voltage to increase higher than expected.

[0116] Figure 13A and Figure 13B This is a diagram illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure. Figure 13A The diagram illustrates the programming loop in the i-th iteration (i... th The number N of verification operations performed in PGM LOOP VP Not greater than the maximum number of verification operations (MAX) VP In the case of, and Figure 13B The diagram illustrates the programming loop in the i-th iteration (i... th The number N of verification operations performed in PGMLOOP VP Greater than the maximum number of verification operations (MAX) VP The situation will be illustrated based on the maximum number of verification operations (MAX). VP It is described using "3".

[0117] refer to Figure 13A In the i-th programming loop (i th In the PGM LOOP, the i-th programming voltage VPi is first applied to the selected word line. Subsequently, in the verification phase, a first verification voltage VR1, a second verification voltage VR2, and a third verification voltage VR3 are used. That is, in the i-th programming loop (i... th In the PGM LOOP, the verification operations corresponding to the first programming state P1, the second programming state P2, and the third programming state P3 are executed respectively. That is, in Figure 13A In the example, in the i-th programming loop (i th The number N of verification operations performed in PGMLOOP VP It is 3. Because in the i-th programming loop (i... th The number N of verification operations performed in PGM LOOP VP(=3) is not greater than the maximum number of verification operations MAX VP (=3), therefore the subsequent programming loop, that is, the (i+1)th programming loop ((i+1) th PGM LOOP can be executed. Although Figure 13A The verification operation is not illustrated, but it can also be performed after the (i+1)th programming voltage VP(i+1) has been applied.

[0118] refer to Figure 13B In the i-th programming loop (i th In the PGM LOOP, the i-th programming voltage VPi is first applied to the selected word line. Subsequently, during the verification phase, a first verification voltage VR1, a second verification voltage VR2, a third verification voltage VR3, and a fourth verification voltage VR4 are used. That is, in the i-th programming loop (i... th In the PGM LOOP, the verification operations corresponding to the first programming state P1, the second programming state P2, the third programming state P3, and the fourth programming state P4 are executed respectively. That is, in Figure 13B In the example, in the i-th programming loop (i th The number N of verification operations performed in PGM LOOP VP The value is 4. Because in the i-th programming loop (i... th The number N of verification operations performed in PGM LOOP VP (=4) is greater than the maximum number of verification operations MAX VP (=3), therefore the subsequent programming loop was not executed, and it can be determined that the programming operation has failed.

[0119] Figure 14A and Figure 14B This is a diagram illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0120] refer to Figure 14A The illustration shows an embodiment in which the verification operation corresponding to the first programming state P1 begins in the first programming loop, the verification operation corresponding to the second programming state P2 begins in the second programming loop, the verification operation corresponding to the third programming state P3 begins in the third programming loop, the verification operation corresponding to the fourth programming state P4 begins in the sixth programming loop, and the verification operation corresponding to the fifth programming state P5 begins in the eighth programming loop.

[0121] Therefore, it can be seen that in the first programming cycle, the first programming voltage VP1 and the first verification voltage VR1 are applied to the selected word line. In the second programming cycle, the second programming voltage VP2, the first verification voltage VR1, and the second verification voltage VR2 are applied to the selected word line. In the third programming cycle, the third programming voltage VP3, the first verification voltage VR1, the second verification voltage VR2, and the third verification voltage VR3 are applied to the selected word line.

[0122] exist Figure 14A In the third programming cycle, the verification for the first programming state P1 has passed. Therefore, starting from the fourth programming cycle, the first verification voltage VR1 is not applied to the selected word line.

[0123] Thus, in Figure 14A In the example shown, the number of verification operations performed in each programming loop does not exceed 3. Therefore, it can be seen that subsequent programming loops are executed consecutively.

[0124] refer to Figure 14B Similar to Figure 14A The example illustrates an embodiment in which the verification operation corresponding to the first programming state P1 begins in the first programming loop, the verification operation corresponding to the second programming state P2 begins in the second programming loop, the verification operation corresponding to the third programming state P3 begins in the third programming loop, the verification operation corresponding to the fourth programming state P4 begins in the sixth programming loop, and the verification operation corresponding to the fifth programming state P5 begins in the eighth programming loop.

[0125] Therefore, it can be seen that in the first programming cycle, the first programming voltage VP1 and the first verification voltage VR1 are applied to the selected word line. In the second programming cycle, the second programming voltage VP2, the first verification voltage VR1, and the second verification voltage VR2 are applied to the selected word line. In the third programming cycle, the third programming voltage VP3, the first verification voltage VR1, the second verification voltage VR2, and the third verification voltage VR3 are applied to the selected word line.

[0126] It can be seen that, with Figure 14A Different, according to Figure 14BAs illustrated in the diagram, in the third programming cycle, the verification for the first programming state P1 has not yet passed. Therefore, even in the fourth programming cycle, the first verification voltage VR1 is applied to the selected word line. Furthermore, even in the fifth programming cycle, the verification for the first programming state P1 has not yet passed, so even in the sixth programming cycle, the first verification voltage VR1 is applied to the selected word line.

[0127] Furthermore, it can be seen that, with Figure 14A Different, according to Figure 14B As illustrated in the diagram, the verification for the second programming state P2 has not yet passed in the fifth programming cycle. Therefore, even in the sixth programming cycle, the second verification voltage VR2 is applied to the selected word line.

[0128] Therefore, in the sixth programming cycle, the first to fourth verification voltages VR1 to VR4 are applied to the selected word lines. That is, the number N of verification operations performed in the sixth programming cycle... VP The value is 4, which is greater than the maximum number of verification operations (MAX). VP That is, 3. Therefore, Figure 11 The overvalidation operation detector 145 can determine that the currently executing programming operation has failed.

[0129] Figure 15 The illustration shows an embodiment of the present disclosure including... Figure 1 A block diagram of a semiconductor memory device's memory system.

[0130] refer to Figure 15 The memory system 1000 may include a semiconductor memory device 100 and a controller 1100. The semiconductor memory device 100 may be a reference... Figure 1 The semiconductor memory device is described. Repeated descriptions will be omitted in the following text.

[0131] Controller 1100 is coupled to a host computer and a semiconductor memory device 100. Controller 1100 can access the semiconductor memory device 100 in response to requests from the host computer. For example, controller 1100 can control read, write, erase, and background operations of the semiconductor memory device 100. Controller 1100 provides an interface between the semiconductor memory device 100 and the host computer. Controller 1100 can execute instructions, such as firmware, for controlling the semiconductor memory device 100.

[0132] Controller 1100 includes random access memory (RAM) 1110, processor 1120, host interface 1130, memory interface 1140, and error correction block 1150. RAM 1110 is used as at least one of the following: working memory of processor 1120, cache memory between semiconductor memory device 100 and host, and buffer memory between semiconductor memory device 100 and host. Processor 1120 can control the overall operation of controller 1100. Additionally, controller 1100 can temporarily store programming data provided from host during write operations.

[0133] The host interface 1130 includes protocols for performing data exchange between the host and the controller 1100. In one embodiment, the controller 1100 can communicate with the host via at least one of various communication standards or interfaces, such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Fast (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and proprietary protocols.

[0134] The memory interface 1140 interfaces with the semiconductor memory device 100. For example, the memory interface may include a NAND interface or a NOR interface.

[0135] Error correction block 1150 can use error correction codes (ECC) to detect and correct errors in data received from semiconductor memory device 100. Processor 1120 can adjust the read voltage based on the error detection results of error correction block 1150 and can control semiconductor memory device 100 to perform a reread. In one embodiment, the error correction block can be provided as a component of controller 1100.

[0136] The controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device. In one embodiment, the controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash Card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, or MMCmicro), an SD card (SD, miniSD, microSD, or SDHC), or Universal Flash Memory (UFS).

[0137] The controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a solid-state drive (SSD). The SSD includes a storage device configured to store data in the semiconductor memory. When the memory system 1000 is used as an SSD, the operating speed of the host coupled to the memory system 1000 can be significantly improved.

[0138] In one embodiment, the memory system 1000 may be provided as one of various elements in an electronic device, such as a computer, ultra-mobile PC (UMPC), workstation, netbook, personal digital assistant (PDA), portable computer, network tablet, wireless telephone, mobile phone, smartphone, e-book reader, portable multimedia player (PMP), game console, navigation device, black box, digital camera, 3D television, digital recorder, digital audio player, digital image recorder, digital image player, digital video recorder, digital video player, device capable of transmitting / receiving information in a wireless environment, one of various electronic devices for forming a home network, one of various electronic devices for forming a computer network, one of various electronic devices for forming a telematics network, radio frequency identification (RFID) device, or one of various elements for forming a computing system.

[0139] In one embodiment, the semiconductor memory device 100 or memory system 1000 can be mounted in various types of packages. For example, the semiconductor memory device 100 or memory system 1000 can be packaged and mounted in types such as stacked package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), waffle package die, die-form-on-board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level processing stacked package (WSP).

[0140] Figure 16 The illustration shows an embodiment according to the present disclosure. Figure 15 A block diagram illustrating an application example of a memory system.

[0141] refer to Figure 16The memory system 2000 may include a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 may include multiple semiconductor memory chips. The semiconductor memory chips are divided into multiple groups.

[0142] exist Figure 16 The diagram illustrates multiple groups communicating with controller 2200 via channels CH1 to CHk (first to kth channels). Each semiconductor memory chip can communicate with a reference... Figure 1 The semiconductor memory device 100 described is configured and operated in the same manner.

[0143] Each group can communicate with controller 2200 through a common channel. Controller 2200 can have a reference... Figure 15 The controller 1100 described has the same configuration and can control multiple memory chips of the semiconductor memory device 2100 through multiple channels CH1 to CHk.

[0144] Figure 17 The illustration shows an embodiment according to the present disclosure, including references. Figure 16 A block diagram of the computing system describing the memory system.

[0145] The computing system 3000 includes a central processing unit (CPU) 3100, RAM 3200, user interface 3300, power supply 3400, system bus 3500 and memory system 2000.

[0146] The memory system 2000 is electrically coupled to the CPU 3100, RAM 3200, user interface 3300, and power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the CPU 3100 can be stored in the memory system 2000.

[0147] exist Figure 17 In the diagram, semiconductor memory device 2100 is illustrated as being coupled to system bus 3500 via controller 2200. However, semiconductor memory device 2100 may be directly coupled to system bus 3500. Here, the functions of controller 2200 may be performed by CPU 3100 and RAM 3200.

[0148] exist Figure 17 In the middle, for reference Figure 16 The memory system 2000 described is illustrated as provided. However, the memory system 2000 can utilize references... Figure 15 The memory system 1000 described herein is used as a replacement. In one embodiment, the computing system 3000 may include a reference... Figure 15 and Figure 16The memory systems described are 1000 and 2000.

[0149] This disclosure provides a semiconductor memory device that can enhance the reliability of programming operations, as well as a method for operating the semiconductor memory device.

[0150] Furthermore, embodiments of this disclosure have been described in the accompanying drawings and specification. While specific terms are used herein, they are only for describing embodiments of this disclosure. Therefore, this disclosure is not limited to the embodiments described above, and many variations can exist within the spirit and scope of this disclosure. Embodiments can be combined to form additional embodiments.

[0151] Furthermore, the embodiments disclosed in this specification and accompanying drawings are intended to help those skilled in the art to better understand this disclosure, and are not intended to limit the scope of this disclosure. Therefore, those skilled in the art to which this disclosure pertains will readily understand that various modifications based on the technical scope of this disclosure and the appended claims are possible.

Claims

1. A semiconductor memory device, comprising: A memory cell array, comprising multiple memory cells; Peripheral circuitry is configured to perform a programming operation on a selected memory cell among the plurality of memory cells, coupled to a selected word line. The programming operation includes a plurality of programming cycles, each of which includes a programming phase and a verification phase, the verification phase including one or more verification operations. as well as Control logic, configured to control the programming operation of the peripheral circuit, includes a verification operation counter configured to count the number of verification operations performed by the peripheral circuit in the verification phase included in one of the plurality of programming cycles during the programming operation, wherein the verification voltages of the verification operations are different from each other. The control logic is further configured to determine whether the number of verification operations is greater than the set maximum number of verification operations. The control logic is further configured to determine that the programming operation has failed when the number of verification operations is greater than the set maximum number of verification operations.

2. The semiconductor memory device of claim 1, wherein the control logic is further configured to: when the number of verification operations is not greater than the set maximum number of verification operations, control the peripheral circuit such that a subsequent programming cycle in the plurality of programming cycles is executed during the programming operation.

3. The semiconductor memory device of claim 1, wherein the control logic further comprises: A maximum number of verification operations storage device is configured to store the set maximum number of verification operations; as well as An overvalidation operation detector is configured to compare the number of validation operations performed in the programming loop with the set maximum number of validation operations.

4. The semiconductor memory device of claim 1, wherein the control logic is further configured to: determine whether the verification operation corresponding to all programming states has passed when the number of verification operations is not greater than the set maximum number of verification operations.

5. The semiconductor memory device of claim 4, wherein the control logic is further configured to: determine that the programming operation has been successful when the verification operation corresponding to all programming states has passed.

6. The semiconductor memory device of claim 4, wherein the control logic is further configured to: determine whether the current number of programming cycles has reached the maximum number of programming cycles when the verification operation corresponding to all programming states has not yet passed.

7. The semiconductor memory device of claim 6, wherein the control logic is further configured to: determine that the programming operation has failed when the current number of programming cycles has reached the maximum number of programming cycles.

8. The semiconductor memory device of claim 6, wherein the control logic is further configured to: when the current number of programming cycles has not yet reached the maximum number of programming cycles, control the peripheral circuitry such that subsequent programming cycles among the plurality of programming cycles are executed during the programming operation.

9. A method of operating a semiconductor memory device, the semiconductor memory device comprising a plurality of memory cells, the method comprising performing a programming operation to program a memory cell among the plurality of memory cells coupled to a selected word line. The programming operation includes multiple programming loops, and each of the multiple programming loops includes: Apply a programming voltage to the selected word line; Perform one or more verification operations on the memory cell coupled to the selected word line, each of the one or more verification operations corresponding to one or more programming states; as well as The number of the multiple verification operations performed in the current programming loop at an increasing verification voltage is counted. The programming loop further includes determining whether the counted number of verification operations is greater than the set maximum number of verification operations. The programming loop further includes determining that the programming operation has failed in response to a determination that indicates the count of the verification operation is greater than the maximum number of verification operations.

10. The method of claim 9, wherein the programming loop further comprises: In response to the determination that the count of the verification operations is not greater than the maximum number of verification operations, it is determined whether the verification operation corresponding to all programming states has passed.

11. The method of claim 10, wherein the programming loop further comprises: In response to a determination that the verification operation corresponding to all programming states has passed, the programming operation is determined to be successful.

12. The method of claim 10, wherein the programming loop further comprises: In response to a determination that indicates the verification operation corresponding to all programming states has not yet passed, determine whether the current number of programming loops has reached the maximum number of programming loops.

13. The method of claim 12, wherein the programming loop further comprises: In response to a determination that the current number of programming loops has reached the maximum number of programming loops, it is determined that the programming operation has failed.

14. The method of claim 12, wherein the programming loop further comprises: In response to a determination indicating that the current number of programming loops has not yet reached the maximum number of programming loops, it is determined that the subsequent programming loop of the programming loop shall be executed.

15. The method of claim 9, wherein performing the verification operation corresponding to the programming state on the memory cell coupled to the selected word line comprises: A verification voltage corresponding to the programming state is applied to the selected word line.

16. A semiconductor memory device, comprising: A memory cell array, comprising multiple memory cells; Peripheral circuitry is configured to perform a programming operation on a selected memory cell among the plurality of memory cells, coupled to a selected word line. The programming operation includes a plurality of programming cycles, each of which includes a programming phase and a verification phase, the verification phase including one or more verification operations. as well as Control logic, configured to control the programming operations of the peripheral circuitry, the control logic including: A verification operation counter is configured to count the number of verification operations performed by the peripheral circuitry in one of the plurality of programming cycles during the programming operation, wherein the verification voltages of the verification operations are different from each other. The maximum number of verification operations storage device is configured to store the maximum number of verification operations; as well as An overvalidation operation detector is configured to compare the number of validation operations performed in the programming loop with the maximum number of validation operations, and determine whether the programming operation has been successful based on the result of the comparison.

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