Substrate processing apparatus with intermediate electrode

Abstract

The present disclosure relates to a substrate processing apparatus having an intermediate electrode. The substrate processing apparatus can include a vacuum chamber, a substrate support unit disposed at a lower portion of an inside of the vacuum chamber, and an electric field forming unit forming an electric field at the inside of the vacuum chamber. The electric field forming unit can include an upper electrode disposed at an upper portion of the inside of the vacuum chamber, a lower electrode disposed in the substrate support unit, and an intermediate electrode disposed between the upper electrode and the lower electrode.

Description

Technical Field

[0001] Embodiments of this disclosure provide a substrate processing apparatus having an intermediate electrode and a method for processing a substrate using the substrate processing apparatus. Background Technology

[0002] Recently, as semiconductor devices have become miniaturized and highly multilayered, it has become increasingly difficult to process substrates (e.g., semiconductor wafers) using etching processes. To form patterns with high aspect ratios, hard metal masks with excellent etch selectivity are used, but even with hard metal masks, it is difficult to withstand etching damage. Summary of the Invention

[0003] A substrate processing apparatus according to embodiments of the present disclosure may include: a vacuum chamber; a substrate support unit disposed in the lower portion of the interior of the vacuum chamber; and an electric field forming unit that forms an electric field inside the vacuum chamber. The electric field forming unit may include: an upper electrode disposed in the upper portion of the interior of the vacuum chamber; a lower electrode disposed in the substrate support unit; and an intermediate electrode disposed between the upper electrode and the lower electrode.

[0004] A substrate processing apparatus according to embodiments of the present disclosure may include: a vacuum chamber; a gas supply unit configured to supply gas into the vacuum chamber; a support plate disposed in a lower portion of the interior of the vacuum chamber; an upper electrode disposed in an upper portion of the interior of the vacuum chamber; a lower electrode disposed in the support plate; and an intermediate electrode adjacent to an upper surface of the support plate. The intermediate electrode may include an end portion configured to physically contact an edge region of a wafer on the support plate.

[0005] A method for processing a substrate according to embodiments of the present disclosure may include the following steps: loading a wafer onto a support plate of a substrate support unit in a vacuum chamber; evacuating the vacuum chamber using a gas evacuation unit; supplying one of a reactive gas, a precursor, or plasma into the vacuum chamber using a gas supply unit; and processing the wafer using an electric field forming unit. The step using the electric field forming unit may include the step of forming an electric field. The step of forming the electric field may include applying an upper electrode voltage to an upper electrode, applying a lower electrode voltage to a lower electrode, and applying an intermediate electrode voltage to an intermediate electrode. The intermediate electrode is in physical contact with the wafer. Attached Figure Description

[0006] Figure 1 This is a schematic structural diagram of a substrate processing apparatus according to an embodiment of the present disclosure.

[0007] Figures 2A to 2D and Figure 3A and Figure 3B This is a diagram illustrating an intermediate electrode in contact with the upper surface of a wafer.

[0008] Figures 4A to 4C This is a diagram illustrating a wafer processed using a substrate processing apparatus according to an embodiment of the present disclosure. Detailed Implementation

[0009] Embodiments of this disclosure provide a substrate processing apparatus having an intermediate electrode and a method for processing a substrate using the substrate processing apparatus.

[0010] Embodiments of this disclosure provide methods and processes for applying voltage to a metal hard mask of a wafer during substrate processing.

[0011] Figure 1 This is a schematic structural diagram of a substrate processing apparatus 100 according to an embodiment of the present disclosure. (Refer to...) Figure 1 According to the embodiments, the substrate processing apparatus 100 may include a vacuum chamber 10, a gas supply unit 20, a substrate support unit 30, a gas discharge unit 40, and electric field forming units 51 to 54.

[0012] The gas supply unit 20 can supply various reactive gases, precursors, or plasmas from outside the vacuum chamber 10 into the vacuum chamber 10. The reactive gases may include at least one of gases used in etching processes, deposition processes, purging processes, and cleaning processes. The gas supply unit 20 may include a gas supply pipe 21, a mass flow meter 22, a gas delivery pipe 23, and a gas distribution unit 24. The gas supply pipe 21 can supply gas from a gas tank or gas reservoir to the mass flow meter 22. Although only one gas supply pipe 21 is shown in the figures, it may include multiple sub-gas supply pipes (not shown). The mass flow meter 22 can control the flow rate of various gases as they are delivered into the vacuum chamber 10. Although only one mass flow meter 22 is shown in the figures, it may include multiple sub-mass flow meters (not shown). The gas delivery pipe 23 can deliver reactive gases, precursors, or plasmas from the mass flow meter 22 to the gas distribution unit 24 located within the vacuum chamber 10. Gas delivery pipe 23 can deliver and supply reactant gases, precursors, or plasma into vacuum chamber 10 through the upper and / or side portions of vacuum chamber 10. Gas distribution unit 24 can uniformly distribute reactant gases, precursors, or plasma into vacuum chamber 10. In one embodiment, gas distribution unit 24 may include a shower head. For example, gas distribution unit 24 may include multiple gas injection openings 24a. In one embodiment, gas distribution unit 24 may include a baffle.

[0013] The substrate support unit 30 may be disposed in the lower part inside the vacuum chamber 10. The substrate support unit 30 may include a support plate 31 and an actuator 32. The substrate (e.g., a wafer) W may be mounted on the support plate 31. In one embodiment, the support plate 31 may include an electrostatic chuck (ESC). In one embodiment, the support plate 31 may include a vacuum chuck. The actuator 32 may perform lifting, lowering, and rotating operations. Therefore, the support plate 31 may be raised, lowered, and rotated by the operation of the actuator 32.

[0014] The gas exhaust unit 40 may include a gas exhaust pipe 41 and a vacuum pump 42. The gas exhaust pipe 41 can transfer the reactant gas, precursor, and plasma from the inside of the vacuum chamber 10 to the vacuum pump 42. The vacuum pump 42 can exhaust the reactant gas, precursor, and plasma from the inside of the vacuum chamber 10 to the outside of the vacuum chamber 10. The vacuum pump 42 can evacuate the gas inside the vacuum chamber 10.

[0015] The substrate processing apparatus 100 may further include a coil 61 disposed outside the vacuum chamber 10. The coil 61 can generate a magnetic field inside the vacuum chamber 10. The coil 61 may be disposed on the side wall of the vacuum chamber 10. In one embodiment, the coil 61 may be disposed above the vacuum chamber 10.

[0016] The electric field forming units 51 to 54 may include an upper electrode 51, a lower electrode 52, an intermediate electrode 53, and a controller 54. The upper electrode 51 may be disposed in the upper portion of the vacuum chamber 10. The upper electrode 51 may be disposed above the gas distribution unit 24 of the gas supply unit 20. The lower electrode 52 may be embedded in or disposed in the support plate 31. In one embodiment, the lower electrode 52 may be disposed below the support plate 31. The upper electrode 51 and the lower electrode 52 can form a plasma P in the vacuum chamber 10 and can form an electric field to allow the plasma P to react with the wafer W.

[0017] The intermediate electrode 53 may be disposed adjacent to the support plate 31 of the substrate support unit 30. In one embodiment, the intermediate electrode 53 may be disposed adjacent to the upper surface of the support plate 31. In one embodiment, the intermediate electrode 53 may be disposed adjacent to the side surface of the support plate 31. The substrate support unit 30 may also include an edge ring 33 disposed on an edge portion of the support plate 31. The edge ring 33 may be mounted on the support plate 31 and may be configured to be coupled to and separate from the support plate 31. The edge ring 33 may include an insulating material such as quartz. In one embodiment, the intermediate electrode 53 may be disposed adjacent to the edge ring 33 disposed on the support plate 31. In one embodiment, the intermediate electrode 53 may penetrate the edge ring 33 of the support plate 31. In one embodiment, the intermediate electrode 53 may be embedded in the edge ring 33. The intermediate electrode 53 may contact the wafer W. The intermediate electrode 53 may be in electrical contact with a conductive material layer disposed on the uppermost portion of the wafer W. For example, the intermediate electrode 53 can be in direct contact with the conductive material layer of the wafer W or can be capacitively connected to the conductive material layer of the wafer W. By inserting a dielectric between the intermediate electrode 53 and the conductive material layer of the wafer W, a substantial electrical connection can be formed between the intermediate electrode 53 and the wafer W. In one embodiment, the substrate processing apparatus 100 may include at least two intermediate electrodes 53 disposed along the outer periphery of the support plate 31 of the substrate support unit 30. Therefore, the intermediate electrode 53 and the wafer W may have two or more contact points.

[0018] The controller 54 can apply voltages to the upper electrode 51, lower electrode 52, and intermediate electrode 53. The controller 54 can periodically change the voltages. For example, the controller 54 can adjust the voltages applied to the upper electrode 51, lower electrode 52, and intermediate electrode 53 so that the applied voltage levels change independently.

[0019] Figures 2A to 2D and Figure 3A and Figure 3B This diagram illustrates an intermediate electrode 53 in contact with the upper surface of wafer W. Wafer W may include a lower layer 71, an intermediate layer 72, and an upper layer 73. Lower layer 71 may include an etch target layer. For example, lower layer 71 may include one of a silicon substrate, a silicon oxide layer, a silicon nitride layer, or other non-conductive material layers. Intermediate layer 72 may include a conductive material layer. For example, intermediate layer 72 may include a metal etch mask layer. Upper layer 73 may include a non-conductive material layer. For example, upper layer 73 may include a photoresist pattern. Intermediate electrode 53 may be physically in contact with or electrically in contact with intermediate layer 72 of wafer W. For example, intermediate electrode 53 may penetrate upper layer 73 of wafer W to contact an edge region of intermediate layer 72. Because intermediate layer 72 may be formed entirely on lower layer 71 of wafer W, intermediate layer 72 may be parallel to lower electrode 52 in support plate 31. Therefore, intermediate layer 72 and lower electrode 52 may form electrodes of a capacitor. Intermediate electrode 53 may have a strip shape or a rod shape. The end of the intermediate electrode 53 may taper gradually to a point and may have a needle-like shape. The needle-like end portion of the intermediate electrode 53 may be rounded or may have a substantially flat end face.

[0020] Reference Figure 2B The intermediate electrode 53 may include a body portion B and an end portion E. The end portion E may directly contact the wafer W. The body portion B may have a vertical cylindrical shape. In different embodiments, the cross-section of the body portion B may have different shapes. For example, the body portion B may have a substantially flat vertical side surface. The end portion E may have an inverted conical shape, an inverted pyramid shape, or an inverted wedge shape. The end portion E may have a pointed shape and may physically penetrate the upper layer 73. For example, the distal or furthest end of the end portion E may have a needle-like shape or a pinnacle shape. In one embodiment, the distal or furthest point of the end portion E may be circular. The body portion B and the end portion E of the intermediate electrode 53 may include conductors such as metal.

[0021] Reference Figure 2C The end portion E of the intermediate electrode 53 may include a pointed end tip E2 and an end body E1 that may have sloping side surfaces. The end tip E2 may include an insulating material such as Teflon or plastic. The end tip E2 may be formed of a material that is harder than the material used to form the upper layer 73 of the wafer W, which may facilitate physical penetration of the upper layer 73 of the wafer W.

[0022] Reference Figure 2DThe wafer W may include an exposed edge region EA, and the intermediate electrode 53 may be in direct contact with the intermediate layer 72 exposed in the edge region EA. In the edge region EA of the wafer W, a portion of the upper layer 73 may be removed to expose the intermediate layer 72. In various embodiments with or without an exposed edge region EA, the end portion of the intermediate electrode 53 may differ. For example, refer to… Figure 2B The intermediate electrode 53 may include an end portion E. (See reference...) Figure 2C The intermediate electrode 53 may include an end body E1 and an end tip E2. The end portion of the intermediate electrode 53 may be rounded or flat. Therefore, referring to... Figures 2B to 2D The inventive concept described herein is compatible with each other and with implementations that have or do not have exposed edge regions EA.

[0023] Reference Figure 3A and Figure 3B The intermediate electrode 53 may include a body portion B and an end portion E. The body portion B may be elastic. For example, the body portion B may have a flat spring or a strip shape with elastic properties. The end portion E of the intermediate electrode 53 may have a curved shape. For example, the end portion E of the intermediate electrode 53 may have an elbow shape or a bracket shape. The end portion E of the intermediate electrode 53 may also be elastic. In one embodiment, the body portion B of the intermediate electrode 53 may have a horizontally extending rod shape or a horizontal strip shape. In one embodiment, the intermediate electrode 53 may have an inclined shape. For example, the intermediate electrode 53 may form an angle ranging from 0° to 90° relative to the top surface of the intermediate layer 72 of the wafer W.

[0024] Reference Figure 3A The end portion E can have a curved or bent shape with the apex pointing downwards. At the lowest end or lowest point of the apex, the end portion E can descend and rise to become rounded or have a V-shape so that the end portion E of the intermediate electrode 53 and the intermediate layer 72 of the wafer W can contact each other.

[0025] Reference Figure 3B The end portion E may have a sliding rod shape or a segment shape that is inclined relative to the main body portion B. For example, the end portion E may form an angle in the range of 0° to 90° relative to the main body portion B. The intermediate electrode 53 or the wafer W may be translated in the horizontal direction so that the end portion E and the intermediate layer 72 of the wafer W can contact each other. The end portion E of the intermediate electrode 53 may slide onto the edge of the intermediate layer 72 of the wafer W. In other embodiments, the intermediate electrode 53 or the wafer W may be translated in the vertical direction so that the end portion E of the intermediate electrode 53 and the intermediate layer 72 of the wafer W contact each other.

[0026] Figures 4A to 4C This is a diagram illustrating a wafer W processed using a substrate processing apparatus 100 according to an embodiment of the present disclosure. For example, a process for selectively etching the wafer W using a reactor R will be described.

[0027] Reference Figure 1 and Figure 4A The method of etching wafer W using substrate processing equipment 100 may include the following steps: loading wafer W onto support plate 31 of substrate support unit 30 in vacuum chamber 10; creating a vacuum inside vacuum chamber 10 using gas exhaust unit 40; supplying at least one of reactive gas, precursor or plasma into vacuum chamber 10 using gas supply unit 20; and processing wafer W using electric field forming units 51 to 54.

[0028] The steps of processing wafer W using electric field forming units 51 to 54 may include: applying a first upper electrode voltage Va1 to upper electrode 51; applying a first lower electrode voltage Vb1 to lower electrode 52; and applying a first intermediate electrode voltage Vc1 to intermediate electrode 53 to perform a substrate processing process in a first time period. The first upper electrode voltage Va1 may be a ground voltage or a negative (-) voltage, the first lower electrode voltage Vb1 may be a positive (+) voltage, and the first intermediate electrode voltage Vc1 may be a positive voltage or a floating voltage. A floating voltage may be a state in which no voltage is applied to intermediate electrode 53. Due to the electric field generated between upper electrode 51 and lower electrode 52, the reactant R is strongly affected by the electric field and moves relatively quickly from the outer periphery of upper electrode 51 to the surface of wafer W, and in subsequent reactions, the lower layer 71, intermediate layer 72, and upper layer 73 of wafer W can be etched. In this case, the upper layer 73 of wafer W may selectively expose a portion of the lower layer 71 and a portion of the intermediate layer 72. The intermediate layer 72 of wafer W can selectively expose a portion of the underlying layer 71. Therefore, the reactant R can partially remove both the exposed underlying layer 71 and the exposed intermediate layer 72 of wafer W. Due to etching selectivity, the underlying layer 71 can be etched more easily than the intermediate layer 72. In one embodiment, the first upper electrode voltage Va1 and the first lower electrode voltage Vb1 can be interchanged. For example, the same voltage as the first lower electrode voltage Vb1 can be applied to the upper electrode 51, and the same voltage as the first upper electrode voltage Va1 can be applied to the lower electrode 52. In one embodiment, the first intermediate electrode voltage Vc1 can be an intermediate voltage falling between the first upper electrode voltage Va1 and the first lower electrode voltage Vb1. In one embodiment, the intermediate layer 72 can be completely covered by the upper layer 73 and can be left unetched. For example, the exposed underlying layer 71 and upper layer 73 can be partially removed.

[0029] Reference Figure 1 and Figure 4B A method for processing wafer W using substrate processing equipment 100 may include the following steps: applying a second upper electrode voltage Va2 to an upper electrode 51; applying a second lower electrode voltage Vb2 to a lower electrode 52; and applying a second intermediate electrode voltage Vc2 to an intermediate electrode 53 to perform a substrate processing process in a second time period. The second upper electrode voltage Va2 may be a ground voltage or a negative (-) voltage, the second lower electrode voltage Vb2 may be a higher positive (+) voltage, and the second intermediate electrode voltage Vc2 may be a lower positive (+) voltage or a ground voltage than Vb2. For example, the second intermediate electrode voltage Vc2 may be an intermediate voltage falling between the second upper electrode voltage Va2 and the second lower electrode voltage Vb2. Because the second intermediate electrode voltage Vc2 is applied to the intermediate layer 72 of wafer W, the electric field between the upper electrode 51 and the lower electrode 52 can be adjusted. For example, the physical energy of the reactant R bombarding the intermediate layer 72 of wafer W can be controlled. Therefore, damage to the intermediate layer 72 can be mitigated or reduced.

[0030] Reference Figure 1 and Figure 4C A method for processing wafer W using substrate processing equipment 100 may include the following steps: applying a third upper electrode voltage Va3 to an upper electrode 51; applying a third lower electrode voltage Vb3 to a lower electrode 52; and applying a third intermediate electrode voltage Vc3 to an intermediate electrode 53 to perform a substrate processing process in a third time period. The third upper electrode voltage Va3 may be a ground voltage or a negative (-) voltage, the third lower electrode voltage Vb3 may be a positive (+) voltage, and the third intermediate electrode voltage Vc3 may be a negative (-) voltage. For example, the third intermediate electrode voltage Vc3 may be a voltage having the same polarity as the third upper electrode voltage Va3. The intermediate electrode voltages Vc1-Vc3 may be changed or varied between the upper electrode voltages Va1-Va3 and the lower electrode voltages Vb1-Vb3.

[0031] Because the third intermediate electrode voltage VC3 is applied to the intermediate layer 72 of wafer W, the bombardment of the intermediate layer 72 of wafer W by the reactant R can be reduced, or the physical energy guiding the intermediate layer 72 of wafer W can be significantly reduced or weakened.

[0032] When wafer W is processed using substrate processing equipment 100, damage to the metal material layer (e.g., intermediate layer 72) formed on wafer W can be reduced. Therefore, even if the intermediate layer 72 is thin, the etching process can be performed in a stable manner, thereby enabling improvements in fine pattern etching processes and high aspect ratio etching processes.

[0033] According to embodiments of this disclosure, the severity of damage to the metal hard mask on the wafer can be reduced, enabling the stable formation of patterns with a high aspect ratio.

[0034] While this disclosure contains numerous details, these details should not be construed as limiting the scope of the teachings or the content that may be claimed, but rather as descriptions of features specific to particular embodiments of the teachings. Specific features described in this patent document within the context of individual embodiments are also implemented in combination within those individual embodiments. Conversely, various features described in the context of individual embodiments may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a particular combination and even initially claimed in this way, one or more features from the claimed combination may be removed from the combination in some cases, and the claimed combination may involve sub-combinations or variations of sub-combinations.

[0035] Similarly, although operations are described in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or to perform all of the shown operations to achieve the desired result. Furthermore, the separation of the various system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments. Only some embodiments and examples have been described. Other embodiments, enhancements, and variations can be made based on the descriptions and examples in this patent document.

[0036] Cross-reference to related applications

[0037] This application claims priority to Korean Patent Application No. 10-2021-0007395, filed on January 19, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A substrate processing apparatus for processing wafers, the substrate processing apparatus comprising: Vacuum chamber; A substrate support unit is disposed in the lower part of the interior of the vacuum chamber; as well as An electric field forming unit, which forms an electric field inside the vacuum chamber; The electric field forming unit includes: The upper electrode is disposed in the upper part of the interior of the vacuum chamber; The lower electrode is disposed in the substrate support unit; and An intermediate electrode is disposed between the upper electrode and the lower electrode. The intermediate electrode is electrically connected to the conductive material layer of the wafer. The wafer comprises a lower layer, an intermediate layer, and a top layer. The intermediate electrode is in physical contact with the intermediate layer of the wafer. The intermediate layer of the wafer includes a metal etching mask layer. The intermediate electrode voltage applied to the intermediate electrode is applied to the intermediate layer of the wafer. The intermediate electrode voltage is an intermediate voltage that falls between the upper electrode voltage applied to the upper electrode and the lower electrode voltage applied to the lower electrode.

2. The substrate processing apparatus according to claim 1, further comprising a controller that applies voltage to the upper electrode, the lower electrode and the intermediate electrode.

3. The substrate processing apparatus according to claim 1, further comprising a gas supply unit, the gas supply unit including a gas distribution unit disposed in the upper portion inside the vacuum chamber. in, The upper electrode is positioned above the gas distribution unit.

4. The substrate processing apparatus according to claim 1, wherein, The substrate support unit includes a support plate and an actuator for moving the support plate, and The lower electrode is disposed in the support plate.

5. The substrate processing apparatus according to claim 1, wherein, The intermediate electrode includes a main body portion and an end portion having a rod-shaped form.

6. The substrate processing apparatus according to claim 5, wherein, The end portion includes an end tip with a pointed shape.

7. The substrate processing apparatus according to claim 6, wherein, The tip of the end includes an insulating material.

8. The substrate processing apparatus according to claim 6, wherein, The tip of the end is rounded.

9. The substrate processing apparatus according to claim 6, wherein, The end portion also includes an end body with an inclined side surface.

10. The substrate processing apparatus according to claim 1, wherein, The intermediate electrode includes: The main body portion has a horizontal rod-shaped form; as well as The end portion has a curved shape.

11. The substrate processing apparatus according to claim 10, wherein, The end portion includes a downward-facing vertex.

12. The substrate processing apparatus according to claim 10, wherein, The end portion has a rod-shaped form that forms an angle with the main body portion.

13. The substrate processing apparatus according to claim 1, wherein, The substrate support unit includes a support plate and an edge ring, and The intermediate electrode is adjacent to the edge ring.

14. The substrate processing apparatus according to claim 13, wherein, The intermediate electrode penetrates the edge ring.

15. A substrate processing apparatus for processing wafers, the substrate processing apparatus comprising: Vacuum chamber; A gas supply unit that supplies gas to the vacuum chamber; A support plate is disposed in the lower part of the interior of the vacuum chamber; The upper electrode is disposed in the upper part of the interior of the vacuum chamber; The lower electrode is disposed in the support plate; as well as An intermediate electrode, which is adjacent to the upper surface of the support plate; The intermediate electrode includes an end portion that is in physical contact with the edge region of the substrate on the support plate. The intermediate electrode is electrically connected to the conductive material layer of the wafer. The wafer comprises a lower layer, an intermediate layer, and a top layer. The intermediate electrode is in physical contact with the intermediate layer of the wafer. The intermediate layer of the wafer includes a metal etching mask layer. The intermediate electrode voltage applied to the intermediate electrode is applied to the intermediate layer of the wafer. The intermediate electrode voltage is an intermediate voltage that falls between the upper electrode voltage applied to the upper electrode and the lower electrode voltage applied to the lower electrode.

16. A method for processing a substrate, the method comprising the following steps: The wafer is loaded onto the support plate of the substrate support unit in the vacuum chamber; The vacuum chamber is evacuated using a gas exhaust unit; A gas supply unit is used to supply one of the reactant gas, precursor, and plasma into the vacuum chamber, and The wafer is processed using an electric field forming unit. The step of using the electric field forming unit includes the step of forming an electric field, and the step of forming an electric field includes the following steps: Apply the voltage to the upper electrode; Apply the lower electrode voltage to the lower electrode, and Apply the intermediate electrode voltage to the intermediate electrode; The intermediate electrode is in physical contact with the wafer. The intermediate electrode is electrically connected to the conductive material layer of the wafer. The wafer comprises a lower layer, an intermediate layer, and a top layer. The intermediate electrode is in physical contact with the intermediate layer of the wafer. The intermediate layer of the wafer includes a metal etching mask layer. The intermediate electrode voltage applied to the intermediate electrode is applied to the intermediate layer of the wafer. The intermediate electrode voltage is an intermediate voltage that falls between the upper electrode voltage applied to the upper electrode and the lower electrode voltage applied to the lower electrode.

17. The method according to claim 16, wherein, The intermediate electrode voltage is the voltage between the upper electrode voltage and the lower electrode voltage.

18. The method of claim 17, further comprising the step of: The intermediate electrode voltage is changed between the upper electrode voltage and the lower electrode voltage to control the physical energy guiding the wafer.

19. The method according to claim 16, in, The intermediate electrode voltage has the same polarity as the upper electrode voltage.

20. The method of claim 16, wherein, The voltage of the intermediate electrode is the ground voltage.

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