A method for manufacturing a first via dual damascene

Abstract

The application relates to the field of semiconductor manufacturing, in particular to a via-first dual damascene method, which comprises the following steps: forming a via in a medium layer of a semiconductor substrate; conformally depositing a thin bottom anti-reflection layer; depositing a spin-on hard mask layer to fill the via; performing a photoetching and etching process to form a groove communicating with the via above the via; and filling a metal layer in the via and the groove. The via-first dual damascene method can better fill the via and avoid defects in the subsequent spin-on hard mask layer filling, and can prevent over-etching of the lower layer and cause poor performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a via-first dual damascene method. BACKGROUND

[0002] Dual damascene process (also known as dual damascene process) is frequently used in semiconductor manufacturing process to form via and trench, and then Cu, W, Si is deposited once to form, and then planarization process is performed once. Whether via or trench is etched first can be distinguished according to which process is performed first, and currently, via-first dual damascene process is mostly used.

[0003] In the process of via-first dual damascene process, via is formed first, and then organic matter (for example, spin-on hard mask composition) is filled in the via to protect the via, and then, as shown in Fig. 1a , a trench pattern is formed, and then, as shown in Fig. 1b , the trench is etched again, and then, as shown in Fig. 1c , metal material is deposited to fill the via and the trench, and then the surface is planarized.

[0004] However, when the organic protective matter is filled in the via formed first in the above-mentioned via-first dual damascene process, the filling layer cannot be uniformly and densely formed, and void defects are easily generated. These defects are difficult to effectively play the role of hard mask to protect the interlayer dielectric layer and the via when the trench is etched subsequently, and over-etching is generated near the defects, which further causes the deformation of the appearance of the via and induces the poor electrical performance of the product. SUMMARY

[0005] The present application at least partially solves the above-mentioned technical problems in the related art. To this end, the present application provides a via-first dual damascene method to solve at least one of the above-mentioned technical problems.

[0006] To achieve the above-mentioned purpose, the present application provides a via-first dual damascene method, comprising the following steps:

[0007] forming a via in a dielectric layer of a semiconductor substrate;

[0008] conformally depositing a thin bottom anti-reflective layer;

[0009] depositing a spin-on hard mask layer to fill the via;

[0010] forming a trench communicating with the via above the via;

[0011] filling a metal layer in the via and the trench.

[0012] The first via dual damascene method in the present application can better fill the via and avoid defects in filling of the subsequent spin-on hard mask layer, and can prevent over-etching of the lower layer and resulting poor performance, by first conformally depositing a thin bottom anti-reflective coating before filling the via with a spin-on hard mask or other mask protection material. BRIEF DESCRIPTION OF DRAWINGS

[0013] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of preferred embodiments, and are not intended to limit the scope of the present application. Furthermore, the same reference numerals are used throughout the drawings to represent the same or similar components. In the drawings:

[0014] Figs. 1a-1c A structure diagram of a prior art first via dual damascene process is shown;

[0015] Figs. 2a-2f A structure diagram of a first via dual damascene process in the present application is shown. DETAILED DESCRIPTION

[0016] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description which follows is merely exemplary and is not intended to limit the scope of the present disclosure. Furthermore, in the following description, descriptions of well-known structures and techniques are omitted to avoid obscuring the concept of the present disclosure.

[0017] Various structure diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity, and certain details can be omitted. The shapes of various regions, layers, and their relative sizes and positional relationships shown in the diagrams are merely exemplary, and in actuality can be deviated due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art as needed.

[0018] In the context of the present disclosure, when a layer / element is said to be located "on" another layer / element, the layer / element can be directly on the other layer / element, or an intervening layer / element can be present therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0019] Reference will now be made to Figs. 2a to 2f Embodiments of the present application provide a first via dual damascene method, which can specifically include the following steps:

[0020] As Fig. 2aAs shown, a semiconductor substrate 10 is provided, which has a conductive layer 11 formed therein, and which has sequentially formed thereon from bottom to top a first etch stop layer 12, an interlayer dielectric layer 13, a first spin-on hard mask layer 14, and a second etch stop layer 15.

[0021] In particular, the semiconductor substrate 10 can include any known silicon-based semiconductor material, including silicon, silicon-germanium, silicon-on-insulator, or silicon-on-sapphire substrates. Alternatively, the semiconductor substrate 10 can include a silicon layer formed on a non-silicon-based semiconductor material, such as gallium arsenide, germanium, gallium nitride, or aluminum-phosphorous. In some embodiments, the semiconductor substrate 10 is a doped or undoped silicon substrate. The conductive layer 11 is, for example, a copper-containing conductive layer; the materials of the first etch stop layer 12 and the second etch stop layer 16 are, for example, silicon oxynitride (SiON); the material of the interlayer dielectric layer 13 can be an oxide or other low-k or ultra-low-k material, such as tetraethyl orthosilicate (TEOS); and the material of the first spin-on hard mask layer 14 is, for example, a spin-on hard mask composition (SOH). The formation of the above layers can be performed using, for example, conventional chemical vapor deposition processes.

[0022] Next, a first bottom anti-reflective coating (BARC) 16 and a first photoresist layer 17 can be sequentially coated on the second etch stop layer from bottom to top, and then the first photoresist layer 17 can be patterned to form a first photoresist pattern, it is worth mentioning that the position and shape of the opening of the first photoresist pattern correspond to the position and shape of the via to be formed, and the patterning can be performed using a conventional photolithography process.

[0023] Next, referring to Fig. 2b The first photoresist pattern can be used as a mask to perform etching from top to bottom until the first etch stop layer 12 is exposed, and then the first spin-on hard mask layer 14, the second etch stop layer 15, the first bottom anti-reflective coating 16, and the first photoresist layer 17 can be removed to form a via 18. The etching can be performed using a conventional dry etching process, such as anisotropic dry etching, and the etching medium can be, for example, a mixed gas selected from CF4, CHF3, Ar, and a small amount of C4F8 and O2; the first spin-on hard mask layer 14, the second etch stop layer 15, the first bottom anti-reflective coating 16, and the first photoresist layer 17 can be removed, for example, using a process such as ashing.

[0024] Next, referring to Fig. 2c A thin second bottom anti-reflective coating 19 can be conformally deposited on the surface of the interlayer dielectric layer 13 and in the via 18, and in particular, in this embodiment, the thickness of the second bottom anti-reflective coating 19 is preferably in the range of 1-10 nm, and more preferably in the range of 2-5 nm. The material of the second bottom anti-reflective layer 19 is preferably an organic polymer. The present application first deposits a bottom anti-reflective layer before filling the second spin-on hard mask layer, so that the via can be better filled and defects caused by filling the second spin-on hard mask layer later can be avoided, and meanwhile, the performance caused by over-etching of the lower layer can be prevented. The second bottom anti-reflective layer can also be easily removed together with the second spin-on hard mask layer later.

[0025] Next, please refer to Fig. 2d The second spin-on hard mask layer 20 can be deposited to fill the via 18 and cover the surface of the second bottom anti-reflective layer 19, and then the third etching stop layer 21, the third bottom anti-reflective layer 22 and the second photoresist layer 23 can be deposited in sequence on the surface of the second spin-on hard mask layer 20. The material of the second spin-on hard mask layer 20 is, for example, a spin-on hard mask composition (SOH); the material of the third etching stop layer 21 is, for example, silicon oxynitride (SiON).

[0026] Next, the second photoresist layer 23 can be patterned to form a second photoresist pattern; it is worth mentioning that the position and shape of the opening of the second photoresist pattern correspond to the position and shape of the trench to be formed, and the via 18 is located in the opening of the second photoresist pattern; the patterning can be performed by using a conventional photolithography process.

[0027] Next, please refer to Fig. 2e The etching can be performed downward to form the trench 24, and then the second bottom anti-reflective layer 19, the second spin-on hard mask layer 20, the third etching stop layer 21, the third bottom anti-reflective layer 22 and the second photoresist layer 23 can be removed, for example, by using a process such as ashing.

[0028] Next, please refer to Fig. 2f The copper metal layer 25 can be formed in the via 18 and the trench 24. The copper metal layer can be formed by using various suitable process techniques familiar to those skilled in the art, such as an electroplating process, and before forming the copper metal layer, a copper metal diffusion barrier layer and a copper metal seed layer can be formed in sequence on the bottom and sidewall of the trench and the via. The copper metal diffusion barrier layer can prevent the copper in the copper metal layer from diffusing into the low-k dielectric layer, and the copper metal seed layer can enhance the adhesion between the copper metal layer and the copper metal diffusion barrier layer. The copper metal diffusion barrier layer and the copper metal seed layer can be formed by using various suitable process techniques familiar to those skilled in the art, for example, the copper metal diffusion barrier layer can be formed by using a physical vapor deposition process, and the copper metal seed layer can be formed by using a sputtering process or a chemical vapor deposition process. The material of the copper metal diffusion barrier layer can be a metal, a metal nitride or a combination thereof, and preferably a combination of Ta and TaN or a combination of Ti and TiN.

[0029] Then, the copper metal layer 25 can be subjected to chemical mechanical planarization treatment to expose the surface of the interlayer dielectric layer 13, thereby forming a dual damascene structure of the copper metal interconnection line 251 and the copper metal plug 252.

[0030] As mentioned above, the first via dual damascene method in the present application can better fill the via and avoid defects in filling the hard mask layer by first conformally depositing a thin bottom anti-reflective coating before filling the via with a spin-on hard mask or other mask protection material, and can prevent over-etching of the underlying layer and resulting poor performance.

[0031] In the above description, the patterning, etching and other technical details of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions and other shapes as required. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0032] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A via-first dual damascene method, comprising the steps of: forming a via in a dielectric layer of a semiconductor substrate; conformally depositing a thin bottom anti-reflective layer; the thickness of the bottom anti-reflective layer is 30-100 A; the bottom anti-reflective layer is selected from organic polymers; depositing a spin-on hard mask layer to fill the via; forming a trench in communication with the via above the via; the forming of the trench in communication with the via specifically comprises, after filling the spin-on hard mask layer, sequentially forming an etch stop layer, a bottom anti-reflective layer and a photoresist layer on the spin-on hard mask layer; performing a lithography and etching process to form a trench in communication with the via; filling a metal layer in the via and the trench.

2. The first via dual damascene method according to claim 1, wherein, the forming of the via specifically comprises, sequentially forming a spin-on hard mask layer, an etch stop layer, a bottom anti-reflective layer and a photoresist layer on the dielectric layer of the semiconductor substrate; performing a lithography and etching process to form a via in the dielectric layer.

3. The first via dual damascene process of claim 1, wherein, the metal layer is a copper metal layer.

4. The first via dual damascene method of claim 3, wherein, Before forming the copper metal layer, a copper metal diffusion barrier layer and a copper metal seed layer are sequentially formed on the bottom and sidewall of the trench and the via.

5. The first via dual damascene process of claim 1, wherein, After forming the trench in communication with the via above the via, the thin bottom anti-reflective layer is removed by an ashing process.

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