3D Memory and Method for Preparing the Same

Abstract

The present application provides a three-dimensional memory and a method for manufacturing the same. The method includes: forming a stacked structure including alternately stacked insulating layers and sacrificial layers on a substrate, and forming a channel hole penetrating the stacked structure; etching a part of the sacrificial layer through the channel hole to form a first groove; forming a first filling layer on the inner walls of the channel hole and the first groove, and forming a second filling layer on the first filling layer in the first groove; and performing an oxidation treatment on the part of the first filling layer not covered by the second filling layer to form a plurality of oxidation portions.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more particularly, to a structure and a manufacturing method of a three-dimensional memory (3D NAND). Background Art

[0002] Three-dimensional storage devices have large storage density and high storage capacity, and have been continuously developed and widely applied in recent years. Generally, in a 3D NAND structure, there are multiple vertically alternating stacked gate layers and insulating layers. However, with the increase in storage capacity, the number of stacked layers also increases, and with the miniaturization trend of the memory, the interlayer height decreases. Therefore, there are serious interferences during the read and write processes of the memory, seriously affecting the performance of the memory.

[0003] Therefore, on the premise of not changing the height of the memory, reducing the coupling interference between word lines is an urgent problem to be solved. Summary of the Invention

[0004] Some embodiments of this application provide a three-dimensional memory and a manufacturing method thereof that can at least partially solve the above problems existing in the prior art.

[0005] According to one aspect of this application, there is provided a manufacturing method of a three-dimensional memory, the method may include: forming a stacked structure including alternately stacked insulating layers and sacrificial layers on a substrate, and forming a channel hole penetrating the stacked structure; etching part of the sacrificial layer through the channel hole to form a first groove; forming a first filling layer on the inner walls of the channel hole and the first groove, and forming a second filling layer on the first filling layer in the first groove; and performing an oxidation treatment on the part of the first filling layer not covered by the second filling layer to form a plurality of oxidation parts.

[0006] In an embodiment of this application, forming a second filling layer on the first filling layer in the first groove may include: depositing a second filling layer on the first filling layer formed in the first groove and on the inner wall of the channel hole; and removing the part of the second filling layer outside the first groove while retaining the part inside the first groove.

[0007] In an embodiment of this application, the volume of each oxidation part may be greater than the volume of the corresponding first filling layer before oxidation.

[0008] In an embodiment of this application, the method may further include: removing the first filling layer and the second filling layer in the first groove; and forming a channel sacrificial layer inside a plurality of the first grooves.

[0009] In an embodiment of the present application, forming a channel sacrificial layer inside multiple said first grooves may include: depositing the channel sacrificial layer via the channel holes, where the channel sacrificial layer is located inside the first grooves and covers the oxidation part.

[0010] In an embodiment of the present application, the method may further include: removing the channel sacrificial layer inside the intervals between adjacent said oxidation parts and on the inner wall of the channel holes to form second grooves; forming a first dielectric layer on the inner walls of adjacent said second grooves and on the inner wall of the channel holes, and sequentially forming a first barrier layer and a charge trapping layer on the surface of the first dielectric layer; and removing the charge trapping layer on the inner wall of the channel holes so that the charge trapping layer is located inside the second grooves.

[0011] In an embodiment of the present application, the method may further include: removing a part of the channel sacrificial layer so that the remaining channel sacrificial layer is located inside the first grooves and inside part of the intervals between adjacent said oxidation parts; oxidizing the channel sacrificial layer inside the intervals of the oxidation parts to form third grooves between multiple adjacent said oxidation parts, and the oxidized channel sacrificial layer and the multiple spaced oxidation parts form a second barrier layer; forming a charge trapping layer on the surface of the second barrier layer; and removing the charge trapping layer on the inner wall of the channel holes so that the charge trapping layer is located inside the third grooves.

[0012] In an embodiment of the present application, the material of the sacrificial layer is the same as that of the channel sacrificial layer.

[0013] In an embodiment of the present application, the method may further include: forming a gate line gap that penetrates the stacked structure and extends to the substrate; and replacing the sacrificial layer and the channel sacrificial layer with a gate layer via the gate line gap.

[0014] In an embodiment of the present application, the material of the first filling layer may include polysilicon.

[0015] On the other hand, the present application provides a three-dimensional memory, which may include: a substrate; a stacked structure located on the substrate, including alternately stacked insulating layers and gate layers; and multiple oxidation parts located at one end of the insulating layer and correspondingly arranged with the insulating layer.

[0016] In an embodiment of the present application, the memory further includes: a channel structure that penetrates the stacked structure and includes a channel filling layer, and a channel layer, a tunneling layer, a discontinuous charge trapping layer, and a barrier layer that sequentially surround the channel filling layer, where the discontinuous charge trapping layer includes multiple storage sub-structures, and the storage sub-structures are correspondingly arranged with the gate layers.

[0017] In an embodiment of the present application, in a direction perpendicular to the substrate, the height of the oxidation portion may be greater than the height of the insulating layer.

[0018] In an embodiment of the present application, the barrier layer may include a first barrier layer, and the first barrier layer and a part of the tunneling layer surround the storage sub-structure.

[0019] In an embodiment of the present application, the barrier layer may include a plurality of spaced oxidation portions and a gate barrier layer. Wherein, the gate barrier layer is located at one end of the gate layer, and the plurality of spaced oxidation portions, the gate barrier layer and a part of the tunneling layer surround the storage sub-structure.

[0020] In an embodiment of the present application, the channel structure may further include: a first dielectric layer surrounding the first barrier layer.

[0021] In an embodiment of the present application, the material of the oxidation portion may include silicon oxide.

[0022] In an embodiment of the present application, in a direction perpendicular to the substrate, the height of the charge trapping layer is less than the height of the gate layer.

[0023] According to an aspect of the present application, there is provided a memory system, the memory system includes: a three-dimensional memory as described above; and a controller, electrically connected to the three-dimensional memory and controlling the three-dimensional memory to execute operation instructions.

[0024] According to an exemplary embodiment of the present application, by forming a plurality of oxidation portions corresponding to the sacrificial layer, discrete charge trapping layers can be formed in subsequent processes. And by oxidizing a part of the first filling layer, the width of the discrete charge trapping layer in a direction perpendicular to the substrate can be further reduced, the diffusion of charges stored therein along a direction perpendicular to the substrate can be reduced, and the loss of charges stored in the charge trapping layer can be reduced. And by etching a part of the sacrificial layer in the stacked structure to form a plurality of first grooves, part of the channel structure can be formed in the plurality of first grooves in subsequent processes, without additionally occupying the width of the channel hole. Therefore, on the basis of not increasing the width of the channel hole, the interference between adjacent memory cells can be reduced, the data retention ability of the three-dimensional memory can be enhanced, and the effectiveness and reliability of the memory can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, objects and advantages of the present application will become more obvious. Among them:

[0026] Figure 1 It is a flowchart of a method for manufacturing a three-dimensional memory according to an exemplary embodiment of the present application;

[0027] Figures 2 - 8 Schematic cross-sectional view of a partial preparation process of a 3D memory according to an exemplary embodiment of the present application;

[0028] Figures 9A - 9G Schematic cross-sectional view of a preparation process of a 3D memory according to an exemplary embodiment of the present application;

[0029] Figures 10A - 10F Schematic cross-sectional view of a preparation process of a 3D memory according to another exemplary embodiment of the present application; and

[0030] Figure 11A and Figure 11B Schematic diagram of a memory system according to an exemplary embodiment of the present application. Detailed Embodiments

[0031] To better understand the present application, more detailed descriptions of various aspects of the present application will be made with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] In the drawings, for ease of illustration, the sizes, dimensions, and shapes of the elements have been slightly adjusted. The drawings are only examples and are not drawn to scale strictly. As used herein, terms such as "substantially", "about", and similar terms are used as approximate terms and not as terms of degree, and are intended to illustrate the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. Additionally, in the present application, the order of description of the steps of the processes does not necessarily represent the order in which these processes occur in actual operation, unless otherwise clearly defined or derivable from the context.

[0033] It should also be understood that expressions such as "comprises", "comprising", "has", "including", and / or "including having" are open-ended rather than closed-ended expressions in this specification, which means that there are the stated features, elements, and / or components, but do not exclude the existence of one or more other features, elements, components, and / or their combinations. Further, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features rather than just an individual element in the list. Additionally, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It should also be understood that, unless explicitly stated otherwise in this application, terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0035] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The following will detail this application with reference to the drawings and in combination with the embodiments.

[0036] Figure 1 FIG. is a flowchart of a method for manufacturing a three-dimensional memory 1000 according to an embodiment of the present application. As Figure 1 shown, the manufacturing method 1000 of the three-dimensional memory may include:

[0037] Step S100: Form a stacked structure including alternately stacked insulating layers and sacrificial layers on a substrate, and form a channel hole penetrating the stacked structure;

[0038] Step S200: Etch part of the sacrificial layer through the channel hole to form a first groove;

[0039] Step S300: Form a first filling layer on the inner walls of the channel hole and the first groove, and form a second filling layer on the first filling layer in the first groove; and

[0040] Step S400: Oxidize the part of the first filling layer not covered by the second filling layer to form a plurality of oxidation parts.

[0041] The following will Figures 2 to 1 detail the specific processes of each step of the above manufacturing method 1000 in combination with

[0042] Step S100

[0043] Figure 2 FIG. is a schematic cross-sectional view after forming a channel hole on a substrate according to an exemplary embodiment of the present application. As Figure 2 shown, a stacked structure 120 including alternately stacked insulating layers 121 and sacrificial layers 122 is formed on a substrate 110, and a channel hole 130 penetrating the stacked structure 120 is formed.

[0044] The substrate 110 can be a single-crystalline silicon (Si) substrate, a single-crystalline germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. The material of the substrate 110 can also be a compound semiconductor. For example, the substrate 110 can be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate, etc. It should be noted that the substrate 110 of the present application can also be prepared using at least one of other semiconductor materials known in the art.

[0045] Exemplarily, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to deposit the insulating layer 121 and the sacrificial layer 122 to form the stacked structure 120. In some embodiments, due to the increasing requirements for the number of stacked layers, in order to reduce the deposition time to improve productivity, a deposition process with a higher deposition rate is usually adopted, such as chemical vapor deposition. The heights of the multiple sacrificial layers 122 can be the same or different, the heights of the multiple insulating layers 121 can be the same or different, and the heights of the insulating layer 121 and the sacrificial layer 122 can be set according to specific process requirements. The stacked structure 120 can include multiple pairs of insulating layers 121 and sacrificial layers 122 stacked alternately. For example, the stacked structure 120 can include 64 pairs, 128 pairs, or more than 128 pairs of insulating layers 121 and sacrificial layers 122. Although specific numbers of pairs of the insulating layer 121 and the sacrificial layer 122 are exemplified here, in other embodiments, other numbers of pairs of the insulating layer 121 and the sacrificial layer 122 can also be used, and the present application does not limit this.

[0046] In an exemplary embodiment, the materials selected for the insulating layer 121 and the sacrificial layer 122 can have different etching selectivity ratios. The sacrificial layer 122 can be removed in a subsequent process and replaced with a conductive material to form a gate layer. Optionally, the material of the insulating layer 121 can include, for example, silicon oxide, and the material of the sacrificial layer 122 can include, for example, silicon nitride. The more the number of layers of the insulating layer 121 and the sacrificial layer 122 in the stacked structure 120, the higher the integration degree, and the more the number of memory cells formed by it. The stacking number and stacking height of the stacked structure 120 can be designed according to actual storage requirements, and the present application does not make specific limitations on this.

[0047] In an exemplary embodiment, a channel hole 130 can be formed in the stacked structure 120 by using, for example, photolithography, dry etching, or wet etching processes. The channel hole 130 can extend vertically in the direction of the substrate 110, and a part of the substrate 110 is exposed through the channel hole.

[0048] Step S200

[0049] In an exemplary embodiment of the present application, through the channel holes 130, a part of the sacrificial layer 122 is etched. Since the materials selected for the insulating layer 121 and the sacrificial layer 122 may have different etching selectivity ratios, a suitable etchant can be selected to remove a part of the sacrificial layer 122, forming a plurality of first grooves 123. Figure 3 FIG. is a cross-sectional schematic view after forming a plurality of first grooves according to an exemplary embodiment of the present application. As Figure 3 shown, the bottom of the first groove 123 is located in the sacrificial layer 122, and in the direction perpendicular to the substrate 110, the width of the bottom of the first groove 123 is equal to the height of the corresponding sacrificial layer 122.

[0050] Step S300

[0051] Through the channel holes 130, a first filling layer 131 is formed on the inner walls of the channel holes 130 and the plurality of first grooves 123, and a second filling layer 132 is formed inside the plurality of first grooves 123. Figure 4 FIG. is a cross-sectional schematic view after forming a plurality of first filling layers according to an exemplary embodiment of the present application. In an exemplary embodiment, a suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to form the first filling layer 131 on the inner walls of the channel holes 130 and the plurality of first grooves 123, as Figure 4 shown, wherein the material of the first filling layer 131 is a material whose volume can increase after oxidation, such as polysilicon.

[0052] Figure 5A and Figure 5B FIG. is a cross-sectional schematic view of the process of forming a plurality of second filling layers according to an exemplary embodiment of the present application. In an exemplary embodiment, a suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to deposit the second filling layer 132 on the first filling layer 131, as Figure 5A shown. Then, an isotropic etching method can be used. By strictly controlling the etching time, a part of the second filling layer 132 is removed, so that the remaining second filling layer 132 is located inside the first groove (not shown in the figure). The etched second filling layer 132 is discontinuous. After etching the second filling layer 132, the first filling layer 131 located on the inner wall of the channel hole 130 can be exposed, as Figure 5BAs shown. Among them, the materials of the second filling layer 132 and the first filling layer 131 may have different etching selectivity ratios, and the material of the second filling layer 132 needs to have good oxidation resistance. Since the second filling layer 132 and the first filling layer 131 have different etching selectivity ratios, during the etching process, appropriate etchants can be selected and the etching time can be controlled so that the remaining second filling layer 132 is only located inside the first groove after the first filling layer 131 is deposited, exposing the first filling layer 131 on the sidewall of the channel hole 130, and in subsequent processes, only the first filling layer 131 not covered by the second filling layer 132 can be processed.

[0053] Step S400

[0054] Figure 6 It is a cross-sectional schematic diagram after forming multiple oxidation parts according to an exemplary embodiment of the present application. In the exemplary embodiment of the present application, the first filling layer 131 not covered by the second filling layer 132, that is, the first filling layer 131 on the sidewall of the channel hole 130, is oxidized to form multiple oxidation parts 133, and an interval 134 is formed between adjacent oxidation parts 133. Since the second filling layer 132 has good oxidation resistance, the second filling layer 132 is not oxidized during the oxidation process. The material of the oxidation part 133 may include, for example, silicon oxide, etc.

[0055] According to an exemplary embodiment of the present application, by oxidizing the first filling layer on the sidewall of the channel hole, its volume becomes larger and it changes from a semiconductor to an insulating material. Therefore, in the direction perpendicular to the substrate, the interval between adjacent oxidation parts is smaller than the height of the sacrificial layer. After forming the storage unit subsequently, it can effectively resist the diffusion of charges between multiple storage units, thereby reducing the interference between storage units and improving the effectiveness and reliability of the memory.

[0056] In the exemplary embodiment of the present application, the method for manufacturing a three-dimensional memory may further include: removing the second filling layer and the unoxidized first filling layer; and forming a channel sacrificial layer inside multiple first grooves via the channel hole.

[0057] The second filling layer 132 and the unoxidized first filling layer 131 located inside the first groove (not shown in the figure) can be removed by using, for example, photolithography, dry etching, or wet etching processes. After removing the second filling layer 132 and the unoxidized first filling layer 131, a first groove 123 can be formed respectively, and an interval 134 can be reformed between the oxidation parts 133, as Figure 7 shown. Among them, in the direction perpendicular to the substrate 110, the width of the bottom of the first groove 123 is greater than the interval 134 between adjacent oxidation parts 133.

[0058] In an exemplary embodiment, a suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof may be used to deposit a channel sacrificial layer 135 via the channel hole 130. As Figure 8 shown, the channel sacrificial layer 135 is located within the interval 134 between the first groove 123 and the oxidation portion 133, as well as on the inner wall of the channel hole 130. Among them, the material of the channel sacrificial layer 135 may be the same as that of the sacrificial layer 122, such as silicon nitride. When the materials of the channel sacrificial layer 135 and the sacrificial layer 122 are the same, it is beneficial for the subsequent process to form the gate layer. The channel sacrificial layer and the sacrificial layer in the stacked structure can be removed simultaneously through a single etching process. However, those skilled in the art know that the materials of the channel sacrificial layer 135 and the sacrificial layer 122 may also be different, and the present application does not limit this.

[0059] In an embodiment of the present application, an isotropic etching method may be used to remove the channel sacrificial layer 135 within the interval 134 between the oxidation portions 133 by strictly controlling the etching time, so that the channel sacrificial layer 135 is located within a plurality of first grooves. Among them, the adjacent oxidation portion 133 and the channel sacrificial layer 135 within the middle first groove form a second groove 136, as Figure 9A shown. The second groove 136 corresponds to the sacrificial layer 122, and in the direction perpendicular to the substrate 110, the width of the second groove 136 is smaller than the height of the sacrificial layer 122.

[0060] Then, a suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof may be used to deposit a first dielectric layer 141 via the channel hole 130, as Figure 9B shown. Among them, the first dielectric layer 141 may be selected from high-k materials such as alumina or hafnium oxide. The first dielectric layer 141 can, to a certain extent, prevent the diffusion of the subsequent charge trapping layer material, and can be used as an etching stop layer during the formation of the gate to further protect the channel structure. However, those skilled in the art know that the first dielectric layer in the embodiment of the present application is a preferred embodiment, and the first dielectric layer may also not be formed.

[0061] Furthermore, a suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof may be used to sequentially deposit a first barrier layer 142 and a charge trapping layer 143 on the surface of the first dielectric layer 141 via the channel hole 130, as Figure 9C and 9DAs shown. The first blocking layer 142 is used to block the outflow of the stored charges in the charge trapping layer 143. The material of the first blocking layer 142 may include an oxide, such as silicon oxide. The charge trapping layer 143 is used to trap charges during the memory programming process. The stored data can be further obtained according to the amount of charge stored in the charge trapping layer 143. The material of the charge trapping layer 143 may include a nitride, such as silicon nitride.

[0062] As Figure 9E shown, the charge trapping layer 143 on the inner wall of the channel hole 130 is removed, and then discrete charge trapping layers 143 are obtained. Then, a tunneling layer 144 and a channel layer 145 can be sequentially formed on the inner wall of the channel hole 130 by using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The material of the tunneling layer 144 may include an oxide, such as silicon oxide, and the material of the channel layer 145 may include a semiconductor material such as silicon (such as amorphous silicon, polycrystalline silicon, single crystal silicon). In some embodiments, after the channel layer 145 is formed, an insulating material may be filled in the remaining space of the channel hole to form a channel filling layer 146, as Figure 9F shown. The material of the channel filling layer 146 may include an oxide, such as silicon oxide. Optionally, one or more air gaps (not shown in the figure) may be formed during the filling process by controlling the filling process to relieve the structural stress. The first dielectric layer 141, the first blocking layer 142, the discrete charge trapping layers 143, the tunneling layer 144, the channel layer 145, and the channel filling layer 146 together form a channel structure.

[0063] According to an exemplary embodiment of the present application, the sacrificial layer can be replaced with a gate layer in a subsequent process. During the memory programming process, by applying a voltage to the gate layer, an electric field will be formed between the first blocking layer, the charge trapping layer, the tunneling layer, and the channel layer. As the voltage increases, electrons will undergo a tunneling effect and pass through the tunneling layer to reach the charge trapping layer. Since the charge trapping layer of the present application is discrete, the diffusion of the charges stored therein along the direction perpendicular to the substrate can be reduced, and the loss of the charges stored in the charge trapping layer can be reduced. By etching back the sacrificial layer and forming a part of the first dielectric layer, the first blocking layer, and the charge trapping layer, the width of the channel hole is not additionally occupied. Therefore, the interference between adjacent memory cells can be reduced on the basis of not increasing the width of the channel hole, the data retention ability of the three-dimensional memory can be enhanced, and the effectiveness and reliability of the memory can be improved.

[0064] In an exemplary embodiment of the present application, after forming the channel structure, processes such as lithography, dry etching, or wet etching can also be used to form a gate line gap (not shown in the figure) that penetrates the stacked structure and extends to the substrate. The sacrificial layer 122 and the channel sacrificial layer 135 are replaced with the gate layer 124 via the gate line gap. According to an exemplary embodiment of the present application, forming a first dielectric layer in the channel structure is beneficial to reducing the process difficulty of replacing the sacrificial layer and the channel sacrificial layer with the gate layer.

[0065] In an exemplary embodiment of the present application, before forming the gate layer 124, an adhesion layer and a barrier layer (not shown in the figure) surrounding the gate layer 124 can be sequentially formed. Among them, the adhesion layer is located between the gate layer 124 and the barrier layer and is used to increase the adhesion between the barrier layer and the gate layer 124. The barrier layer is located between the insulating layer 121 and the gate layer 124 and can, to a certain extent, prevent the diffusion of the gate layer 124 material. The material of the gate layer 124 can be selected from, for example, tungsten, cobalt, copper, aluminum, or doped crystalline silicon, etc. The material of the barrier layer can be selected from high dielectric constant materials such as alumina or hafnium oxide, and the material of the adhesion layer can be selected from, for example, tantalum nitride or titanium nitride. It should be understood that the materials of the gate layer, the adhesion layer, and the barrier layer are not limited to this, and other materials can also be used.

[0066] In another embodiment of the present application, after forming the channel sacrificial layer 135 as shown in Figure 8 An isotropic etching method can be used to remove part of the channel sacrificial layer 135 by strictly controlling the etching time, so that the remaining channel sacrificial layer 135 and the adjacent oxidation part 133 form a third pre-treatment groove 152-1, where the bottom of the third pre-treatment groove 152-1 is located between the adjacent oxidation parts 133, and in the direction parallel to the substrate, the height of the third pre-treatment groove 152-1 is less than the width of the oxidation part 133. As shown in Figure 10A Then, part of the channel sacrificial layer 135 near the bottom of the third pre-treatment groove 152-1 is oxidized, for example, by remote plasma oxidation (RPO), to form a gate blocking layer 151. The adjacent oxidation part 133 and the gate blocking layer 151 in the middle form a third groove 152, as shown in Figure 10B The third groove 152 corresponds to the sacrificial layer 122, and in the direction perpendicular to the substrate 110, the width of the third groove 152 is less than the height of the sacrificial layer 122.

[0067] Furthermore, a charge trapping layer 143 can be deposited via the channel hole 130 using a suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination of thin film deposition processes, as shown in Figure 10CAs shown. The charge trapping layer 143 is used to trap charges during the memory programming process. The stored data can be further obtained according to the amount of charges stored in the charge trapping layer 143. The material of the charge trapping layer 143 may include nitrides, such as silicon nitride.

[0068] As Figure 10D shown, the charge trapping layer 143 on the inner wall of the channel hole 130 is removed, and then discrete charge trapping layers 143 are obtained, so that the discrete charge trapping layers 143 are located inside a third groove (not shown in the figure). The discrete charge trapping layer 143 is used to trap charges during the memory programming process. The stored data can be further obtained according to the amount of charges stored in the charge trapping layer 143. The material of the charge trapping layer 143 may include nitrides, such as silicon nitride.

[0069] Then, a tunneling layer 144 and a channel layer 145 can be sequentially formed on the inner wall of the channel hole (not shown in the figure) by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The material of the tunneling layer 144 may include oxides, such as silicon oxide, and the material of the channel layer 145 may include semiconductor materials such as silicon (such as amorphous silicon, polycrystalline silicon, single crystal silicon), etc. In some embodiments, after the channel layer 145 is formed, an insulating material can be filled in the remaining space of the channel hole to form a channel filling layer 146, as Figure 10E shown. The material of the channel filling layer 146 may include oxides, such as silicon oxide. Optionally, by controlling the filling process, one or more air gaps (not shown in the figure) can be formed during the filling process to relieve the structural stress. Among them, the oxidation part 133 and the gate blocking layer 151 together form a second blocking layer. The second blocking layer is used to block the outflow of the charges stored in the charge trapping layer 143, prevent the diffusion of the charge trapping layer material, and can be used as an etching blocking layer during the formation of the gate to further protect the channel structure. The second blocking layer, the discrete charge trapping layer 143, the tunneling layer 144, the channel layer 145, and the channel filling layer 146 together form a channel structure.

[0070] According to an exemplary embodiment of the present application, the sacrificial layer can be replaced with a gate layer through subsequent processes. During the memory programming process, by applying a voltage to the gate layer, an electric field will be formed between the first blocking layer, the charge trapping layer, the tunneling layer, and the channel layer. As the voltage increases, electrons will undergo a tunneling effect and pass through the tunneling layer to reach the charge trapping layer. Since the charge trapping layer of the present application is discrete, the diffusion of the charges stored therein along the direction perpendicular to the substrate can be reduced, and the loss of the charges stored in the charge trapping layer can be reduced. By back-etching the sacrificial layer and forming a part of the second blocking layer and the charge trapping layer, the width of the channel hole is not additionally occupied. Therefore, on the basis of not increasing the width of the channel hole, the interference between adjacent memory cells can be reduced, the data retention ability of the three-dimensional memory can be enhanced, and the effectiveness and reliability of the memory can be improved.

[0071] In an exemplary embodiment of the present application, after forming the channel structure, processes such as lithography, dry etching, or wet etching may be employed to form a gate line gap (not shown in the figure) that penetrates the stacked structure and extends to the substrate. And the sacrificial layer 122 and the channel sacrificial layer 135 are replaced with the gate layer 124 via the gate line gap. According to an exemplary embodiment of the present application, forming a first dielectric layer in the channel structure is beneficial to reducing the process difficulty of replacing the sacrificial layer and the channel sacrificial layer with the gate layer.

[0072] In an exemplary embodiment of the present application, before forming the gate layer 124, an adhesion layer and a barrier layer (not shown in the figure) surrounding the gate layer 124 may be sequentially formed. Among them, the adhesion layer is located between the gate layer 124 and the barrier layer and is used to increase the adhesion between the barrier layer and the gate layer 124. The barrier layer is located between the insulating layer 121 and the gate layer 124 and can, to a certain extent, prevent the diffusion of the material of the gate layer 124. The material of the gate layer 124 may be selected from, for example, tungsten, cobalt, copper, aluminum, or doped crystalline silicon, etc. The material of the barrier layer may be selected from high dielectric constant materials such as alumina or hafnium oxide, and the material of the adhesion layer may be selected from, for example, tantalum nitride or titanium nitride. It should be understood that the materials of the gate layer, the adhesion layer, and the barrier layer are not limited thereto, and other materials may also be used.

[0073] On the other hand, the present application also provides a three-dimensional memory, which may at least include: a substrate, a stacked structure, and a plurality of oxidation parts.

[0074] In an exemplary embodiment of the present application, as Figure 9G shown, the three-dimensional memory may include a substrate 110; a stacked structure 120-1 located on the substrate 110, including alternately stacked insulating layers 121 and gate layers 124; and a plurality of oxidation parts 133 located at one end of the insulating layer 121. Among them, the plurality of oxidation parts 133 are correspondingly arranged with the insulating layer 121, and in the direction perpendicular to the substrate 110, the height of the oxidation part 133 is greater than the height of the insulating layer 121, and the material of the oxidation part 133 may include silicon oxide.

[0075] The three-dimensional memory may further include a channel structure penetrating the stacked structure. Among them, the channel structure may include a channel filling layer 146 located in the core, and a channel layer 145, a tunneling layer 144, a discontinuous charge trapping layer 143, and a first barrier layer 142 sequentially surrounding the channel filling layer 146. Among them, the discontinuous charge trapping layer includes a plurality of storage sub-structures, the storage sub-structures are correspondingly arranged with the gate layer 124, and the first barrier layer 142 and a part of the tunneling layer 144 surround the storage sub-structures.

[0076] In an exemplary embodiment of the present application, the channel structure may further include a first dielectric layer 141 surrounding the first blocking layer 142. The first dielectric layer 141 may be made of a high-k material such as alumina or hafnium oxide. The first dielectric layer 141 can, to a certain extent, prevent the diffusion of the subsequent charge trapping layer material and can serve as an etching stop layer during the formation of the gate, further protecting the channel structure.

[0077] According to an exemplary embodiment of the present application, during the memory programming process, by applying a voltage to the gate layer, an electric field is formed between the first blocking layer, the charge trapping layer, the tunneling layer, and the channel layer. As the voltage increases, electrons will undergo a tunneling effect and pass through the tunneling layer to reach the charge trapping layer. Since the charge trapping layer of the present application is discrete, the diffusion of the charges stored therein along the direction perpendicular to the substrate can be reduced, and the loss of the stored charges in the charge trapping layer can be reduced. Moreover, the first dielectric layer, the first blocking layer, and the charge trapping layer surrounding the memory substructure do not additionally occupy the width of the channel hole. Therefore, on the basis of not increasing the width of the channel hole, the interference between adjacent memory cells can be reduced, the data retention ability of the 3D memory can be enhanced, and the effectiveness and reliability of the memory can be improved.

[0078] In another exemplary embodiment of the present application, the 3D memory, as Figure 10F shown, may include a substrate 110; a stacked structure 120-1 located on the substrate 110, including alternately stacked insulating layers 121 and gate layers 124; a plurality of oxidation portions 133 located at one end of the insulating layer 121. Among them, the plurality of oxidation portions 133 are correspondingly arranged with the insulating layer 121, and in the direction perpendicular to the substrate 110, the height of the oxidation portion 133 is greater than the height of the insulating layer 121. The material of the oxidation portion 133 may include silicon oxide.

[0079] The 3D memory may further include a channel structure penetrating the stacked structure. Among them, the channel structure may include a channel filling layer 146 located in the core, and a channel layer 145, a tunneling layer 144, a discontinuous charge trapping layer 143, and a second blocking layer sequentially surrounding the channel filling layer 146. The discontinuous charge trapping layer 143 includes a plurality of memory substructures, and the memory substructures are correspondingly arranged with the gate layer 124. The second blocking layer may include the oxidation portion 133 and a gate blocking layer 151. The gate blocking layer 151 is located at one end of the gate layer 124, and the second blocking layer and a part of the tunneling layer 144 surround the memory substructure.

[0080] According to an exemplary embodiment of the present application, during the memory programming process, by applying a voltage to the gate layer, an electric field is formed between the second blocking layer, the charge trapping layer, the tunneling layer, and the channel layer. As the voltage increases, electrons will undergo a tunneling effect and pass through the tunneling layer to reach the charge trapping layer. Since the charge trapping layer of the present application is discrete, the diffusion of the charges stored therein along the direction perpendicular to the substrate can be reduced, and the loss of the stored charges in the charge trapping layer can be reduced. Moreover, the second blocking layer and the charge trapping layer surrounding the storage sub-structure do not additionally occupy the width of the channel hole. Therefore, on the basis of not increasing the width of the channel hole, the interference between adjacent memory cells can be reduced, the data retention ability of the 3D memory can be enhanced, and the effectiveness and reliability of the memory can be improved.

[0081] Since the content and structure involved in describing the manufacturing method 1000 above can be fully or partially applied to the 3D memory structure described herein, the content related or similar thereto will not be described in detail.

[0082] A memory system according to an exemplary embodiment of the present application is as Figure 11A shown. The controller 41 and a single memory 42 can be integrated into the memory system 400a. The controller 41 can control the memory 42 through, for example, a channel (not shown), and the memory 42 can perform operations based on the control of the controller 41. The memory 42 can receive commands and addresses from the controller 41 through the channel and access the area selected from the storage array in response to the address. More specifically, the controller 41 can send commands and addresses for executing the programming operation method 1000 described in any of the above embodiments through the channel, causing the memory 42 to execute the programming operation method.

[0083] In some exemplary embodiments, the controller 41 and one or more memories 42 can be integrated into various types of storage systems. In other words, the memory systems 400a, 400b can be implemented and packaged into different types of final electronic products. In an example as Figure 11A shown, the controller 41 and the memory 42 can be integrated into a memory system 400a in the form of a memory card. The memory card can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a Universal Flash Storage card (UFS), etc. The memory system 400a in the form of a memory card can also include a memory card connector 43 for coupling it to a host (not shown).

[0084] A memory system according to an exemplary embodiment of the present application is as Figure 11BAs shown, the controller 41 and the plurality of memories 42 may be integrated into the memory system 400b. The controller 41 and the plurality of memories 42 may be integrated into the memory system 400b formed by a solid state drive (SSD). The solid state drive (SSD) may further include an SSD connector 43 for coupling it to a host. In some embodiments, the storage capacity and / or operating speed of the solid state drive (SSD) may be higher than those of a memory card.

[0085] The specific embodiments described above further elaborate on the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that, the method comprises: forming a stacked structure including alternately stacked insulating layers and sacrificial layers on a substrate, and forming a channel hole penetrating the stacked structure; etching part of the sacrificial layer through the channel hole to form a first groove; forming a first filling layer on the inner walls of the channel hole and the first groove, and forming a second filling layer on the first filling layer in the first groove; performing an oxidation treatment on the part of the first filling layer not covered by the second filling layer to form a plurality of oxidation parts, wherein, in a direction perpendicular to the substrate, the interval between adjacent oxidation parts is smaller than the height of the sacrificial layer; and forming a discontinuous charge trapping layer, wherein the charge trapping layer includes a plurality of storage sub-structures located between adjacent oxidation parts.

2. The method according to claim 1, wherein, forming a second filling layer on the first filling layer in the first groove includes: depositing a second filling layer on the first filling layer formed in the first groove and on the inner wall of the channel hole; and removing the part of the second filling layer located outside the first groove while retaining the part located inside the first groove.

3. The method according to claim 1, wherein, the volume of each oxidation part is greater than the volume of the corresponding first filling layer before oxidation.

4. The method according to claim 1, wherein, the method further comprises: removing the first filling layer and the second filling layer in the first groove; and forming a channel sacrificial layer inside a plurality of the first grooves.

5. The method according to claim 4, wherein, forming a channel sacrificial layer inside a plurality of the first grooves includes: depositing a channel sacrificial layer via the channel hole, the channel sacrificial layer being located inside the first groove and covering the oxidation parts.

6. The method according to claim 5, wherein, the method further comprises: removing the channel sacrificial layer within the interval between adjacent oxidation parts and on the inner wall of the channel hole to form a second groove; forming a first dielectric layer on the inner walls of adjacent second grooves and on the inner wall of the channel hole, and sequentially forming a first blocking layer and the charge trapping layer on the surface of the first dielectric layer; and removing the charge trapping layer on the inner wall of the channel hole so that the charge trapping layer is located inside the second groove.

7. The method according to claim 5, wherein, the method further comprises: removing part of the channel sacrificial layer so that the remaining channel sacrificial layer is located inside the first groove and within part of the interval between adjacent oxidation parts; performing an oxidation treatment on the channel sacrificial layer within the interval between the oxidation parts to form a third groove between a plurality of adjacent oxidation parts, and the oxidized channel sacrificial layer and the plurality of spaced oxidation parts form a second blocking layer; forming the charge trapping layer on the surface of the second blocking layer; and removing the charge trapping layer on the inner wall of the channel hole so that the charge trapping layer is located inside the third groove.

8. The method according to claim 6 or 7, wherein, The sacrificial layer is made of the same material as the channel sacrificial layer.

9. The method according to claim 8, wherein, the method further comprises: forming a gate line gap that penetrates the stacked structure and extends to the substrate; and replacing the sacrificial layer and the channel sacrificial layer with a gate layer via the gate line gap.

10. The method according to claim 1, wherein, the material of the first filling layer includes polysilicon.

11. A three-dimensional memory, characterized in that, it includes: a substrate; a stacked structure located on the substrate, including alternately stacked insulating layers and gate layers; a plurality of oxidation portions arranged in the stacking direction of the stacked structure, the oxidation portions being located at one end of the insulating layer and corresponding to the insulating layer, wherein, in the stacking direction, the distance between adjacent oxidation portions is less than the height of the gate layer located therebetween; and a discontinuous charge trapping layer, including a plurality of memory sub-structures arranged in the stacking direction, and at least part of the memory sub-structures being located between adjacent oxidation portions.

12. The three-dimensional memory according to claim 11, wherein, the memory further includes: a channel structure that penetrates the stacked structure and includes a channel filling layer, and a channel layer, a tunneling layer, the charge trapping layer, and a blocking layer that sequentially surround the channel filling layer, wherein, the memory sub-structures are correspondingly arranged with the gate layers.

13. The three-dimensional memory according to claim 12, wherein, the blocking layer includes a first blocking layer, and the first blocking layer and part of the tunneling layer surround the memory sub-structures.

14. The three-dimensional memory according to claim 12, wherein, the blocking layer includes a plurality of spaced oxidation portions and a gate blocking layer, wherein the gate blocking layer is located at one end of the gate layer, and the plurality of spaced oxidation portions, the gate blocking layer, and part of the tunneling layer surround the memory sub-structures.

15. The three-dimensional memory according to claim 13, wherein, the channel structure further includes: a first dielectric layer that surrounds the first blocking layer.

16. The three-dimensional memory according to claim 11, wherein, the material of the oxidation portion includes silicon oxide.

17. The three-dimensional memory according to claim 11, wherein, in a direction perpendicular to the substrate, the height of the charge trapping layer is less than the height of the gate layer.

18. A memory system, characterized in that, the memory system includes: the three-dimensional memory according to claims 11-17; and a controller electrically connected to the three-dimensional memory and controlling the three-dimensional memory to execute operation instructions.

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