A display panel and a method for manufacturing the same

Abstract

The embodiment of the present invention discloses a display panel and a preparation method thereof, comprising a non-display area and a display area surrounding the non-display area; and a substrate layer extending from the display area to the non-display area; and a functional structure layer arranged on the substrate layer; wherein the functional structure layer comprises a first active layer and a second active layer, and the first active layer and the second active layer are located in different film layers. By moving the second active layer of the switching transistor upward, the second active layer is kept away from the flexible substrate layer, and the influence of back channel etching on the switching transistor is weakened; and the first gate layer of the switching transistor is located below the second active layer, which can shield the polarization effect of the flexible substrate, improve the reliability of the switching transistor, and thus solve the problems of afterimage and brightness reduction of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a display panel and a method for preparing the same. Background Art

[0002] Compared with traditional liquid crystal displays, the reliability of TFT in the pixel circuit of organic light emitting diode (OLED) display technology is significantly affected by back channel etching due to the material properties of its flexible substrate PI. The reliability of TFT is a key factor affecting the luminance drop. Usually, image sticking is also one of the main phenomena of luminance drop.

[0003] The TFTs that mainly affect the brightness drop include the driver transistor (Driver TFT) and the switching transistor (DualGate TF), and the switching transistor is T3. According to the research on the afterimage of the display panel, it is found that T3 is the key factor affecting the brightness drop.

[0004] Therefore, it is necessary to develop a new type of display panel to reduce the impact of back channel etching on TFT. Summary of the invention

[0005] An embodiment of the present invention provides a display panel to solve the technical problems of image retention and brightness reduction of the display panel in the prior art.

[0006] In order to solve the above technical problems, the embodiments of the present invention disclose the following technical solutions:

[0007] On the one hand, a display panel is provided, comprising a non-display area and a display area surrounding the non-display area; and a substrate layer extending from the display area to the non-display area; and a functional structure layer disposed on the substrate layer; wherein the functional structure layer comprises a first active layer and a second active layer, and the first active layer and the second active layer are located in different film layers.

[0008] In addition to or instead of one or more features disclosed above, the substrate layer includes a first flexible substrate; a first buffer layer disposed on the first flexible substrate; a second flexible substrate disposed on the second buffer layer; and a second buffer layer disposed on the second flexible substrate.

[0009] In addition to one or more of the features disclosed above, or as an alternative, the functional structure layer includes a protective layer, which is arranged on the second buffer layer and extends from the display area to the non-display area; a first active layer, which is arranged on the protective layer in the display area; a first gate insulating layer, which is arranged on the first active layer and covers the first active layer, and extends from the display area to the non-display area; a first gate layer, which is arranged on the first gate insulating layer in the display area; a second gate insulating layer, which is arranged on the first gate layer and covers the first gate layer, and extends from the display area to the non-display area; a second active layer, which is arranged on the second gate insulating layer in the display area; a first interlayer dielectric layer, which is arranged on the second active layer and covers the second active layer, and extends from the display area to the non-display area; a second gate layer, which is arranged on the first interlayer dielectric layer in the display area; a second interlayer dielectric layer, which is arranged on the second gate layer and extends from the display area to the non-display area; and a source-drain electrode layer, which is arranged on the surface of the second interlayer dielectric layer in the display area.

[0010] In addition to one or more of the features disclosed above, or as an alternative, the functional structure layer also includes a first via, which is arranged in the display area and extends from a side of the second interlayer dielectric layer away from the substrate layer to a side of the first active layer away from the substrate layer, and the source and drain layer is connected to the first active layer through the first via; a second via is arranged in the display area and extends from a side of the second interlayer dielectric layer away from the substrate layer to a side of the second active layer away from the substrate layer, and the source and drain layer is connected to the second active layer through the second via.

[0011] In addition to or as an alternative to one or more features disclosed above, the material filled in the first via hole and the second via hole is the same as the source and drain electrode layer.

[0012] In addition to one or more of the features disclosed above, or as an alternative, it also includes a slot hole, which is arranged in the non-display area, and the slot hole extends from the side of the functional structure layer away from the substrate layer through the functional structure layer to the surface of the second flexible substrate layer, and the second flexible substrate layer is exposed in the slot hole.

[0013] In addition to one or more of the features disclosed above, or as an alternative, the orthographic projection of the first active layer on the substrate layer does not overlap with the orthographic projection of the second active layer on the substrate layer; the functional structure layer under the orthographic projection of the first active layer on the substrate layer constitutes a driving transistor; and the functional structure layer under the orthographic projection of the second active layer on the substrate layer constitutes a switching transistor.

[0014] In addition to or as an alternative to one or more of the features disclosed above, the driving transistor further includes a third gate layer disposed between the second flexible substrate and the second buffer layer.

[0015] In addition to or as an alternative to one or more of the features disclosed above, the driving transistor also includes a third via extending from a side of the first gate insulating layer away from the first flexible substrate to a side of the third gate layer away from the first flexible substrate, and the first gate layer is connected to the third gate layer through the third via.

[0016] On the other hand, a preparation method is further disclosed for preparing the display panel of the present invention, wherein the display panel comprises a non-display area and a display area surrounding the non-display area, and the preparation method comprises the following steps:

[0017] Providing a substrate layer extending from the display area to the non-display area;

[0018] Preparing a functional structure layer on the substrate layer;

[0019] The functional structure layer includes a first active layer and a second active layer, and the first active layer and the second active layer are located in different film layers.

[0020] One of the above technical solutions has the following advantages or beneficial effects: by moving the second active layer of the switching transistor upward, the second active layer is kept away from the flexible substrate layer, thereby reducing the impact of back channel etching on the switching transistor; and the first gate layer of the switching transistor is located below the second active layer, which can shield the polarization effect of the flexible substrate and improve the reliability of the switching transistor, thereby solving the problems of afterimage and brightness reduction of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The technical solutions and other beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0022] Figure 1 A schematic cross-sectional structural diagram of a display panel provided in Embodiment 1 of the present invention;

[0023] Figure 2 A flow chart of a method for manufacturing a display panel provided in Embodiment 1 of the present invention;

[0024] Figure 3 This is a schematic cross-sectional structural diagram of a display panel provided in Embodiment 2 of the present invention. Description of the drawings:

[0026] Display panel-100; Display area-101;

[0027] Non-display area-102; Substrate layer-110;

[0028] Functional structure layer-120; Slot-140;

[0029] First flexible substrate-111; First buffer layer-112;

[0030] Second flexible substrate-113; Second buffer layer-114;

[0031] Protective layer-1201; First active layer-121;

[0032] First gate layer-123; First gate insulating layer-122;

[0033] A second gate layer-125; A second gate insulating layer-124;

[0034] First interlayer dielectric layer-126; Source and drain layer-127;

[0035] A second active layer-128; A second interlayer dielectric layer-129;

[0036] First via hole-161; Second via hole-162;

[0037] The third via hole-163; The third gate-130. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0039] Example 1

[0040] The embodiment of the present invention provides a display panel 100. Figure 1 , Figure 1 The cross-sectional structure diagram of the display panel 100 provided in an embodiment of the present invention includes a display area 101 and a non-display area 102 surrounding the display area 101 . The display panel 100 includes a substrate layer 110 , a functional structure layer 120 and a slot 140 .

[0041] The substrate layer 110 extends from the display area 101 to the non-display area 102, and includes a first flexible substrate 111, a first buffer layer 112, a second flexible substrate 113 and a second buffer layer 114. The first buffer layer 112 is disposed on the first flexible substrate 111, the second flexible substrate 113 is disposed on the first buffer layer 112, and the second buffer layer 114 is disposed on the second flexible substrate 113.

[0042] The functional structure layer 120 is arranged on the second buffer layer 114, and the functional structure layer 120 extends from the display area 101 to the non-display area 102. The functional structure layer 120 includes a protective layer 1201, a first active layer 121, a first gate insulating layer 122, a first gate layer 123, a second gate insulating layer 124, a second gate layer 125, a first interlayer dielectric layer 126, a source and drain layer 127, a second active layer 128 and a second interlayer dielectric layer.

[0043] The protective layer 1201 is disposed on the second buffer layer 114 and extends from the display area 101 to the non-display area 102; the first active layer 121 is disposed on the protective layer 1201 in the display area 101; the first gate insulating layer 122 It is arranged on the first active layer 121 and covers the first active layer 121, extending from the display area 101 to the non-display area 102; the first gate layer 123 is arranged on the first gate insulating layer 122 of the display area 101; the second gate insulating layer 124 is arranged on the first gate layer 123 and covers the first gate layer 123, extending from the display area 101 to the non-display area 102; the second active layer 128 is arranged on the second gate insulating layer 124 of the display area; the first interlayer dielectric layer 126 is arranged on the second gate layer 125, extending from the display area 101 to the non-display area 102; the second gate layer 125 is arranged on the first interlayer dielectric layer 126 of the display area 101; the second interlayer dielectric layer 129 is arranged on the second gate layer 125, extending from the display area 101 to the non-display area 102; the source and drain layer 127 is arranged on the surface of the second interlayer dielectric layer 129 of the display area 101.

[0044] The functional structure layer 120 further includes a first via hole 161 and a second via hole 162. The first via hole 161 is provided in the display area 101, extending from a side of the second interlayer dielectric layer 129 away from the second buffer layer 114 to a side of the first active layer 121 away from the second buffer layer 114, and the source-drain electrode layer 127 is connected to the first active layer 121 through the first via hole 161. The second via hole 162 is provided in the display area 101, extending from a side of the second interlayer dielectric layer 129 away from the second buffer layer 114 to a side of the second active layer 128 away from the second buffer layer 114, and the source-drain electrode layer 127 is connected to the second active layer 128 through the second via hole 162. The materials filled in the first via hole 161 and the second via hole 162 are the same as those in the source-drain electrode layer 127.

[0045] The orthographic projection of the first active layer 121 on the substrate layer 110 does not overlap with the orthographic projection of the second active layer 128 on the substrate layer. The functional structure layer 120 of the first active layer 121 under the orthographic projection of the substrate layer 110 constitutes a driving transistor, and the functional structure layer 120 of the second active layer 128 under the orthographic projection of the substrate layer 110 constitutes a switching transistor.

[0046] In the present invention, the driving transistor is called T1, and the switching transistor is called T3. In the experiment, the active layer in T1, the active layer in T2 (not shown), the active layer in T3, and the active layer in T4 (not shown) are moved up in batches, and the afterimage effect diagram obtained is as follows:

[0047]

[0048] It can be seen from the table that the afterimage problem will be greatly improved as long as the active layer in T3 is moved up.

[0049] Therefore, in the present application, the second active layer of the switching transistor is moved upward so that the second active layer is away from the flexible substrate layer, thereby reducing the impact of back channel etching on the switching transistor; and the first gate layer of the switching transistor is located below the second active layer, which can shield the polarization effect of the flexible substrate and improve the reliability of the switching transistor, thereby solving the problems of afterimage and brightness reduction of the display panel.

[0050] Since the second active layer 128 is moved upward, the second gate layer 125 is also moved upward. The second gate insulating layer 124 and the first interlayer dielectric layer 126 are separated from the second gate layer 125 and the first gate layer 123, so the distance d between the second gate layer 125 and the first gate layer 123 is increased. According to the capacitance formula

[0051]

[0052] ; When d increases, it is necessary to keep C unchanged and increase ε as well.

[0053] In order to increase ε, after preparing the first gate layer 123, the first gate layer 123 is doped twice, including doping the first gate layer 123 through the second gate insulating layer and doping the first gate layer 123 through the first interlayer dielectric layer 126. The specific doping dosage needs to be based on the working capacity of the pixel circuit and the actual process debugging.

[0054] The slot 140 is disposed in the non-display area 102 , and extends from a side of the light emitting device layer 130 away from the substrate layer 110 , through the functional structure layer 120 , to the surface of the second flexible substrate layer 113 . The second flexible substrate layer 113 is exposed in the slot 140 .

[0055] The embodiment of the present invention further provides a manufacturing method for manufacturing the display panel 100 of the present invention. Figure 2 , Figure 2 The present invention provides a flow chart of a method for manufacturing a display panel according to an embodiment of the present invention. The method for manufacturing the display panel includes the following steps 1 to 3.

[0056] Step 1: Provide a substrate layer 110 , wherein the substrate layer 110 extends from the display area 101 to the non-display area 102 .

[0057] Specifically, step 1 includes step 11 to step 14;

[0058] Step 11 : providing a first flexible substrate 111 , wherein the first flexible substrate 111 extends from the display area 101 to the non-display area 102 .

[0059] Step 12: Prepare a first buffer layer 112 on the first flexible substrate 111 , wherein the first buffer layer 112 extends from the display area 101 to the non-display area 102 .

[0060] Step 13 : preparing a second flexible substrate 113 on the first buffer layer 112 , wherein the second flexible substrate 113 extends from the display area 101 to the non-display area 102 .

[0061] Step 14: Prepare a second buffer layer 114 on the second flexible substrate 113 , wherein the second buffer layer 114 extends from the display area 101 to the non-display area 102 .

[0062] Step 2: Prepare a functional structure layer 120 on the second buffer layer 114, wherein the functional structure layer 120 extends from the display area 101 to the non-display area 102; the functional structure layer 120 includes a first active layer 121 and a second active layer 128, and the first active layer 121 and the second active layer 128 are located in different film layers.

[0063] Specifically, step 2 includes step 21-step 299;

[0064] Step 21 : preparing a protection layer 1201 on the second buffer layer 114 , wherein the protection layer 1201 extends from the display area 101 to the non-display area 102 .

[0065] Step 22: deposit polysilicon on the protective layer 1201 on the display area 101, prepare a semiconductor layer pattern by photolithography, and form a first active layer 121; the thickness of the first active layer 121 is

[0066] Step 23 : preparing a first gate insulating layer 122 on the first active layer 121 and covering the first active layer 121 , wherein the first gate insulating layer 122 extends from the display area 101 to the non-display area 102 .

[0067] Step 24: Prepare a first gate layer 123 on the first gate insulating layer 122 of the display area 101; use the first gate layer 123 as a mask to perform SD doping on the first active layer 121.

[0068] Step 25: Prepare a second gate insulating layer 124 on the first gate layer 123 and cover the first gate layer 123, the second gate insulating layer 124 extending from the display area 101 to the non-display area 102; and dope the first gate layer 123 through the second gate insulating layer.

[0069] Step 26: Prepare a second active layer 128 on the second gate insulating layer 124 in the display area.

[0070] Step 27 : preparing a first interlayer dielectric layer 126 on the second active layer 128 , extending from the display area 101 to the non-display area 102 ; and doping the first gate layer 123 through the first interlayer dielectric layer 126 .

[0071] Step 28: Prepare a second gate layer 125 on the first interlayer dielectric layer 126 of the display area 101; use the second gate layer 125 as a mask to perform SD doping on the second active layer 128.

[0072] Step 29: Prepare a second interlayer dielectric layer 129 on the second gate layer 125 , extending from the display area 101 to the non-display area 102 , and form the first via hole 161 , the second via hole 162 and the slot 140 by photolithography and dry etching.

[0073] The first via hole 161 , the second via hole 162 in the display area 101 and the slot hole 140 in the non-display area 102 are prepared at the same time, which can reduce the process and save the cost.

[0074] In this embodiment, the non-display area 102 is a bending area, and the slot 140 can reduce the bending stress and improve the yield of the display panel.

[0075] Step 299 : deposit source and drain electrodes on the surface of the second interlayer dielectric layer 129 , and connect to the first active layer 121 through the first via hole 161 , and connect to the second active layer 128 through the second via hole 162 , and prepare source and drain electrode patterns by photolithography and wet etching to form a source and drain electrode layer 127 .

[0076] Example 2

[0077] The display panel of this embodiment has a substantially similar structure to that of the embodiment 1. For details, please refer to the embodiment 1. The difference is that the driving transistor further includes a third gate layer 130 and a third via hole 163. For details, please refer to the embodiment 1. Figure 3 , Figure 3 A schematic diagram of a cross-sectional structure of a display panel provided in this embodiment. In this embodiment, the driving transistor further includes a third gate layer 130 and a third via 163, the third gate layer 130 is disposed between the second flexible substrate 113 and the second buffer layer 114, the third via 163 extends from a side of the first gate insulating layer 122 away from the first flexible substrate 111 to a side of the third gate layer 130 away from the first flexible substrate 111, and the first gate layer 123 is connected to the third gate layer 130 through the third via 163.

[0078] The third gate layer 130 of the driving transistor is located below the first active layer 121 and can play a shielding role, shield the polarization effect of the flexible substrate, and improve the reliability of the driving transistor.

[0079] The third via hole 163 is filled with the same material as the first gate layer 123 , and the first gate layer 123 and the third gate layer 130 are also filled with the same material.

[0080] The embodiment of the present invention further provides a manufacturing method for manufacturing the display panel 100 of the present invention. Figure 3 , Figure 3 The present invention provides a flow chart of a method for manufacturing a display panel according to an embodiment of the present invention. The method for manufacturing the display panel includes the following steps 1 to 3.

[0081] Step 1: Provide a substrate layer 110 , wherein the substrate layer 110 extends from the display area 101 to the non-display area 102 .

[0082] Specifically, step 1 includes step 11 to step 15;

[0083] Step 11 : providing a first flexible substrate 111 , wherein the first flexible substrate 111 extends from the display area 101 to the non-display area 102 .

[0084] Step 12: Prepare a first buffer layer 112 on the first flexible substrate 111 , wherein the first buffer layer 112 extends from the display area 101 to the non-display area 102 .

[0085] Step 13 : preparing a second flexible substrate 113 on the first buffer layer 112 , wherein the second flexible substrate 113 extends from the display area 101 to the non-display area 102 .

[0086] Step 14: Prepare a third gate layer on the second flexible substrate 113 in the display area 101 .

[0087] Step 15: Prepare a second buffer layer 114 on the second flexible substrate 113 , wherein the second buffer layer 114 extends from the display area 101 to the non-display area 102 .

[0088] Step 2: Prepare a functional structure layer 120 on the second buffer layer 114 , wherein the functional structure layer 120 extends from the display area 101 to the non-display area 102 .

[0089] Specifically, step 2 includes step 21-step 299;

[0090] Step 21 : preparing a protection layer 1201 on the second buffer layer 114 , wherein the protection layer 1201 extends from the display area 101 to the non-display area 102 .

[0091] Step 22: deposit polysilicon on the protective layer 1201 on the display area 101, prepare a semiconductor layer pattern by photolithography, and form a first active layer 121; the thickness of the first active layer 121 is

[0092] Step 23 : preparing a first gate insulating layer 122 on the first active layer 121 and covering the first active layer 121 , wherein the first gate insulating layer 122 extends from the display area 101 to the non-display area 102 .

[0093] Step 24 : preparing a first gate layer 123 on the first gate insulating layer 122 of the display area 101 ; and then preparing a third via hole 163 , connecting the first gate layer 123 to the third gate layer 130 through the third via hole 163 .

[0094] Since the third via hole 163 is very close to the first active layer 121, hydrogen added in the preparation of the third via hole 163 will diffuse into the first active layer 121, improving the conductor properties of the first active layer 121. Therefore, the first active layer 121 does not need to be SD doped, saving a procedure.

[0095] Step 25: Prepare a second gate insulating layer 124 on the first gate layer 123 and cover the first gate layer 123, the second gate insulating layer 124 extending from the display area 101 to the non-display area 102; and dope the first gate layer 123 through the second gate insulating layer.

[0096] Step 26: Prepare a second active layer 128 on the second gate insulating layer 124 in the display area.

[0097] Step 27 : preparing a first interlayer dielectric layer 126 on the second active layer 128 , extending from the display area 101 to the non-display area 102 ; and doping the first gate layer 123 through the first interlayer dielectric layer 126 .

[0098] Step 28: Prepare a second gate layer 125 on the first interlayer dielectric layer 126 of the display area 101; use the second gate layer 125 as a mask to perform SD doping on the second active layer 128.

[0099] Step 29: Prepare a second interlayer dielectric layer 129 on the second gate layer 125 , extending from the display area 101 to the non-display area 102 , and form the first via hole 161 , the second via hole 162 and the slot 140 by photolithography and dry etching.

[0100] The first via hole 161 , the second via hole 162 in the display area 101 and the slot hole 140 in the non-display area 102 are prepared at the same time, which can reduce the process and save the cost.

[0101] In this embodiment, the non-display area 102 is a bending area, and the slot 140 can reduce the bending stress and improve the yield of the display panel.

[0102] Step 299 : deposit source and drain electrodes on the surface of the second interlayer dielectric layer 129 , and connect to the first active layer 121 through the first via hole 161 , and connect to the second active layer 128 through the second via hole 162 , and prepare source and drain electrode patterns by photolithography and wet etching to form a source and drain electrode layer 127 .

[0103] The above is a detailed introduction to a display panel and a preparation method thereof provided in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: comprising a non-display area and a display area surrounding the non-display area; and a substrate layer extending from the display area to the non-display area; A functional structure layer is provided on the substrate layer; Wherein, the substrate layer includes a first flexible substrate, a first buffer layer, a second flexible substrate and a second buffer layer; the first buffer layer is arranged on the first flexible substrate; the second flexible substrate is arranged on the second buffer layer; the second buffer layer is arranged on the second flexible substrate; the functional structure layer includes a first active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second active layer, a first interlayer dielectric layer, a second gate layer, and a second interlayer dielectric layer, and the first active layer and the second active layer are located in different film layers; the first active layer is arranged on one side of the substrate layer, the first gate insulating layer is arranged on the first active layer and covers the first active layer, extending from the display area to the non-display area, the first gate layer is arranged on the first gate insulating layer in the display area, the second gate insulating layer is arranged on the first gate layer and covers the first gate layer, extending from the display area to the non-display area, the second active layer is arranged on the second gate insulating layer in the display area, the first interlayer dielectric layer is arranged on the second interlayer dielectric layer The first active layer is provided on the active layer and covers the second active layer, extending from the display area to the non-display area, the second gate layer is provided on the first interlayer dielectric layer in the display area, and the second interlayer dielectric layer is provided on the second gate layer, extending from the display area to the non-display area; the orthographic projection of the first active layer on the substrate layer does not overlap with the orthographic projection of the second active layer on the substrate layer; the functional structure layer of the first active layer under the orthographic projection of the substrate layer constitutes a driving transistor; the functional structure layer of the second active layer under the orthographic projection of the substrate layer constitutes a switching transistor; the driving transistor also includes a third gate layer, which is provided between the second flexible substrate and the second buffer layer, and the driving transistor also includes a third via hole, which extends from a side of the first gate insulating layer away from the first flexible substrate to a side of the third gate layer away from the first flexible substrate, the first gate layer is connected to the third gate layer through the third via hole, and the first active layer is not SD doped.

2. The display panel according to claim 1, wherein: The functional structural layer includes A protective layer, disposed on the second buffer layer, extending from the display area to the non-display area; The source-drain electrode layer is arranged on the surface of the second interlayer dielectric layer in the display area.

3. The display panel according to claim 2, wherein: The functional structural layer also includes a first via hole, provided in the display area, extending from a side of the second interlayer dielectric layer away from the substrate layer to a side of the first active layer away from the substrate layer, wherein the source and drain electrode layer is connected to the first active layer through the first via hole; The second via hole is provided in the display area, extending from a side of the second interlayer dielectric layer away from the substrate layer to a side of the second active layer away from the substrate layer, and the source and drain layer is connected to the second active layer through the second via hole.

4. The display panel according to claim 3, wherein: The material filled in the first via hole and the second via hole is the same as that of the source and drain electrode layer.

5. The display panel according to claim 1, wherein: It also includes a slot hole, which is arranged in the non-display area. The slot hole extends from a side of the functional structure layer away from the substrate layer through the functional structure layer to the surface of the second flexible base layer, and the second flexible base layer is exposed in the slot hole.

6. A preparation method, characterized in that: The method for preparing the display panel according to claim 1, wherein the display panel comprises a non-display area and a display area surrounding the non-display area, and the preparation method comprises the following steps: Providing a substrate layer extending from the display area to the non-display area; Preparing a functional structure layer on the substrate layer; The functional structure layer includes a first active layer and a second active layer, and the first active layer and the second active layer are located in different film layers.

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