Circuit board fault diagnosis method and system based on artificial intelligence

Abstract

The invention provides a circuit board fault diagnosis method and system based on artificial intelligence, and relates to the technical field of circuit board fault diagnosis, and the method comprises the steps: constructing a three-dimensional electromagnetic field simulation model of a circuit board, setting a plurality of virtual sensing probes in the three-dimensional electromagnetic field simulation model, and generating an electromagnetic field distortion distribution diagram; dividing a fault sensitive area of the circuit board based on the electromagnetic field distortion distribution diagram, outputting a performance degradation rate of each functional area of the circuit board, and generating a fault risk assessment matrix according to the performance degradation rate; performing function reconstruction on the circuit board according to the fault risk assessment matrix, establishing a dynamic fault-tolerant mechanism of the circuit board, generating a task load distribution strategy based on the dynamic fault-tolerant mechanism, and deploying the task load distribution strategy to a field programmable gate array of the circuit board. And self-repairing the circuit board by adjusting the logic structure of the field programmable gate array, verifying the repairing effect and outputting a diagnosis report.

Description

Technical Field

[0001] The present invention relates to circuit board fault diagnosis technology, and in particular to a circuit board fault diagnosis method and system based on artificial intelligence. Background Art

[0002] As electronic devices develop towards high-density integration and high performance, circuit board fault diagnosis and maintenance face huge challenges. Traditional fault diagnosis methods mainly rely on manual experience and fixed detection rules, which are difficult to cope with complex fault scenarios. In the existing technology, the diagnosis method based on the rule base has poor adaptability and is difficult to handle unknown types of faults; the method based on the statistical model has high computational complexity and lacks real-time performance; the method based on the expert system has difficulty in knowledge acquisition and high maintenance costs. Although some studies have begun to introduce machine learning technology for fault diagnosis, there are problems such as strong sample dependence and poor generalization ability. In addition, the existing diagnostic methods often separate fault detection and repair, and lack systematic solutions.

[0003] Therefore, it is urgent to establish an intelligent and adaptive circuit board fault diagnosis and repair mechanism to improve system reliability. Summary of the invention

[0004] The embodiments of the present invention provide a circuit board fault diagnosis method and system based on artificial intelligence, which can solve the problems in the prior art.

[0005] According to a first aspect of the embodiments of the present invention, Provided is a circuit board fault diagnosis method based on artificial intelligence, comprising: Constructing a three-dimensional electromagnetic field simulation model of a circuit board, setting a plurality of virtual sensor probes in the three-dimensional electromagnetic field simulation model, wherein the virtual sensor probes correspond one-to-one to the physical sensor positions of the circuit board, collecting measured data of the physical sensor and simulation data of the virtual sensor probes, establishing an abnormal behavior pattern library of the circuit board by comparing the deviation values ​​between the measured data and the simulation data, constructing a back propagation neural network according to the abnormal behavior pattern library, calculating the degree of electromagnetic field distortion of each functional area of ​​the circuit board based on the back propagation neural network, and generating an electromagnetic field distortion distribution map; Based on the electromagnetic field distortion distribution map, the fault-sensitive area of ​​the circuit board is divided, and an adaptive sampling array is deployed in the fault-sensitive area, wherein the adaptive sampling array includes a temperature sensing unit, a voltage sensing unit, and an electromagnetic sensing unit. A fault feature vector is constructed according to the multi-dimensional signal collected by the adaptive sampling array, and the fault feature vector is input into a pre-trained reinforcement learning model, and the performance degradation rate of each functional area of ​​the circuit board is output, and a fault risk assessment matrix is ​​generated according to the performance degradation rate; The circuit board is functionally reconstructed according to the fault risk assessment matrix, computing tasks in high-risk areas are migrated to low-risk areas, a dynamic fault-tolerant mechanism for the circuit board is established, a task load distribution strategy is generated based on the dynamic fault-tolerant mechanism, the task load distribution strategy is deployed to the field programmable gate array of the circuit board, the circuit board is autonomously repaired by adjusting the logical structure of the field programmable gate array, the operating data of the repaired circuit board is collected, the operating data is compared with the fault feature vector before repair, the repair effect is verified and a diagnostic report is output.

[0006] In an optional embodiment, By comparing the deviation values ​​of the measured data and the simulated data, an abnormal behavior pattern library of the circuit board is established, a back propagation neural network is constructed according to the abnormal behavior pattern library, and the electromagnetic field distortion degree of each functional area of ​​the circuit board is calculated based on the back propagation neural network to generate an electromagnetic field distortion distribution map, including: The time domain statistical features are generated by the adaptive wavelet decomposition module, the frequency domain spectrum features are generated by the fast Fourier transform module, and the attention mechanism is used to dynamically assign weights to the time domain statistical features and the frequency domain spectrum features to form a fusion feature vector; The recursive least squares algorithm is used to update the feature covariance matrix, and the Mahalanobis distance between the measured feature vector and the simulated feature vector is calculated based on the updated feature covariance matrix to obtain the abnormality sequence; A dual-criteria density clustering method based on local density and distance distribution is used to determine the cluster center of the abnormal degree sequence, and the clustering parameters are adaptively adjusted using the fractal dimension to form an abnormal pattern sequence. The abnormal mode sequence is decomposed through empirical mode decomposition to obtain the intrinsic mode function, and the evolution characteristics of the intrinsic mode function are extracted using a sliding time window. The time series association rules of the evolution characteristics are mined based on the improved Apriori algorithm to establish an abnormal behavior pattern library. A deep hybrid neural network is trained based on the abnormal behavior pattern library. The spatial domain features are extracted through the residual connection convolution layer. The temporal domain features are extracted using the long short-term memory unit and the gated recurrent unit. The topological domain features are extracted using the graph convolution layer. The extracted features are combined and input into the fully connected layer to output the electromagnetic field distortion prediction value. The spatial anisotropy constraints of circuit board wiring density and impedance distribution are introduced into the variogram. The Bayesian optimization algorithm is used to adjust the Kriging interpolation parameters. The electromagnetic field distortion prediction values ​​are spatially interpolated. The multi-resolution distortion distribution representation is constructed through wavelet transform to generate the electromagnetic field distortion distribution map.

[0007] In an optional embodiment, The spatial anisotropy constraints of circuit board wiring density and impedance distribution are introduced into the variogram, and the Kriging interpolation parameters are adjusted by Bayesian optimization algorithm. The electromagnetic field distortion prediction value is spatially interpolated, and a multi-resolution distortion distribution representation is constructed by wavelet transform. The electromagnetic field distortion distribution map is generated, including: Constructing a density weight matrix based on the wiring density distribution of the circuit board, and constructing an impedance weight matrix based on the impedance distribution of the circuit board, and combining the density weight matrix and the impedance weight matrix through a rotation matrix to form an anisotropic matrix; Using the anisotropy matrix to construct an exponential variogram, the variogram includes a nugget effect value, a sill value, and a spatial vector product term of the anisotropy matrix; An optimization objective function including an interpolation prediction error term, a spatial smoothness constraint term and an anisotropic characteristic term is established, a mapping relationship between parameters and the objective function is established by using Gaussian process regression, and the nugget effect value, the sill value and the search radius of the Kriging interpolation of the variogram are iteratively optimized by maximizing the expected improvement criterion; The Kriging weight coefficient is calculated based on the optimized variogram, and the estimated value of the electromagnetic field distortion of the interpolation point is obtained by solving the Kriging equations; The electromagnetic field distortion estimation value is decomposed at multiple scales using orthogonal wavelet basis functions to obtain approximate coefficients of the coarsest scale and detail coefficients of different scales. The approximate coefficients and the detail coefficients are reconstructed to generate an electromagnetic field distortion distribution map. The electromagnetic field distortion distribution map uses pseudo-color coding to represent the distortion intensity and superimposes contour lines to display the distortion gradient changes.

[0008] In an optional embodiment, Constructing a fault feature vector according to the multidimensional signal collected by the adaptive sampling array, inputting the fault feature vector into a pre-trained reinforcement learning model, outputting the performance degradation rate of each functional area of ​​the circuit board, and generating a fault risk assessment matrix according to the performance degradation rate includes: Constructing a state space based on the multidimensional signals collected by the adaptive sampling array, wherein the state space includes functional unit states, operating parameters and historical diagnosis results, and constructing an action space, wherein the action space includes operating condition identification and risk assessment actions; Based on the state space, a functional association graph is constructed, wherein a vertex set in the functional association graph represents a functional unit of a circuit board, and an edge set represents a signal coupling relationship between the functional units; based on the functional association graph, mutual influences between the functional units are modeled through a graph attention mechanism to obtain fault characteristics; The top-level policy network of the executive body and the judge body structure is used for working condition identification. The executive body network processes the working condition state vector through the residual connection layer and the batch normalization layer to obtain the working condition category probability distribution. The judge body network evaluates the state value function, constructs an experience replay buffer to store state transition samples, and constructs a reward function according to the working condition identification accuracy and risk assessment effect. Constructing a variational autoencoder model, wherein the encoder uses a bidirectional long short-term memory network to map the input sequence consisting of the fault characteristics and the operating condition category probability distribution into a latent variable posterior distribution, and the decoder uses a transposed convolutional network to reconstruct the performance degradation trajectory; A causal temporal convolutional network is introduced into the latent variable posterior distribution space, wherein the causal temporal convolutional network obtains the performance degradation evolution law through hole convolution, and performs multiple forward propagations using random inactivation to obtain the performance degradation prediction result; Constructing a graph converter model, modeling the circuit board as a heterogeneous graph network, wherein the node features of the heterogeneous graph network include the failure probability, performance index and topological features of the functional unit, inputting the performance degradation prediction result into the graph converter model, and learning the risk propagation model through a multi-head attention mechanism; A causal graph is constructed based on the risk propagation model, a variational reasoning method is used to perform structural learning on the causal graph, and the fault propagation intensity between the functional units is evaluated through intervention calculation to generate a fault risk assessment matrix.

[0009] In an optional embodiment, A causal graph is constructed based on the risk propagation model, a variational reasoning method is used to perform structural learning on the causal graph, and the fault propagation intensity between the functional units is evaluated through intervention calculation to generate a fault risk assessment matrix including: Constructing a neural causal graph, the neural causal graph includes directed edges between multiple functional unit nodes, extracting time series features of each functional unit node, using a variational adversarial neural network generator to map the time series features into conditional latent variables, and using a variational adversarial neural network discriminator to evaluate the difference between the conditional latent variables and the true distribution to obtain a time series feature representation; Based on the temporal feature representation, a graph morphology adaptive layer is constructed, wherein the graph morphology adaptive layer generates a dynamic convolution kernel according to the local structural features of the functional unit nodes, and adaptively adjusts the topological structure of the neural causal graph to obtain an optimized neural causal graph; Inputting the optimized neural causal graph into a causal graph neural network, wherein the causal embedding layer of the causal graph neural network maps the functional unit nodes to the causal representation space, and the causal reasoning layer extracts the causal dependency through gated graph convolution; The causal dependency relationship is input into a random causal field model, the random causal field model uses an energy function to perform joint distribution modeling on the states of the functional unit nodes, calculates the causal strength between the nodes, and uses a dual attention mechanism to process the causal strength to obtain an attention-enhanced causal feature; A risk propagation network is constructed based on the attention-enhanced causal features. The risk propagation network models the propagation of fault risks through graph diffusion convolution, adopts residual connections to maintain local risk features, outputs propagation features, and weightedly combines the propagation features with the causal strength to generate a fault risk assessment matrix, wherein the elements of the fault risk assessment matrix represent the degree of risk propagation between functional unit nodes.

[0010] In an optional embodiment, The circuit board is functionally reconstructed according to the fault risk assessment matrix, computing tasks in high-risk areas are migrated to low-risk areas, a dynamic fault-tolerant mechanism for the circuit board is established, and a task load distribution strategy is generated based on the dynamic fault-tolerant mechanism, including: Calculate the incoming risk value and the outgoing risk value of each functional unit according to the fault risk assessment matrix, wherein the incoming risk value represents the risk impact degree of other functional units on the target functional unit, and the outgoing risk value represents the risk propagation degree of the target functional unit to other functional units; The inbound risk value and the outbound risk value are weightedly merged to obtain a comprehensive risk of each functional unit, and a migration optimization model is established for the computing tasks in the circuit board according to the comprehensive risk; Generate a set of candidate migration solutions based on the migration optimization model, calculate the overall system risk value for each candidate solution in the set of candidate migration solutions, and select the candidate solution with the minimum overall system risk value as the optimal task allocation solution; According to the optimal task allocation scheme, a three-module redundant structure is constructed in each functional unit, and the three-module redundant structure realizes reliable output of data through parallel data processing and majority voting selection mechanism; Collecting real-time load data of each functional unit, calculating the load distribution state in combination with the processing capacity of the functional unit, and calculating the deployment score for the task to be deployed according to the load distribution state; The task priority is calculated by combining the task importance index with the comprehensive risk, and a task queue based on priority sorting is generated, wherein the task priority in the task queue is dynamically adjusted according to the load distribution state; An initial task allocation plan is generated according to the task queue and the deployment score, and the initial allocation plan is iteratively optimized in combination with the risk assessment matrix and the processing capacity of each functional unit to output a final task load allocation strategy including task deployment location, execution timing and load adjustment parameters.

[0011] In an optional embodiment, Deploy the task load distribution strategy to the field programmable gate array of the circuit board, autonomously repair the circuit board by adjusting the logical structure of the field programmable gate array, collect the operation data of the circuit board after the repair, compare the operation data with the fault feature vector before the repair, verify the repair effect and output a diagnostic report including: Establish a state machine execution model according to the received task load distribution strategy, and generate a state transition rule base including state transition conditions and trigger thresholds, wherein the state machine execution model includes an idle state, a loading start state, a loading state, a verification state, and a switching state; Reading the state transition condition in the state transition rule base, calculating the mapping relationship between the storage address of the configuration bit stream and the reconfigurable area of ​​the FPGA, and generating a configuration bit stream loading control signal according to the mapping relationship; Building a double buffer structure based on the load control signal, setting a buffer mutex and a buffer status flag, wherein the buffer status flag indicates a read / write status of a current buffer; Detecting the buffer state flag bit, when data is written into one buffer, setting a data output selection signal of another buffer according to the mutex lock; Writing the configuration bit stream into the writable buffer of the double buffer structure, and updating the buffer status flag after writing is completed, triggering the state machine to execute the state switching of the model; Collect the working status data, timing parameter data and resource occupancy data of the functional units in the FPGA, generate the operating status feature vector, perform correlation analysis on the operating status feature vector and the preset fault feature vector, calculate the functional unit status recovery rate, timing parameter recovery rate and resource utilization optimization rate, and generate the repair effect evaluation index; A multi-layer scoring model is established based on the repair effect evaluation indicators, and each evaluation indicator is weighted and calculated according to the weight set by the task priority identification bit to generate a comprehensive repair score, and output a diagnostic report containing fault location information and repair status information.

[0012] According to a second aspect of the embodiments of the present invention, Provided is a circuit board fault diagnosis system based on artificial intelligence, comprising: The first unit is used to construct a three-dimensional electromagnetic field simulation model of a circuit board, set a plurality of virtual sensor probes in the three-dimensional electromagnetic field simulation model, the virtual sensor probes correspond to the physical sensor positions of the circuit board one by one, collect measured data of the physical sensor and simulation data of the virtual sensor probes, establish an abnormal behavior pattern library of the circuit board by comparing the deviation value between the measured data and the simulation data, construct a back propagation neural network according to the abnormal behavior pattern library, calculate the electromagnetic field distortion degree of each functional area of ​​the circuit board based on the back propagation neural network, and generate an electromagnetic field distortion distribution map; The second unit is used to divide the fault-sensitive area of ​​the circuit board based on the electromagnetic field distortion distribution map, deploy an adaptive sampling array in the fault-sensitive area, the adaptive sampling array includes a temperature sensing unit, a voltage sensing unit and an electromagnetic sensing unit, construct a fault feature vector according to the multi-dimensional signal collected by the adaptive sampling array, input the fault feature vector into a pre-trained reinforcement learning model, output the performance degradation rate of each functional area of ​​the circuit board, and generate a fault risk assessment matrix according to the performance degradation rate; The third unit is used to reconstruct the functions of the circuit board according to the fault risk assessment matrix, migrate the computing tasks in the high-risk area to the low-risk area, establish a dynamic fault-tolerant mechanism for the circuit board, generate a task load distribution strategy based on the dynamic fault-tolerant mechanism, deploy the task load distribution strategy to the field programmable gate array of the circuit board, autonomously repair the circuit board by adjusting the logical structure of the field programmable gate array, collect the operating data of the repaired circuit board, compare the operating data with the fault feature vector before repair, verify the repair effect and output a diagnosis report.

[0013] According to a third aspect of the embodiments of the present invention, An electronic device is provided, comprising: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0014] According to a fourth aspect of the embodiments of the present invention, A computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the aforementioned method is implemented.

[0015] In this embodiment, by establishing a three-dimensional electromagnetic field simulation model combined with actual sensor data, the abnormal behavior pattern of the circuit board can be accurately identified; the back-propagation neural network is used to analyze the electromagnetic field distortion distribution to achieve accurate positioning of fault-sensitive areas; an adaptive sampling array and a reinforcement learning model are used to quantitatively evaluate fault risks, thereby improving the accuracy of fault diagnosis; dynamic task load distribution and FPGA reconstruction are used to achieve autonomous repair of the circuit board, thereby reducing maintenance costs; a complete closed-loop mechanism of fault diagnosis-risk assessment-autonomous repair is established, thereby improving the reliability and service life of the circuit board system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of a circuit board fault diagnosis method based on artificial intelligence according to an embodiment of the present invention; Figure 2 The figure is a schematic diagram of the structure of a circuit board fault diagnosis system based on artificial intelligence according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0019] Figure 1 FIG. 1 is a flow chart of a circuit board fault diagnosis method based on artificial intelligence according to an embodiment of the present invention. Figure 1 As shown, the method includes: S101. Construct a three-dimensional electromagnetic field simulation model of a circuit board, set a plurality of virtual sensor probes in the three-dimensional electromagnetic field simulation model, wherein the virtual sensor probes correspond one-to-one to the physical sensor positions of the circuit board, collect measured data of the physical sensor and simulation data of the virtual sensor probes, establish an abnormal behavior pattern library of the circuit board by comparing the deviation value between the measured data and the simulation data, construct a back propagation neural network according to the abnormal behavior pattern library, calculate the degree of electromagnetic field distortion of each functional area of ​​the circuit board based on the back propagation neural network, and generate an electromagnetic field distortion distribution map.

[0020] First, a three-dimensional electromagnetic field simulation model of the circuit board is constructed. Using computer-aided design software, an accurate three-dimensional geometric model is established based on the actual structure and material parameters of the circuit board. Then, using the finite element analysis method, the entire model is divided into a large number of tiny units, and boundary conditions and excitation sources are set. Several key locations are selected in the model and virtual sensor probes are placed, which correspond one-to-one to the sensor locations on the actual circuit board.

[0021] Next, the model is solved using electromagnetic field simulation software to obtain electromagnetic field parameters such as the electric field strength and magnetic field strength at each virtual probe position. At the same time, the actual circuit board is tested to collect measurement data from the physical sensors at the corresponding positions. The simulation data is compared with the measured data to calculate the deviation between the two. Based on the distribution characteristics of the deviation values, a library of abnormal behavior patterns of the circuit board is established, including various fault modes such as short circuit, open circuit, and component failure.

[0022] Based on the abnormal behavior pattern library, a back propagation neural network is constructed. The network consists of an input layer, a hidden layer, and an output layer. The input is the electromagnetic field parameter deviation value of each probe position, and the output is the electromagnetic field distortion degree of each functional area of ​​the circuit board. The network is trained and optimized through a large number of training samples to give it good generalization ability. By using the trained neural network and inputting new test data, the electromagnetic field distortion degree of each area of ​​the circuit board can be quickly calculated, and an intuitive electromagnetic field distortion distribution map can be generated.

[0023] In an optional embodiment, By comparing the deviation values ​​of the measured data and the simulated data, an abnormal behavior pattern library of the circuit board is established, a back propagation neural network is constructed according to the abnormal behavior pattern library, and the electromagnetic field distortion degree of each functional area of ​​the circuit board is calculated based on the back propagation neural network to generate an electromagnetic field distortion distribution map, including: The time domain statistical features are generated by the adaptive wavelet decomposition module, the frequency domain spectrum features are generated by the fast Fourier transform module, and the attention mechanism is used to dynamically assign weights to the time domain statistical features and the frequency domain spectrum features to form a fusion feature vector; The recursive least squares algorithm is used to update the feature covariance matrix, and the Mahalanobis distance between the measured feature vector and the simulated feature vector is calculated based on the updated feature covariance matrix to obtain the abnormality sequence; A dual-criteria density clustering method based on local density and distance distribution is used to determine the cluster center of the abnormal degree sequence, and the clustering parameters are adaptively adjusted using the fractal dimension to form an abnormal pattern sequence. The abnormal mode sequence is decomposed through empirical mode decomposition to obtain the intrinsic mode function, and the evolution characteristics of the intrinsic mode function are extracted using a sliding time window. The time series association rules of the evolution characteristics are mined based on the improved Apriori algorithm to establish an abnormal behavior pattern library. A deep hybrid neural network is trained based on the abnormal behavior pattern library. The spatial domain features are extracted through the residual connection convolution layer. The temporal domain features are extracted using the long short-term memory unit and the gated recurrent unit. The topological domain features are extracted using the graph convolution layer. The extracted features are combined and input into the fully connected layer to output the electromagnetic field distortion prediction value. The spatial anisotropy constraints of circuit board wiring density and impedance distribution are introduced into the variogram. The Bayesian optimization algorithm is used to adjust the Kriging interpolation parameters. The electromagnetic field distortion prediction values ​​are spatially interpolated. The multi-resolution distortion distribution representation is constructed through wavelet transform to generate the electromagnetic field distortion distribution map.

[0024] Exemplarily, firstly, the measured data and simulation data of the circuit board are analyzed in the time domain by the adaptive wavelet decomposition module to extract statistical features such as mean, variance, skewness, kurtosis, etc. At the same time, the fast Fourier transform module is used to analyze the data in the frequency domain to obtain spectrum features such as main frequency, bandwidth, spectrum energy, etc. Then, the attention mechanism is used to dynamically assign weights to the time domain statistical features and frequency domain spectrum features to form a fusion feature vector that can comprehensively characterize the electromagnetic characteristics of the circuit board.

[0025] Next, the recursive least squares algorithm is used to update the feature covariance matrix in real time to adapt to the dynamic changes in the working state of the circuit board. Based on the updated feature covariance matrix, the Mahalanobis distance between the measured feature vector and the simulated feature vector is calculated to obtain the abnormality sequence reflecting the abnormality of the circuit board. For example, the abnormality sequence of a circuit board in normal working state is [0.2, 0.3, 0.1, 0.4, 0.2], and when an abnormality occurs, the sequence becomes [1.5, 2.1, 1.8, 2.5, 2.3].

[0026] Then, the abnormal degree sequence is clustered using a dual-criteria density clustering method based on local density and distance distribution. This method first calculates the local density and distance distribution of each data point, and then determines the cluster center by comprehensively considering these two indicators. In the clustering process, the fractal dimension is used to adaptively adjust clustering parameters such as the cutoff distance to adapt to abnormal patterns of different scales. Through cluster analysis, similar abnormal patterns are classified into one category to form an abnormal pattern sequence.

[0027] Perform empirical mode decomposition on the obtained abnormal mode sequence to obtain a series of intrinsic mode functions. Use the sliding time window method to extract the evolution characteristics of the intrinsic mode function, such as amplitude change rate, frequency drift, etc. Based on the improved Apriori algorithm, the temporal association rules of these evolution characteristics are mined to establish an abnormal behavior pattern library. For example, it may be found that there is a strong correlation between "amplitude mutation" and "frequency drift", indicating that these two phenomena often occur at the same time.

[0028] Based on the established abnormal behavior pattern library, a deep hybrid neural network is trained to predict electromagnetic field distortion. The network contains multiple functional modules: extract spatial domain features through residual connection convolution layer to capture the local characteristics of electromagnetic field distribution; use long short-term memory units and gated recurrent units to extract temporal domain features and learn the change law of electromagnetic field over time; use graph convolution layer to extract topological domain features and consider the connection relationship between various regions of the circuit board. The extracted features are combined and input into the fully connected layer, and finally the electromagnetic field distortion prediction value is output.

[0029] Finally, the spatial anisotropy constraints of the circuit board wiring density and impedance distribution are introduced into the variogram to reflect the changing characteristics of the electromagnetic field distortion in different directions. The Bayesian optimization algorithm is used to adaptively adjust the parameters of the Kriging interpolation, such as the range and the sill value, to perform spatial interpolation on the discrete electromagnetic field distortion prediction values ​​to obtain a continuous distribution. Then, a multi-resolution distortion distribution representation is constructed through wavelet transform, which not only retains the global trend but also highlights the local details, and finally generates an intuitive electromagnetic field distortion distribution map.

[0030] In this embodiment, by constructing an abnormal behavior pattern library, the electromagnetic field distortion of the circuit board is effectively identified and classified. The combination of adaptive wavelet decomposition and fast Fourier transform provides comprehensive features in the time domain and frequency domain, making feature extraction more comprehensive. Using the recursive least squares algorithm and Mahalanobis distance, the feature covariance matrix can be updated in real time to improve the accuracy of abnormality assessment. Through dual-criteria density clustering and fractal dimension adjustment, the identification of abnormal patterns is further refined. At the same time, the application of deep hybrid neural networks, combined with a variety of feature extraction methods, enhances the model's adaptability to complex data. The introduction of spatial anisotropy constraints and Bayesian optimization optimizes the accuracy of electromagnetic field distortion prediction. The resulting electromagnetic field distortion distribution map provides a visual and quantitative basis for circuit board design and fault diagnosis, helping to improve product reliability and performance.

[0031] In an optional embodiment, The spatial anisotropy constraints of circuit board wiring density and impedance distribution are introduced into the variogram, and the Kriging interpolation parameters are adjusted by Bayesian optimization algorithm. The electromagnetic field distortion prediction value is spatially interpolated, and a multi-resolution distortion distribution representation is constructed by wavelet transform. The electromagnetic field distortion distribution map is generated, including: Constructing a density weight matrix based on the wiring density distribution of the circuit board, and constructing an impedance weight matrix based on the impedance distribution of the circuit board, and combining the density weight matrix and the impedance weight matrix through a rotation matrix to form an anisotropic matrix; Using the anisotropy matrix to construct an exponential variogram, the variogram includes a nugget effect value, a sill value, and a spatial vector product term of the anisotropy matrix; An optimization objective function including an interpolation prediction error term, a spatial smoothness constraint term and an anisotropic characteristic term is established, a mapping relationship between parameters and the objective function is established by using Gaussian process regression, and the nugget effect value, the sill value and the search radius of the Kriging interpolation of the variogram are iteratively optimized by maximizing the expected improvement criterion; The Kriging weight coefficient is calculated based on the optimized variogram, and the estimated value of the electromagnetic field distortion of the interpolation point is obtained by solving the Kriging equations; The electromagnetic field distortion estimation value is decomposed at multiple scales using orthogonal wavelet basis functions to obtain approximate coefficients of the coarsest scale and detail coefficients of different scales. The approximate coefficients and the detail coefficients are reconstructed to generate an electromagnetic field distortion distribution map. The electromagnetic field distortion distribution map uses pseudo-color coding to represent the distortion intensity and superimposes contour lines to display the distortion gradient changes.

[0032] First, a density weight matrix is ​​constructed based on the wiring density distribution of the circuit board. Specifically, the circuit board can be divided into several grid cells, the wiring density in each grid is counted, and it is normalized to between 0 and 1 to form a two-dimensional matrix. Similarly, an impedance weight matrix is ​​constructed based on the impedance distribution of the circuit board, and the impedance value of each grid cell is normalized to form another two-dimensional matrix.

[0033] Next, the density weight matrix and the impedance weight matrix are combined through the rotation matrix to form an anisotropic matrix. The principal component analysis method can be used to determine the rotation angle so that the combined matrix can reflect the main directional characteristics of the circuit board wiring and impedance distribution. For example, assuming that the density weight matrix is ​​D, the impedance weight matrix is ​​Z, and the rotation matrix is ​​R, the anisotropic matrix A can be expressed as: A = R * (αD + βZ) * R^T, where α and β are weight coefficients.

[0034] Then, the exponential variogram is constructed using the anisotropy matrix. The variogram contains the nugget effect value C0, the sill value C, and the spatial vector product term of the anisotropy matrix. It can be expressed as: γ(h) = C0 + C * [1 - exp(-h^T * A * h)], where h is the spatial distance vector. The nugget effect value C0 represents the random variation at the microscopic scale, and the sill value C represents the limit value of spatial correlation.

[0035] Next, an optimization objective function is established, including interpolation prediction error terms, spatial smoothness constraint terms, and anisotropic characteristic terms. Gaussian process regression is used to establish the mapping relationship between parameters and objective functions, and the nugget effect value of the variogram, the sill value, and the search radius of the Kriging interpolation are iteratively optimized by maximizing the expected improvement criterion. For example, the initial values ​​C0=0.1, C=1, and the search radius r=10 can be set, and then the optimization is performed in the range of [0, 0.5], [0.5, 2], [5, 20] until the objective function converges.

[0036] The Kriging weight coefficients are calculated based on the optimized variogram, and the estimated value of the electromagnetic field distortion of the interpolation point is obtained by solving the Kriging equations. For each interpolation point, known sampling points in its neighborhood are selected, the Kriging equations are constructed and solved to obtain the distortion estimate of the point.

[0037] Finally, the orthogonal wavelet basis function is used to perform multi-scale decomposition on the electromagnetic field distortion estimate. Haar wavelet or Daubechies wavelet can be used to decompose the distortion field into the coarsest scale approximate coefficients and detail coefficients of different scales. For example, for a 64×64 distortion field, a three-layer decomposition can be performed to obtain 8×8 approximate coefficients and three groups of 8×8, 16×16, and 32×32 detail coefficients. These coefficients are reconstructed to generate the electromagnetic field distortion distribution map.

[0038] In the visualization, pseudo color coding is used to indicate the distortion intensity, such as blue for low distortion areas and red for high distortion areas. At the same time, contour lines are superimposed to show the distortion gradient change, and 5-10 contour lines can be selected to reflect the main gradient change characteristics. This multi-scale and multi-level representation method can reflect both the overall distribution trend of the distortion field and the local fine structure, which is conducive to designers to quickly identify key areas and perform targeted optimization.

[0039] In this embodiment, by introducing the spatial anisotropy constraints of the circuit board wiring density and impedance distribution, the constructed anisotropic matrix enhances the adaptability of the interpolation model to complex circuit board structures. Through the design of the exponential variation function, the spatial variation characteristics of the electromagnetic field can be effectively captured, and the interpolation accuracy is optimized by combining the interpolation prediction error and the spatial smoothness constraint. The Gaussian process regression is used for parameter optimization, so that the effect of Kriging interpolation is significantly improved, and the accuracy of the electromagnetic field distortion estimation of the interpolation point is improved. Finally, the multi-scale decomposition realized by the orthogonal wavelet basis function can clearly present the distortion information at different scales, and the generated electromagnetic field distortion distribution map intuitively shows the distortion intensity and gradient changes in the form of pseudo-color coding and contour line superposition, which provides important decision support for the design and troubleshooting of the circuit board.

[0040] S102. Divide the fault-sensitive areas of the circuit board based on the electromagnetic field distortion distribution map, deploy an adaptive sampling array in the fault-sensitive areas, the adaptive sampling array includes a temperature sensor unit, a voltage sensor unit and an electromagnetic sensor unit, construct a fault feature vector based on the multi-dimensional signal collected by the adaptive sampling array, input the fault feature vector into a pre-trained reinforcement learning model, output the performance degradation rate of each functional area of ​​the circuit board, and generate a fault risk assessment matrix based on the performance degradation rate.

[0041] According to the electromagnetic field distortion distribution map, the fault-sensitive areas of the circuit board are divided. The areas with higher distortion are marked as high-sensitive areas, the areas with medium distortion are marked as medium-sensitive areas, and the areas with lower distortion are marked as low-sensitive areas. Adaptive sampling arrays are deployed in the high-sensitive and medium-sensitive areas, including temperature sensing units, voltage sensing units, and electromagnetic sensing units. These sensing units can automatically adjust the sampling frequency and accuracy according to environmental changes to obtain more accurate multi-dimensional signals.

[0042] The temperature, voltage and electromagnetic signals collected by the adaptive sampling array are used to construct a fault feature vector. The vector contains multiple characteristic parameters, such as temperature change rate, voltage ripple coefficient, electromagnetic interference intensity, etc. The constructed fault feature vector is input into a pre-trained reinforcement learning model. The model uses a deep Q network algorithm to continuously optimize the decision-making strategy through interaction with the environment. The output of the model is the performance degradation rate of each functional area of ​​the circuit board, indicating the possibility of failure in each area. A fault risk assessment matrix is ​​generated based on the performance degradation rate, which clearly shows the fault risk level of each area of ​​the circuit board.

[0043] In an optional embodiment, Constructing a fault feature vector according to the multidimensional signal collected by the adaptive sampling array, inputting the fault feature vector into a pre-trained reinforcement learning model, outputting the performance degradation rate of each functional area of ​​the circuit board, and generating a fault risk assessment matrix according to the performance degradation rate includes: Constructing a state space based on the multidimensional signals collected by the adaptive sampling array, wherein the state space includes functional unit states, operating condition parameters and historical diagnosis results, and constructing an action space, wherein the action space includes operating condition identification and risk assessment actions; Based on the state space, a functional association graph is constructed, wherein a vertex set in the functional association graph represents a functional unit of a circuit board, and an edge set represents a signal coupling relationship between the functional units; based on the functional association graph, mutual influences between the functional units are modeled through a graph attention mechanism to obtain fault characteristics; The top-level policy network of the executive body and the judge body structure is used for working condition identification. The executive body network processes the working condition state vector through the residual connection layer and the batch normalization layer to obtain the working condition category probability distribution. The judge body network evaluates the state value function, constructs an experience replay buffer to store state transition samples, and constructs a reward function according to the working condition identification accuracy and risk assessment effect. Constructing a variational autoencoder model, wherein the encoder uses a bidirectional long short-term memory network to map the input sequence consisting of the fault characteristics and the operating condition category probability distribution into a latent variable posterior distribution, and the decoder uses a transposed convolutional network to reconstruct the performance degradation trajectory; A causal temporal convolutional network is introduced into the latent variable posterior distribution space, wherein the causal temporal convolutional network obtains the performance degradation evolution law through hole convolution, and performs multiple forward propagations using random inactivation to obtain the performance degradation prediction result; Constructing a graph converter model, modeling the circuit board as a heterogeneous graph network, wherein the node features of the heterogeneous graph network include the failure probability, performance index and topological features of the functional unit, inputting the performance degradation prediction result into the graph converter model, and learning the risk propagation model through a multi-head attention mechanism; A causal graph is constructed based on the risk propagation model, a variational reasoning method is used to perform structural learning on the causal graph, and the fault propagation intensity between the functional units is evaluated through intervention calculation to generate a fault risk assessment matrix.

[0044] Exemplarily, based on the multidimensional signal collected by the adaptive sampling array, a state space is first constructed. The state space includes three dimensions: functional unit state, operating parameters, and historical diagnostic results. The functional unit state describes the operating state of each functional module of the circuit board, such as voltage, current, temperature, etc.; the operating parameters reflect external environmental conditions, such as ambient temperature, humidity, vibration, etc.; the historical diagnostic results record past fault diagnosis situations. At the same time, an action space is constructed, including two types of actions: operating condition identification and risk assessment. The operating condition identification action is used to judge the current working environment, and the risk assessment action is used to evaluate the performance degradation of each functional unit.

[0045] Based on the constructed state space, a functional association graph is further constructed. In this graph, the vertex set represents the various functional units of the circuit board, such as power modules, signal processing modules, storage modules, etc.; the edge set represents the signal coupling relationship between functional units, such as data transmission, energy transfer, etc. The functional association graph is modeled through the graph attention mechanism, and the correlation weights between different functional units are calculated to obtain the fault characteristics reflecting the status of the entire circuit board.

[0046] Next, the top-level policy network of the executive body and judge body structure is used to identify the working condition. The executive body network consists of multiple residual connection layers and batch normalization layers, which are used to process the working condition state vector and output the probability distribution of the working condition category. For example, possible working condition categories include normal operation, high temperature environment, strong vibration environment, etc. The judge body network evaluates the value function of the current state. At the same time, an experience replay buffer is constructed to store state transition samples. The reward function is designed according to the accuracy of working condition identification and the effect of risk assessment to guide the training process of reinforcement learning.

[0047] Then, a variational autoencoder model is constructed. The encoder uses a bidirectional long short-term memory network to map the input sequence consisting of fault features and operating condition category probability distribution into the posterior distribution of latent variables. The decoder uses a transposed convolutional network to reconstruct the performance degradation trajectory. This can effectively extract time series features and predict future performance degradation trends.

[0048] A causal temporal convolutional network is introduced into the posterior distribution space of latent variables. The network expands the receptive field through the hole convolution layer, effectively captures long-term dependencies, and thus obtains the evolution law of performance degradation. Multiple forward propagations are performed using random inactivation to obtain performance degradation prediction results with uncertainty. This method can evaluate the reliability of the prediction and provide more information for subsequent decision-making.

[0049] Next, we build a graph transformer model and model the circuit board as a heterogeneous graph network. In this network, node features include the failure probability, performance indicators, and topological features of functional units. The performance degradation prediction results obtained in the previous step are input into the graph transformer model, and the risk propagation pattern between different functional units is learned through the multi-head attention mechanism. In this way, the mutual influence between the various parts of the circuit board can be taken into account, and a more accurate overall risk assessment can be obtained.

[0050] Finally, a causal graph is constructed based on the learned risk propagation model. The variational inference method is used to learn the structure of the causal graph and determine the causal relationship between each functional unit. The fault propagation intensity between functional units is evaluated through intervention calculation, that is, the degree to which a unit affects other units after a failure. Finally, a fault risk assessment matrix is ​​generated, and each element in the matrix represents the fault propagation intensity of the corresponding functional unit pair.

[0051] In this embodiment, the fault feature vector constructed by the multi-dimensional signal collected by the adaptive sampling array provides rich input for the reinforcement learning model, and then outputs the performance degradation rate of each functional area. The design of the state space and action space enables the system to dynamically identify the working conditions and evaluate the risks. The constructed functional association diagram effectively captures the coupling relationship between the functional units and improves the ability to extract fault features. Through the combination of the execution body and the judgment body network, the accuracy of working condition identification and risk assessment is improved. At the same time, the constructed variational autoencoder model further refines the reconstruction of the performance degradation trajectory. The causal temporal convolutional network reveals the evolution law of performance degradation and enhances the prediction ability. The application of the graph transformer model makes full use of the characteristics of each node in the heterogeneous graph network, and with the help of the multi-head attention mechanism, the risk propagation model is deeply learned. Finally, the generated fault risk assessment matrix provides a scientific basis for circuit board fault warning and maintenance decision-making, significantly improving the reliability and intelligence level of the system.

[0052] In an optional embodiment, A causal graph is constructed based on the risk propagation model, a variational reasoning method is used to perform structural learning on the causal graph, and the fault propagation intensity between the functional units is evaluated through intervention calculation to generate a fault risk assessment matrix including: Constructing a neural causal graph, the neural causal graph includes directed edges between multiple functional unit nodes, extracting time series features of each functional unit node, using a variational adversarial neural network generator to map the time series features into conditional latent variables, and using a variational adversarial neural network discriminator to evaluate the difference between the conditional latent variables and the true distribution to obtain a time series feature representation; Based on the temporal feature representation, a graph morphology adaptive layer is constructed, wherein the graph morphology adaptive layer generates a dynamic convolution kernel according to the local structural features of the functional unit nodes, and adaptively adjusts the topological structure of the neural causal graph to obtain an optimized neural causal graph; Inputting the optimized neural causal graph into a causal graph neural network, wherein the causal embedding layer of the causal graph neural network maps the functional unit nodes to the causal representation space, and the causal reasoning layer extracts the causal dependency through gated graph convolution; The causal dependency relationship is input into a random causal field model, the random causal field model uses an energy function to perform joint distribution modeling on the states of the functional unit nodes, calculates the causal strength between the nodes, and uses a dual attention mechanism to process the causal strength to obtain an attention-enhanced causal feature; A risk propagation network is constructed based on the attention-enhanced causal features. The risk propagation network models the propagation of fault risks through graph diffusion convolution, adopts residual connections to maintain local risk features, outputs propagation features, and weightedly combines the propagation features with the causal strength to generate a fault risk assessment matrix, wherein the elements of the fault risk assessment matrix represent the degree of risk propagation between functional unit nodes.

[0053] First, a neural causal graph is constructed, which contains multiple nodes representing functional units and directed edges between nodes. For each functional unit node, the time series features in its historical operation data are extracted, such as fault frequency, fault duration, etc. Then a variational adversarial neural network is used, in which the generator maps the extracted time series features into conditional latent variables, and the discriminator evaluates the difference between the conditional latent variables and the true distribution, and finally obtains the time series feature representation of each functional unit node. For example, for a certain engine functional unit, the number of monthly failures and average repair time in the past year are extracted, and after being processed by the variational adversarial neural network, a 64-dimensional vector is obtained as its time series feature representation.

[0054] Next, a graph morphology adaptive layer is constructed based on the temporal feature representation. This layer dynamically generates convolution kernels according to the local structural features of each functional unit node (such as the number of adjacent nodes, edge weights, etc.), which is used to adaptively adjust the topological structure of the neural causal graph. Specifically, the graph attention network can be used to calculate the attention coefficient between nodes, and the edge weights can be dynamically adjusted according to the attention coefficients to obtain an optimized neural causal graph. For example, the attention coefficients of a functional unit node and its three adjacent nodes are 0.4, 0.3, and 0.3, respectively, and the weights of the corresponding edges are adjusted accordingly.

[0055] The optimized neural causal graph is input into the causal graph neural network for processing. The causal embedding layer of the network first maps the functional unit nodes to the causal representation space, that is, each node is represented as a low-dimensional vector. Then the causal reasoning layer extracts the causal dependency between nodes through the gated graph convolution operation. The gated graph convolution can be set up with multiple layers, and each layer aggregates the information of adjacent nodes and updates the representation of the current node. The final output is the features that represent the causal dependency between nodes.

[0056] The above causal dependency features are input into the random causal field model. The model uses an energy function to model the joint distribution of the states of the functional unit nodes and calculates the causal strength between the nodes. Specifically, a potential function can be defined to characterize the energy of a single node and a node pair, and then the joint probability distribution of the node state is obtained by normalization, and then the causal strength between the nodes is calculated. Then, the dual attention mechanism is used to process the causal strength, that is, the attention of the spatial dimension and the channel dimension is considered at the same time to obtain the attention-enhanced causal features. For example, for two functional unit nodes, the calculated initial causal strength is 0.7, which may be adjusted to 0.8 after attention enhancement.

[0057] Finally, a risk propagation network is constructed based on the attention-enhanced causal features. The network models the propagation of fault risks between functional units through graph diffusion convolution, and uses residual connections to maintain local risk features. In specific implementation, multiple layers of graph diffusion convolution can be stacked, and each layer propagates and updates risk information. After the network outputs the propagation features, it is weightedly combined with the causal strength obtained previously to finally generate a fault risk assessment matrix. Each element in the matrix represents the degree of risk propagation between the corresponding two functional unit nodes. For example, in the generated 10x10 risk assessment matrix, the value of element (2, 5) is 0.6, indicating that the degree of risk propagation from functional unit 2 to functional unit 5 is 0.6.

[0058] In this embodiment, the constructed neural causal graph provides strong timing support for the fault propagation model by extracting the timing characteristics of the functional units and using the conditional hidden variables generated by the variational adversarial neural network. The graph morphology adaptation layer optimizes the topological structure of the neural causal graph through dynamic convolution kernels, thereby improving the sensitivity to local features. The causal embedding layer and reasoning layer of the causal graph neural network effectively extract causal dependencies, laying the foundation for subsequent causal strength calculations. The random causal field model jointly models the state of the functional unit through an energy function, calculates the causal strength between nodes, and then enhances the causal characteristics through a dual attention mechanism. Finally, the risk propagation network uses graph diffusion convolution to model the fault risk, and the risk assessment matrix generated by combining the propagation characteristics and causal strength can intuitively reflect the degree of risk propagation between functional units. The application of this series of technologies not only improves the accuracy of fault warning, but also provides comprehensive data support and decision-making basis for the reliability management of circuit boards.

[0059] S103. Reconstruct the functions of the circuit board according to the fault risk assessment matrix, migrate the computing tasks in the high-risk area to the low-risk area, establish a dynamic fault-tolerant mechanism for the circuit board, generate a task load distribution strategy based on the dynamic fault-tolerant mechanism, deploy the task load distribution strategy to the field programmable gate array of the circuit board, autonomously repair the circuit board by adjusting the logical structure of the field programmable gate array, collect the operating data of the repaired circuit board, compare the operating data with the fault feature vector before repair, verify the repair effect and output a diagnostic report.

[0060] Based on the fault risk assessment matrix, the circuit board is functionally reconfigured. The computing tasks in the high-risk area are migrated to the low-risk area to reduce the overall probability of system failure. A dynamic fault-tolerant mechanism is established to monitor the performance status of each area in real time, and automatically start the backup resources when the performance of a certain area decreases. The task load distribution strategy is generated according to the dynamic fault-tolerant mechanism to reasonably allocate computing resources and avoid single point failures.

[0061] The generated task load distribution strategy is deployed to the field programmable gate array (FPGA) of the circuit board. The circuit board can be repaired autonomously by reconfiguring the logic structure of the FPGA. Specifically, the configuration of the internal lookup table and interconnection resources of the FPGA is modified, and the hardware description of each functional module is redefined to bypass or replace the fault area and restore the system function.

[0062] After completing the autonomous repair, collect the operating data of the repaired circuit board, including parameters such as throughput, power consumption, and temperature of each functional module. Compare and analyze these operating data with the fault feature vector before the repair to evaluate the repair effect. If the key performance indicators are significantly improved, the repair is considered successful; otherwise, the repair strategy needs to be further optimized. Finally, generate a detailed diagnostic report based on the analysis results, including information such as fault type, location, severity, and repair measures, to provide a reference for subsequent maintenance.

[0063] In an optional embodiment, The circuit board is functionally reconstructed according to the fault risk assessment matrix, computing tasks in high-risk areas are migrated to low-risk areas, a dynamic fault-tolerant mechanism for the circuit board is established, and a task load distribution strategy is generated based on the dynamic fault-tolerant mechanism, including: Calculate the incoming risk value and the outgoing risk value of each functional unit according to the fault risk assessment matrix, wherein the incoming risk value represents the risk impact degree of other functional units on the target functional unit, and the outgoing risk value represents the risk propagation degree of the target functional unit to other functional units; The inbound risk value and the outbound risk value are weightedly merged to obtain a comprehensive risk of each functional unit, and a migration optimization model is established for the computing tasks in the circuit board according to the comprehensive risk; Generate a set of candidate migration solutions based on the migration optimization model, calculate the overall system risk value for each candidate solution in the set of candidate migration solutions, and select the candidate solution with the minimum overall system risk value as the optimal task allocation solution; According to the optimal task allocation scheme, a three-module redundant structure is constructed in each functional unit, and the three-module redundant structure realizes reliable output of data through parallel data processing and majority voting selection mechanism; Collecting real-time load data of each functional unit, calculating the load distribution state in combination with the processing capacity of the functional unit, and calculating the deployment score for the task to be deployed according to the load distribution state; The task priority is calculated by combining the task importance index with the comprehensive risk, and a task queue based on priority sorting is generated, wherein the task priority in the task queue is dynamically adjusted according to the load distribution state; An initial task allocation plan is generated according to the task queue and the deployment score, and the initial allocation plan is iteratively optimized in combination with the risk assessment matrix and the processing capacity of each functional unit to output a final task load allocation strategy including task deployment location, execution timing and load adjustment parameters.

[0064] First, the incoming risk value and outgoing risk value of each functional unit are calculated according to the fault risk assessment matrix. The incoming risk value represents the degree of risk influence of other functional units on the target functional unit, and the outgoing risk value represents the degree of risk propagation of the target functional unit to other functional units. Specifically, the row elements related to the target functional unit in the fault risk assessment matrix can be summed to obtain the incoming risk value, and the column elements can be summed to obtain the outgoing risk value. For example, for a functional unit A, its incoming risk value is 2.3 and its outgoing risk value is 1.8.

[0065] Then, the inbound risk value and the outbound risk value are weighted and fused to obtain the comprehensive risk of each functional unit. The inbound risk value and the outbound risk value can be weighted with weights of 0.6 and 0.4 respectively to obtain the comprehensive risk. Taking functional unit A as an example, its comprehensive risk is 2.3×0.6+1.8×0.4=2.1. According to the calculated comprehensive risk of each functional unit, a migration optimization model is established for the computing tasks in the circuit board. The model aims to minimize the overall risk of the system and takes the processing capacity of the functional unit as a constraint.

[0066] Next, a set of candidate migration schemes is generated based on the migration optimization model. Multiple candidate schemes can be generated using intelligent optimization algorithms such as genetic algorithms, each of which contains the distribution of tasks among functional units. The overall risk value of the system is calculated for each candidate scheme in the candidate migration scheme set. The risk value can be obtained by summing the product of the comprehensive risk of each functional unit and the amount of tasks it undertakes. The candidate scheme with the smallest overall system risk value is selected as the optimal task allocation scheme.

[0067] According to the optimal task allocation scheme, a three-module redundant structure is constructed in each functional unit. This structure contains three processing modules with the same functions, and reliable data output is achieved through parallel data processing and majority voting selection mechanism. In specific implementation, the input data is sent to three processing modules for calculation at the same time, and the output results of the three modules are compared, and the results consistent with at least two modules are selected as the final output. This mechanism can effectively prevent system errors caused by single point failures.

[0068] Collect the real-time load data of each functional unit and calculate the load distribution status in combination with the processing capacity of the functional unit. Load data can be obtained by real-time monitoring of indicators such as CPU usage and memory usage of the functional unit. Define the ratio of real-time load to processing capacity as the load rate, and then obtain the load distribution status of the entire system. For example, if the real-time CPU usage of a functional unit is 60%, the memory usage is 70%, and its processing capacity upper limit is 80%, then the load rate of the unit is (60%+70%) / (2×80%)=81.25%.

[0069] Calculate the deployment score for the task to be deployed based on the load distribution status. The deployment score can be measured by the matching degree between the task resource requirements and the remaining resources of the functional unit. The higher the matching degree, the higher the score. For example, a task to be deployed requires 20% CPU resources and 30% memory resources. For the above functional unit, the remaining CPU resources are 20% and the remaining memory resources are 10%. The deployment score of the task in this unit can be calculated as (20% / 20%+10% / 30%) / 2=75%.

[0070] The task priority is calculated by combining the task importance index with the comprehensive risk, and a task queue based on priority is generated. The task importance can be divided into different levels according to business needs, and the task priority is obtained by weighting with the comprehensive risk. The task priority in the task queue is dynamically adjusted according to the load distribution status. When the load of a functional unit is too high, the high-priority tasks on it are migrated to the unit with lower load.

[0071] Finally, the initial task allocation plan is generated based on the task queue and deployment score, and the initial allocation plan is iteratively optimized in combination with the risk assessment matrix and the processing capacity of each functional unit. During the optimization process, by adjusting parameters such as task deployment location and execution timing, load balancing is achieved while minimizing the overall risk of the system. The final output includes the final task load allocation strategy containing task deployment location, execution timing, and load adjustment parameters. This strategy can be dynamically adjusted according to the real-time load status to ensure the reliability and performance of the system.

[0072] In this embodiment, the inbound and outbound risk values ​​calculated by the fault risk assessment matrix provide a quantitative basis for the comprehensive risk of each functional unit, which promotes the effective migration of computing tasks. In the migration optimization model, the task allocation scheme with the lowest overall system risk value is selected to ensure that the system maintains overall performance stability while reducing the task burden in high-risk areas. The construction of the three-module redundant structure further enhances the reliability of data output through parallel processing and majority voting mechanisms. The collection and analysis of real-time load data enables the load distribution state to dynamically reflect the actual operation of the system, providing a scientific basis for task priority sorting. The task load allocation strategy finally generated not only realizes the intelligent scheduling and optimization of tasks, but also can be adjusted in real time according to risk assessment and the processing capacity of functional units, thereby improving the adaptability and efficiency of the system. This scheme provides strong support for fault management and resource optimization configuration of circuit boards, and promotes intelligent development.

[0073] In an optional embodiment, Deploy the task load distribution strategy to the field programmable gate array of the circuit board, autonomously repair the circuit board by adjusting the logical structure of the field programmable gate array, collect the operation data of the circuit board after the repair, compare the operation data with the fault feature vector before the repair, verify the repair effect and output a diagnostic report including: Establish a state machine execution model according to the received task load distribution strategy, and generate a state transition rule base including state transition conditions and trigger thresholds, wherein the state machine execution model includes an idle state, a loading start state, a loading state, a verification state, and a switching state; Reading the state transition condition in the state transition rule base, calculating the mapping relationship between the storage address of the configuration bit stream and the reconfigurable area of ​​the FPGA, and generating a configuration bit stream loading control signal according to the mapping relationship; Building a double buffer structure based on the load control signal, setting a buffer mutex and a buffer status flag, wherein the buffer status flag indicates a read / write status of a current buffer; Detecting the buffer state flag bit, when data is written into one buffer, setting a data output selection signal of another buffer according to the mutex lock; Writing the configuration bit stream into the writable buffer of the double buffer structure, and updating the buffer status flag after writing is completed, triggering the state machine to execute the state switching of the model; Collect the working status data, timing parameter data and resource occupancy data of the functional units in the FPGA, generate the operating status feature vector, perform correlation analysis on the operating status feature vector and the preset fault feature vector, calculate the functional unit status recovery rate, timing parameter recovery rate and resource utilization optimization rate, and generate the repair effect evaluation index; A multi-layer scoring model is established based on the repair effect evaluation indicators, and each evaluation indicator is weighted and calculated according to the weight set by the task priority identification bit to generate a comprehensive repair score, and output a diagnostic report containing fault location information and repair status information.

[0074] Exemplarily, first, a state machine execution model is established according to the received task load distribution strategy. The model includes five states: idle, load start, load, verify, and switch. At the same time, a state transition rule base is generated, which includes the transition conditions and trigger thresholds between each state. For example, the condition for switching from the idle state to the load start state may be receiving a new task request, and the trigger threshold may be set to a task priority greater than 8.

[0075] Next, read the state transition conditions in the state transition rule base and calculate the mapping relationship between the storage address of the configuration bitstream and the FPGA reconfigurable area. Assuming that the FPGA has four reconfigurable areas R1-R4, and the configuration bitstream is stored at addresses 0x1000-0x4000, the following mapping can be established: R1 corresponds to 0x1000-0x1FFF, R2 corresponds to 0x2000-0x2FFF, and so on. Generate the loading control signal of the configuration bitstream based on this mapping relationship.

[0076] Then, a double buffer structure is constructed based on the load control signal. Two 4KB buffers A and B are set, as well as the mutex and buffer status flags. Flag = 0 means A is writable and B is readable, and flag = 1 means B is writable and A is readable.

[0077] Then the buffer status flag is checked. When flag=0, data is written to buffer A, and the data output selection signal of buffer B is set according to mutex, so that the data in B can be output. And vice versa.

[0078] Write the configuration bitstream into the currently writable buffer, and update the flag after writing. For example, if the current flag = 0, set the flag to 1 after writing data to A. This will trigger the state machine to switch from the loading start state to the loading state.

[0079] Then, the working status, timing parameters and resource occupancy data of each functional unit in the FPGA are collected to generate the operating status feature vector. The vector is correlated with the preset fault feature vector to calculate the recovery rate and optimization rate. For example, if the working status of a functional unit recovers from a fault, its status recovery rate is 100%; if the timing parameters are optimized from 200ns to 150ns, the timing parameter recovery rate is 25%; if the resource utilization rate is increased from 60% to 80%, the resource utilization optimization rate is 33.33%.

[0080] Finally, a multi-layer scoring model is established based on the above evaluation indicators. Assuming that the task priority is 9, the weights of the state recovery rate, timing recovery rate, and resource optimization rate can be set to 0.5, 0.3, and 0.2 respectively. The comprehensive repair score is obtained through weighted calculation, for example, 90 points. The output diagnostic report contains information such as the fault location (such as R2 area) and the repair status (such as restored to normal).

[0081] In this embodiment, by deploying the task load distribution strategy to the field programmable gate array (FPGA), the system can flexibly adjust the logical structure to cope with fault conditions. The establishment of the state machine execution model ensures the orderliness and controllability of the repair process, and accurately manages the state transition through the state transfer rule base, optimizing the response speed and efficiency of the repair process. The use of the double buffer structure improves the parallelism of data writing and output, and reduces the delay in the repair process. After the repair, the system collects and analyzes the running status data, so that the state recovery, timing parameters and resource utilization of the functional unit can be quantified. The correlation analysis with the preset fault feature vector provides a comprehensive evaluation of the repair effect. The multi-layer scoring model calculates the evaluation indicators by weight, and the generated comprehensive repair score provides an intuitive quantitative result for the fault repair effect. The final output diagnostic report not only contains the fault location information, but also reflects the repair status, helping engineers to quickly identify problems and optimize subsequent maintenance strategies. This solution significantly improves the adaptive ability and maintenance efficiency of the circuit board, and provides an important guarantee for the reliable operation of the intelligent system.

[0082] Figure 2 FIG. 1 is a schematic diagram of the structure of a circuit board fault diagnosis system based on artificial intelligence according to an embodiment of the present invention. Figure 2 As shown, the system comprises: The first unit is used to construct a three-dimensional electromagnetic field simulation model of a circuit board, set a plurality of virtual sensor probes in the three-dimensional electromagnetic field simulation model, the virtual sensor probes correspond to the physical sensor positions of the circuit board one by one, collect measured data of the physical sensor and simulation data of the virtual sensor probes, establish an abnormal behavior pattern library of the circuit board by comparing the deviation value between the measured data and the simulation data, construct a back propagation neural network according to the abnormal behavior pattern library, calculate the electromagnetic field distortion degree of each functional area of ​​the circuit board based on the back propagation neural network, and generate an electromagnetic field distortion distribution map; The second unit is used to divide the fault-sensitive area of ​​the circuit board based on the electromagnetic field distortion distribution map, deploy an adaptive sampling array in the fault-sensitive area, the adaptive sampling array includes a temperature sensing unit, a voltage sensing unit and an electromagnetic sensing unit, construct a fault feature vector according to the multi-dimensional signal collected by the adaptive sampling array, input the fault feature vector into a pre-trained reinforcement learning model, output the performance degradation rate of each functional area of ​​the circuit board, and generate a fault risk assessment matrix according to the performance degradation rate; The third unit is used to reconstruct the functions of the circuit board according to the fault risk assessment matrix, migrate the computing tasks in the high-risk area to the low-risk area, establish a dynamic fault-tolerant mechanism for the circuit board, generate a task load distribution strategy based on the dynamic fault-tolerant mechanism, deploy the task load distribution strategy to the field programmable gate array of the circuit board, autonomously repair the circuit board by adjusting the logical structure of the field programmable gate array, collect the operating data of the repaired circuit board, compare the operating data with the fault feature vector before repair, verify the repair effect and output a diagnosis report.

[0083] According to a third aspect of the embodiments of the present invention, An electronic device is provided, comprising: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0084] According to a fourth aspect of the embodiments of the present invention, A computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the aforementioned method is implemented.

[0085] The present invention may be a method, an apparatus, a system and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for executing various aspects of the present invention.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A circuit board fault diagnosis method based on artificial intelligence, characterized in that: include: Constructing a three-dimensional electromagnetic field simulation model of a circuit board, setting a plurality of virtual sensor probes in the three-dimensional electromagnetic field simulation model, wherein the virtual sensor probes correspond one-to-one to the physical sensor positions of the circuit board, collecting measured data of the physical sensor and simulation data of the virtual sensor probes, establishing an abnormal behavior pattern library of the circuit board by comparing the deviation values ​​between the measured data and the simulation data, constructing a back propagation neural network according to the abnormal behavior pattern library, calculating the degree of electromagnetic field distortion of each functional area of ​​the circuit board based on the back propagation neural network, and generating an electromagnetic field distortion distribution map; Based on the electromagnetic field distortion distribution map, the fault-sensitive area of ​​the circuit board is divided, and an adaptive sampling array is deployed in the fault-sensitive area, wherein the adaptive sampling array includes a temperature sensing unit, a voltage sensing unit, and an electromagnetic sensing unit. A fault feature vector is constructed according to the multi-dimensional signal collected by the adaptive sampling array, and the fault feature vector is input into a pre-trained reinforcement learning model, and the performance degradation rate of each functional area of ​​the circuit board is output, and a fault risk assessment matrix is ​​generated according to the performance degradation rate; The circuit board is functionally reconstructed according to the fault risk assessment matrix, computing tasks in high-risk areas are migrated to low-risk areas, a dynamic fault-tolerant mechanism for the circuit board is established, a task load distribution strategy is generated based on the dynamic fault-tolerant mechanism, the task load distribution strategy is deployed to the field programmable gate array of the circuit board, the circuit board is autonomously repaired by adjusting the logical structure of the field programmable gate array, the operating data of the repaired circuit board is collected, the operating data is compared with the fault feature vector before repair, the repair effect is verified and a diagnostic report is output.

2. The method according to claim 1, characterized in that By comparing the deviation values ​​of the measured data and the simulated data, an abnormal behavior pattern library of the circuit board is established, a back propagation neural network is constructed according to the abnormal behavior pattern library, and the electromagnetic field distortion degree of each functional area of ​​the circuit board is calculated based on the back propagation neural network to generate an electromagnetic field distortion distribution map, including: The time domain statistical features are generated by the adaptive wavelet decomposition module, the frequency domain spectrum features are generated by the fast Fourier transform module, and the attention mechanism is used to dynamically assign weights to the time domain statistical features and the frequency domain spectrum features to form a fusion feature vector; The recursive least squares algorithm is used to update the feature covariance matrix, and the Mahalanobis distance between the measured feature vector and the simulated feature vector is calculated based on the updated feature covariance matrix to obtain the abnormality sequence; A dual-criteria density clustering method based on local density and distance distribution is used to determine the cluster center of the abnormal degree sequence, and the clustering parameters are adaptively adjusted using the fractal dimension to form an abnormal pattern sequence. The abnormal mode sequence is decomposed through empirical mode decomposition to obtain the intrinsic mode function, and the evolution characteristics of the intrinsic mode function are extracted using a sliding time window. The time series association rules of the evolution characteristics are mined based on the improved Apriori algorithm to establish an abnormal behavior pattern library. A deep hybrid neural network is trained based on the abnormal behavior pattern library. The spatial domain features are extracted through the residual connection convolution layer. The temporal domain features are extracted using the long short-term memory unit and the gated recurrent unit. The topological domain features are extracted using the graph convolution layer. The extracted features are combined and input into the fully connected layer to output the electromagnetic field distortion prediction value. The spatial anisotropy constraints of circuit board wiring density and impedance distribution are introduced into the variogram. The Bayesian optimization algorithm is used to adjust the Kriging interpolation parameters. The electromagnetic field distortion prediction values ​​are spatially interpolated. The multi-resolution distortion distribution representation is constructed through wavelet transform to generate the electromagnetic field distortion distribution map.

3. The method according to claim 2, characterized in that The spatial anisotropy constraints of circuit board wiring density and impedance distribution are introduced into the variogram, and the Kriging interpolation parameters are adjusted by Bayesian optimization algorithm. The electromagnetic field distortion prediction value is spatially interpolated, and a multi-resolution distortion distribution representation is constructed by wavelet transform. The electromagnetic field distortion distribution map is generated, including: Constructing a density weight matrix based on the wiring density distribution of the circuit board, and constructing an impedance weight matrix based on the impedance distribution of the circuit board, and combining the density weight matrix and the impedance weight matrix through a rotation matrix to form an anisotropic matrix; Using the anisotropy matrix to construct an exponential variogram, the variogram includes a nugget effect value, a sill value, and a spatial vector product term of the anisotropy matrix; An optimization objective function including an interpolation prediction error term, a spatial smoothness constraint term and an anisotropic characteristic term is established, a mapping relationship between parameters and the objective function is established by using Gaussian process regression, and the nugget effect value, the sill value and the search radius of the Kriging interpolation of the variogram are iteratively optimized by maximizing the expected improvement criterion; The Kriging weight coefficient is calculated based on the optimized variogram, and the estimated value of the electromagnetic field distortion of the interpolation point is obtained by solving the Kriging equations; The electromagnetic field distortion estimation value is decomposed at multiple scales using orthogonal wavelet basis functions to obtain approximate coefficients of the coarsest scale and detail coefficients of different scales. The approximate coefficients and the detail coefficients are reconstructed to generate an electromagnetic field distortion distribution map. The electromagnetic field distortion distribution map uses pseudo-color coding to represent the distortion intensity and superimposes contour lines to display the distortion gradient changes.

4. The method according to claim 1, characterized in that: Constructing a fault feature vector according to the multidimensional signal collected by the adaptive sampling array, inputting the fault feature vector into a pre-trained reinforcement learning model, outputting the performance degradation rate of each functional area of ​​the circuit board, and generating a fault risk assessment matrix according to the performance degradation rate includes: Constructing a state space based on the multidimensional signals collected by the adaptive sampling array, wherein the state space includes functional unit states, operating parameters and historical diagnosis results, and constructing an action space, wherein the action space includes operating condition identification and risk assessment actions; Based on the state space, a functional association graph is constructed, wherein a vertex set in the functional association graph represents a functional unit of a circuit board, and an edge set represents a signal coupling relationship between the functional units; based on the functional association graph, mutual influences between the functional units are modeled through a graph attention mechanism to obtain fault characteristics; The top-level policy network of the executive body and the judge body structure is used for working condition identification. The executive body network processes the working condition state vector through the residual connection layer and the batch normalization layer to obtain the working condition category probability distribution. The judge body network evaluates the state value function, constructs an experience replay buffer to store state transition samples, and constructs a reward function according to the working condition identification accuracy and risk assessment effect. Constructing a variational autoencoder model, wherein the encoder uses a bidirectional long short-term memory network to map the input sequence consisting of the fault characteristics and the operating condition category probability distribution into a latent variable posterior distribution, and the decoder uses a transposed convolutional network to reconstruct the performance degradation trajectory; A causal temporal convolutional network is introduced into the latent variable posterior distribution space, wherein the causal temporal convolutional network obtains the performance degradation evolution law through hole convolution, and performs multiple forward propagations using random inactivation to obtain the performance degradation prediction result; Constructing a graph converter model, modeling the circuit board as a heterogeneous graph network, wherein the node features of the heterogeneous graph network include the failure probability, performance index and topological features of the functional unit, inputting the performance degradation prediction result into the graph converter model, and learning the risk propagation model through a multi-head attention mechanism; A causal graph is constructed based on the risk propagation model, a variational reasoning method is used to perform structural learning on the causal graph, and the fault propagation intensity between the functional units is evaluated through intervention calculation to generate a fault risk assessment matrix.

5. The method according to claim 4, characterized in that A causal graph is constructed based on the risk propagation model, a variational reasoning method is used to perform structural learning on the causal graph, and the fault propagation intensity between the functional units is evaluated through intervention calculation to generate a fault risk assessment matrix including: Constructing a neural causal graph, the neural causal graph includes directed edges between multiple functional unit nodes, extracting time series features of each functional unit node, using a variational adversarial neural network generator to map the time series features into conditional latent variables, and using a variational adversarial neural network discriminator to evaluate the difference between the conditional latent variables and the true distribution to obtain a time series feature representation; Based on the temporal feature representation, a graph morphology adaptive layer is constructed, wherein the graph morphology adaptive layer generates a dynamic convolution kernel according to the local structural features of the functional unit nodes, and adaptively adjusts the topological structure of the neural causal graph to obtain an optimized neural causal graph; Inputting the optimized neural causal graph into a causal graph neural network, wherein the causal embedding layer of the causal graph neural network maps the functional unit nodes to the causal representation space, and the causal reasoning layer extracts the causal dependency through gated graph convolution; The causal dependency relationship is input into a random causal field model, the random causal field model uses an energy function to perform joint distribution modeling on the states of the functional unit nodes, calculates the causal strength between the nodes, and uses a dual attention mechanism to process the causal strength to obtain an attention-enhanced causal feature; A risk propagation network is constructed based on the attention-enhanced causal features. The risk propagation network models the propagation of fault risks through graph diffusion convolution, adopts residual connections to maintain local risk features, outputs propagation features, and weightedly combines the propagation features with the causal strength to generate a fault risk assessment matrix, wherein the elements of the fault risk assessment matrix represent the degree of risk propagation between functional unit nodes.

6. The method according to claim 1, characterized in that The circuit board is functionally reconstructed according to the fault risk assessment matrix, computing tasks in high-risk areas are migrated to low-risk areas, a dynamic fault-tolerant mechanism for the circuit board is established, and a task load distribution strategy is generated based on the dynamic fault-tolerant mechanism, including: Calculate the incoming risk value and the outgoing risk value of each functional unit according to the fault risk assessment matrix, wherein the incoming risk value represents the risk impact degree of other functional units on the target functional unit, and the outgoing risk value represents the risk propagation degree of the target functional unit to other functional units; The inbound risk value and the outbound risk value are weightedly merged to obtain a comprehensive risk of each functional unit, and a migration optimization model is established for the computing tasks in the circuit board according to the comprehensive risk; Generate a set of candidate migration solutions based on the migration optimization model, calculate the overall system risk value for each candidate solution in the set of candidate migration solutions, and select the candidate solution with the minimum overall system risk value as the optimal task allocation solution; According to the optimal task allocation scheme, a three-module redundant structure is constructed in each functional unit, and the three-module redundant structure realizes reliable output of data through parallel data processing and majority voting selection mechanism; Collecting real-time load data of each functional unit, calculating the load distribution state in combination with the processing capacity of the functional unit, and calculating the deployment score for the task to be deployed according to the load distribution state; The task priority is calculated by combining the task importance index with the comprehensive risk, and a task queue based on priority sorting is generated, wherein the task priority in the task queue is dynamically adjusted according to the load distribution state; An initial task allocation plan is generated according to the task queue and the deployment score, and the initial allocation plan is iteratively optimized in combination with the risk assessment matrix and the processing capacity of each functional unit to output a final task load allocation strategy including task deployment location, execution timing and load adjustment parameters.

7. The method according to claim 1, characterized in that Deploy the task load distribution strategy to the field programmable gate array of the circuit board, autonomously repair the circuit board by adjusting the logical structure of the field programmable gate array, collect the operation data of the circuit board after the repair, compare the operation data with the fault feature vector before the repair, verify the repair effect and output a diagnostic report including: Establish a state machine execution model according to the received task load distribution strategy, and generate a state transition rule base including state transition conditions and trigger thresholds, wherein the state machine execution model includes an idle state, a loading start state, a loading state, a verification state, and a switching state; Reading the state transition condition in the state transition rule base, calculating the mapping relationship between the storage address of the configuration bit stream and the reconfigurable area of ​​the FPGA, and generating a configuration bit stream loading control signal according to the mapping relationship; Building a double buffer structure based on the load control signal, setting a buffer mutex and a buffer status flag, wherein the buffer status flag indicates a read / write status of a current buffer; Detecting the buffer state flag bit, when data is written into one buffer, setting a data output selection signal of another buffer according to the mutex lock; Writing the configuration bit stream into the writable buffer of the double buffer structure, and updating the buffer status flag after writing is completed, triggering the state machine to execute the state switching of the model; Collect the working status data, timing parameter data and resource occupancy data of the functional units in the FPGA, generate the operating status feature vector, perform correlation analysis on the operating status feature vector and the preset fault feature vector, calculate the functional unit status recovery rate, timing parameter recovery rate and resource utilization optimization rate, and generate the repair effect evaluation index; A multi-layer scoring model is established based on the repair effect evaluation indicators, and each evaluation indicator is weighted and calculated according to the weight set by the task priority identification bit to generate a comprehensive repair score, and output a diagnostic report containing fault location information and repair status information.

8. A circuit board fault diagnosis system based on artificial intelligence, used to implement the method described in any one of claims 1 to 7, characterized in that: include: The first unit is used to construct a three-dimensional electromagnetic field simulation model of a circuit board, set a plurality of virtual sensor probes in the three-dimensional electromagnetic field simulation model, the virtual sensor probes correspond to the physical sensor positions of the circuit board one by one, collect measured data of the physical sensor and simulation data of the virtual sensor probes, establish an abnormal behavior pattern library of the circuit board by comparing the deviation value between the measured data and the simulation data, construct a back propagation neural network according to the abnormal behavior pattern library, calculate the electromagnetic field distortion degree of each functional area of ​​the circuit board based on the back propagation neural network, and generate an electromagnetic field distortion distribution map; The second unit is used to divide the fault-sensitive area of ​​the circuit board based on the electromagnetic field distortion distribution map, deploy an adaptive sampling array in the fault-sensitive area, the adaptive sampling array includes a temperature sensing unit, a voltage sensing unit and an electromagnetic sensing unit, construct a fault feature vector according to the multi-dimensional signal collected by the adaptive sampling array, input the fault feature vector into a pre-trained reinforcement learning model, output the performance degradation rate of each functional area of ​​the circuit board, and generate a fault risk assessment matrix according to the performance degradation rate; The third unit is used to reconstruct the functions of the circuit board according to the fault risk assessment matrix, migrate the computing tasks in the high-risk area to the low-risk area, establish a dynamic fault-tolerant mechanism for the circuit board, generate a task load distribution strategy based on the dynamic fault-tolerant mechanism, deploy the task load distribution strategy to the field programmable gate array of the circuit board, autonomously repair the circuit board by adjusting the logical structure of the field programmable gate array, collect the operating data of the repaired circuit board, compare the operating data with the fault feature vector before repair, verify the repair effect and output a diagnosis report.

9. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method described in any one of claims 1 to 7.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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