Clock calibration method, device, electronic device and storage medium
By calculating the current adjustment value of the slave clock device, clock calibration is performed using the historical clock difference sequence between the master clock device and the slave clock device, the problem of time deviation during time synchronization in the prior art is solved, and the accuracy of clock calibration is improved and stability of the system.
Patent Information
- Application Number
- CN202210366493.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-04-08
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2042-04-08
AI Technical Summary
The existing timing methods have a big problem of time deviation during time synchronization. Network fluctuations will cause clock deviations to fail to be synchronized quickly, and may even cause the timing system to crash.
The current adjustment value of the slave clock device is calculated by calculating the current clock difference between the master clock device and the slave clock device, the first historical clock difference sequence and the second historical clock difference sequence, and the clock calibration is performed using historical data of different sequence lengths, providing two Re-references to reduce time deviation.
Improve the accuracy of clock calibration, significantly reduce time deviation, and enhance the stability of clock synchronization and system reliability.
Smart Images
Figure CN114826470B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of clock calibration, and in particular to a clock calibration method, device, electronic equipment and storage medium. Background Art
[0002] In existing timing methods, network fluctuations sometimes have a catastrophic impact on timing, and the clock deviation cannot be quickly synchronized. At the same time, there is also a clock deviation between the timing device and the device being timed. This will cause network devices to run in a state of low time accuracy for a long time, and may even cause the timing system to completely collapse. Therefore, when synchronizing time, existing timing methods have the problem of large time deviation. Summary of the invention
[0003] The embodiment of the present invention provides a clock calibration method, which aims to solve the problem of large time deviation in the existing timing method during time synchronization. The current adjustment value of the slave clock device is calculated by the current clock difference between the master clock device and the slave clock device, the first historical clock difference sequence and the second historical clock difference sequence, and the clock of the slave clock device is calibrated based on the current adjustment value. Since the sequence lengths of the first historical clock difference sequence and the second historical clock difference sequence are different, the current adjustment value has two references in the time dimension, which reduces the time deviation, thereby improving the accuracy of clock calibration.
[0004] In a first aspect, an embodiment of the present invention provides a clock calibration method, comprising the following steps:
[0005] Acquire a current clock difference between a master clock device and a slave clock device, a first historical clock difference sequence, and a second historical clock difference sequence, wherein a sequence length of the first historical clock difference sequence is greater than a sequence length of the second historical clock difference sequence;
[0006] Calculating a current adjustment value of the slave clock device according to the current clock difference, the first historical clock difference sequence and the second historical clock difference sequence;
[0007] The clock of the slave clock device is calibrated based on the current adjustment value and the clock of the master clock device.
[0008] Optionally, the current clock error is the clock error at the time of the i-th clock error measurement, and the step of acquiring the first historical clock error sequence between the master clock device and the slave clock device includes:
[0009] Get the clock error during the previous i-1 clock error measurements;
[0010] The clock errors during the previous i-1 clock error measurements are arranged in time sequence to obtain the first historical clock error sequence.
[0011] Optionally, the step of acquiring a second historical clock difference sequence between the master clock device and the slave clock device includes:
[0012] Get the clock difference during the previous n clock difference measurements;
[0013] The clock errors during the previous n clock error measurements are arranged in time sequence to obtain the second historical clock error sequence, where n is less than i-1.
[0014] Optionally, the step of calculating the current adjustment value of the slave clock device according to the current clock difference, the first historical clock difference sequence and the second historical clock difference sequence includes:
[0015] Calculating a first adjustment factor according to the current clock difference and the first historical clock difference sequence;
[0016] Calculating a second adjustment factor according to the second historical clock difference sequence;
[0017] The current adjustment value is calculated based on the current clock difference, the first adjustment factor, and the second adjustment factor.
[0018] Optionally, the first adjustment factor includes a sensitivity factor, a direction adjustment factor, and a weight factor between the current clock error and the first historical clock error sequence, and the step of calculating the first adjustment factor according to the current clock error and the first historical clock error sequence includes:
[0019] Calculating the average of the absolute values of the first historical clock error sequence;
[0020] When the current clock error is greater than the average of the absolute values of the first historical clock error sequence, updating the direction adjustment factor;
[0021] A first adjustment factor is calculated according to the updated direction adjustment factor, the sensitivity factor and the weight factor.
[0022] Optionally, the step of calculating a second adjustment factor according to the second historical clock difference sequence includes:
[0023] An average value of the second historical clock error sequence is calculated as the second adjustment factor.
[0024] Optionally, the step of calculating the current adjustment value based on the current clock difference, the first adjustment factor, and the second adjustment factor includes:
[0025] Calculating a first adjustment item according to the first adjustment factor and the second adjustment factor;
[0026] Calculate a second adjustment item based on the weight factor and the current clock difference;
[0027] The current adjustment value is obtained according to the first adjustment item and the second adjustment item.
[0028] In a second aspect, an embodiment of the present invention provides a clock calibration device, the device comprising:
[0029] An acquisition module, used to acquire a current clock difference between a master clock device and a slave clock device, a first historical clock difference sequence, and a second historical clock difference sequence, wherein the sequence length of the first historical clock difference sequence is greater than the sequence length of the second historical clock difference sequence;
[0030] A calculation module, configured to calculate a current adjustment value of the slave clock device according to the current clock difference, the first historical clock difference sequence and the second historical clock difference sequence;
[0031] A calibration module is used to calibrate the clock of the slave clock device based on the current adjustment value and the clock of the master clock device.
[0032] In a third aspect, an embodiment of the present invention provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps in the clock calibration method provided in the embodiment of the present invention when executing the computer program.
[0033] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps in the clock calibration method provided in the embodiment of the invention are implemented.
[0034] In an embodiment of the present invention, the current clock difference, the first historical clock difference sequence, and the second historical clock difference sequence between the master clock device and the slave clock device are obtained, and the sequence length of the first historical clock difference sequence is greater than the sequence length of the second historical clock difference sequence; the current adjustment value of the slave clock device is calculated according to the current clock difference, the first historical clock difference sequence, and the second historical clock difference sequence; and the clock of the slave clock device is calibrated based on the current adjustment value and the clock of the master clock device. The current adjustment value of the slave clock device is calculated by the current clock difference, the first historical clock difference sequence, and the second historical clock difference sequence between the master clock device and the slave clock device, and the clock of the slave clock device is calibrated based on the current adjustment value. Since the sequence lengths of the first historical clock difference sequence and the second historical clock difference sequence are different, the current adjustment value has two references in the time dimension, which reduces the time deviation, thereby improving the accuracy of clock calibration. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0036] Figure 1 is a flow chart of a clock calibration method provided by an embodiment of the present invention;
[0037] Figure 2 is a flow chart of another clock calibration method provided by an embodiment of the present invention;
[0038] Figure 3 is a clock error distribution diagram provided by an embodiment of the present invention without using the method of the embodiment of the present invention;
[0039] Figure 4 It is a clock difference distribution diagram provided by an embodiment of the present invention that is faster than the method of the embodiment of the present invention;
[0040] Figure 5 is a structural schematic diagram of a clock calibration device provided by an embodiment of the present invention;
[0041] Figure 6 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0043] See also Figure 1 , Figure 1 is a flow chart of a clock calibration method provided by an embodiment of the present invention, such as Figure 1 As shown, the clock calibration method includes the following steps:
[0044] 101. Obtain a current clock difference, a first historical clock difference sequence, and a second historical clock difference sequence between a master clock device and a slave clock device.
[0045] In the embodiment of the present invention, the sequence length of the first historical clock difference sequence is greater than the sequence length of the second historical clock difference sequence.
[0046] In specific applications, the clock calibration method can be applied to time synchronization between two network devices to provide accurate time synchronization services. One of the two network devices is a master clock device and the other is a slave clock device, wherein the master clock device can be understood as a device that provides a standard clock in the network, and the slave clock device can be understood as a device that needs to synchronize network time with the master clock device. Network time synchronization can be performed according to a time synchronization protocol, which includes but is not limited to time synchronization protocols such as PTP and gPTP.
[0047] The above-mentioned clock error refers to the time difference between the slave clock and the master clock (also called time deviation or clock deviation), which can be positive or negative. A positive value indicates that the system time of the slave clock is ahead of the system time of the master clock device, and a negative value indicates that the system time of the slave clock lags behind the system time of the master clock device.
[0048] The clock difference may be acquired by a clock deviation acquisition unit, and the clock deviation acquisition unit can acquire at least one data of the synchronous system time and the clock difference connected thereto.
[0049] Before clock calibration, the master clock device is turned on and waits to receive a clock synchronization request, where the clock synchronization request is initiated by the slave clock device. The slave clock device is turned on and sends a clock synchronization request to the master clock device. After receiving the clock synchronization request from the slave clock device, the master clock device responds and sends its current system time to the slave clock device. The slave clock device obtains the clock difference between itself and the master clock device through the clock deviation unit and stores it.
[0050] Since the sequence length of the first historical clock difference sequence is greater than that of the second historical clock difference sequence, the distribution quantities of the clock differences corresponding to the first historical clock difference sequence and the second historical clock difference sequence in the time dimension are different.
[0051] The current clock difference is obtained by a clock deviation obtaining unit. The current clock difference can be understood as the clock deviation between the master clock device and the slave clock device at the current moment.
[0052] Optionally, the current clock error is obtained by a clock deviation acquisition unit. In an embodiment of the present invention, the current clock error is assumed to be the clock error at the time of the i-th clock error measurement. In the step of obtaining the first historical clock error sequence between the master clock device and the slave clock device, the clock error at the time of the previous i-1 clock error measurement can be obtained; the clock errors at the time of the previous i-1 clock error measurement are arranged in time sequence to obtain the first historical clock error sequence.
[0053] Furthermore, the above-mentioned first historical clock error sequence can be understood as a clock error sequence formed by all i-1 clock errors acquired historically.
[0054] Optionally, in the step of obtaining a second historical clock difference sequence between the master clock device and the slave clock device, the clock differences during the previous n clock difference measurements can be obtained; the clock differences during the previous n clock difference measurements are arranged in time sequence to obtain a second historical clock difference sequence, where n is less than i-1.
[0055] Specifically, the above-mentioned first n times can be calculated from the i-n-1th time, and the second historical clock difference sequence at this time does not include the i-th clock difference. Of course, the above-mentioned first n times can be calculated from the i-nth time, and the second historical clock difference sequence at this time includes the i-th clock difference.
[0056] 102. Calculate a current adjustment value of the slave clock device according to the current clock difference, the first historical clock difference sequence, and the second historical clock difference sequence.
[0057] In the embodiment of the present invention, the current clock difference may be adjusted according to the first historical clock difference sequence and the second historical clock difference sequence to obtain a more accurate clock difference as the current adjustment value.
[0058] Optionally, in the step of calculating the current adjustment value of the slave clock device according to the current clock difference, the first historical clock difference sequence and the second historical clock difference sequence, a first adjustment factor can be calculated according to the current clock difference and the first historical clock difference sequence; the second adjustment factor can be calculated according to the second historical clock difference sequence; and the current adjustment value can be calculated based on the current clock difference, the first adjustment factor and the second adjustment factor.
[0059] Among them, the current clock error is the clock error at the time of the i-th clock error measurement, and the clock error at the time of the previous i-1 clock error measurement can be obtained; the clock errors at the time of the previous i-1 clock error measurement are arranged in time sequence to obtain the first historical clock error sequence. The clock error at the time of the previous n clock error measurements can be obtained; the clock errors at the time of the previous n clock error measurements are arranged in time sequence to obtain the second historical clock error sequence, where n is less than i-1.
[0060] The first adjustment factor is obtained through the first historical clock error sequence, and the second adjustment factor is obtained through the second historical clock error sequence. The first historical clock error sequence and the second historical clock error sequence have different distribution quantities in the time dimension. Since the first historical clock error sequence is the clock error during the previous i-1 clock error measurements, it can represent the global clock error distribution, and the second historical clock error sequence is the clock error during the previous n clock error measurements, it represents the most recent local clock error distribution. Through the global clock error distribution and the most recent local clock error distribution, the dynamic current adjustment value can be calculated. The clock of the slave clock device is calibrated through the dynamic current adjustment value, which can improve the accuracy of the clock.
[0061] Optionally, the first adjustment factor includes a sensitivity factor, a direction adjustment factor, and a weight factor between the current clock error and the first historical clock error sequence. In the step of calculating the first adjustment factor based on the current clock error and the first historical clock error sequence, the average value of the absolute values of the first historical clock error sequence can be calculated; when the current clock error is greater than the average value of the absolute values of the first historical clock error sequence, the direction adjustment factor is updated; and the first adjustment factor is calculated based on the updated direction adjustment factor, sensitivity factor and weight factor.
[0062] Specifically, the above-mentioned sensitivity factor can be selected according to actual needs, the above-mentioned direction adjustment factor can also be called the adjustment direction coefficient or the direction adjustment coefficient, the value of the direction adjustment factor can be limited to +1 or -1, and the above-mentioned weight factor is used to control the weight between the historical data and the current measurement data. Specifically, the above-mentioned weight factor is used to control the weight between the first historical clock difference sequence and the current clock difference.
[0063] First, the absolute value of each clock error in the first historical clock error sequence can be calculated to obtain the absolute value sequence of the first historical clock error sequence, and the average value of the absolute value sequence can be calculated to obtain the average value v of the absolute values of the first historical clock error sequence. Secondly, the current clock error can be set to di. When the current clock error di> the average value v of the absolute values of the first historical clock error sequence, it indicates that the current clock error deviates from the distribution of historical data and the measurement result of the current clock error deteriorates. At this time, the direction adjustment factor s is updated. Specifically, s'=s·(-1) can be set to update the direction adjustment factor s to obtain the updated direction adjustment factor s'; conversely, when the average value v of the absolute values of the first historical clock error sequence> the current clock error di, the current clock error measurement result develops and changes in the direction of gradual optimization, and the direction adjustment factor s can be kept unchanged. Finally, the first adjustment factor is calculated based on the updated direction adjustment factor, sensitivity factor and weight factor.
[0064] Specifically, the calculation formula of the first adjustment factor is as shown in the following formula:
[0065] w'=w+s'·t
[0066] Wherein, the above w' is the first adjustment factor, the above w is the weight factor, the above s' is the updated direction adjustment factor, and the above t is the sensitivity factor. It should be noted that the above first adjustment factor can also be called the iterated weight factor. When the average value v of the absolute value of the first historical clock error sequence> the current clock error di, the direction adjustment factor does not need to be updated, so the first adjustment factor is equal to the weight factor.
[0067] Optionally, in the step of calculating the second adjustment factor according to the second historical clock difference sequence, an average value of the second historical clock difference sequence may be calculated as the second adjustment factor.
[0068] In an embodiment of the present invention, the second historical clock error sequence is the clock error during the previous n clock error measurements, representing the most recent local clock error distribution. According to the local similarity, the second historical clock error sequence will most likely converge to the average value u, making the current adjustment value closer to the actual clock error.
[0069] Optionally, in the step of calculating the current adjustment value based on the current clock difference, the first adjustment factor and the second adjustment factor, the first adjustment item can be calculated based on the first adjustment factor and the second adjustment factor; the second adjustment item can be calculated based on the calculated weight factor and the current clock difference; and the current adjustment value can be obtained based on the first adjustment item and the second adjustment item.
[0070] In the embodiment of the present invention, assuming that the current clock error is di, the first adjustment factor is w', the second adjustment factor is u, and the weight factor is w, the current adjustment value can be expressed as follows:
[0071] d i '=w'·u+(1-w)·d i
[0072] Among them, the above d i ' is the current adjustment value.
[0073] It should be noted that when measuring the clock error for the i+1th time, based on the current adjustment value for the i-th time, the next round of clock error di+1 is continued to be received, and it is continuously iterated so that the current adjustment value gradually develops in the optimal direction, and the average value v of the absolute value of the first historical clock error sequence gradually converges.
[0074] 103. Calibrate the clock of the slave clock device based on the current adjustment value and the clock of the master clock device.
[0075] In an embodiment of the present invention, after the slave clock device sends a clock synchronization request to the master clock device, the master clock device responds to the clock synchronization request and sends the current system time to the slave clock device. The slave clock device adds the current adjustment value to the current system time sent by the master clock device to obtain a calibrated clock.
[0076] The clock adjustment unit can be used to add the current adjustment value to the current system time sent by the master clock device, so as to update the clock of the slave clock device, thereby realizing clock calibration of the slave clock device.
[0077] In an embodiment of the present invention, the current clock difference, the first historical clock difference sequence, and the second historical clock difference sequence between the master clock device and the slave clock device are obtained, and the sequence length of the first historical clock difference sequence is greater than the sequence length of the second historical clock difference sequence; the current adjustment value of the slave clock device is calculated according to the current clock difference, the first historical clock difference sequence, and the second historical clock difference sequence; and the clock of the slave clock device is calibrated based on the current adjustment value and the clock of the master clock device. The current adjustment value of the slave clock device is calculated by the current clock difference, the first historical clock difference sequence, and the second historical clock difference sequence between the master clock device and the slave clock device, and the clock of the slave clock device is calibrated based on the current adjustment value. Since the sequence lengths of the first historical clock difference sequence and the second historical clock difference sequence are different, the current adjustment value has two references in the time dimension, which reduces the time deviation, thereby improving the accuracy of clock calibration.
[0078] Optional, please refer to Figure 2 , Figure 2 is a flow chart of another clock calibration method provided by an embodiment of the present invention. Figure 2 As shown, the specific steps include:
[0079] 201. The master clock device is turned on and waits to receive a clock synchronization request.
[0080] 202. The slave clock device is turned on and sends a clock synchronization request to the master clock.
[0081] 203. The master clock sends its current system time to the slave clock.
[0082] 204. The slave clock obtains the clock difference between the slave clock and the master clock through the clock deviation obtaining unit for the mth time.
[0083] 205. Take the previous n clock differences and calculate the average value u.
[0084] 206. Calculate the average value v of the absolute values of all i-1 clock differences obtained historically.
[0085] 207. In the i-th measurement, update the average value v.
[0086] 208. Set an adjustment sensitivity t and an adjustment direction coefficient s, wherein the value of t is selected according to actual needs, and the value of s is limited to +1 or -1.
[0087] 209. Set a weight w to control the weight between historical data and current measurement data.
[0088] 210. In the i-th measurement, the clock error measured this time is di. If di>v, it indicates that the data deviates from the historical data and the measurement result deteriorates. Let s'=s·(-1) and update s. Otherwise, the measurement result develops in the direction of gradual optimization and s remains unchanged.
[0089] 211. Update w using s' obtained in step 10. The calculation method is as follows:
[0090] w'=w+s'·t
[0091] 212. Use the clock difference di measured this time, the average value u calculated in step 5 and w' obtained in step 11 to calculate the new clock difference d i 'The adjustment value is calculated as follows:
[0092] d i '=w'·u+(1-w)·d i
[0093] 213. Continue to receive the next round of data and iterate continuously. W gradually develops in the optimal direction, and the historical average value v also gradually converges.
[0094] The clock calibration method according to the embodiment of the present invention can adaptively and dynamically adjust the time synchronization system, significantly reduce system fluctuations, and provide more accurate timing services for the clock synchronization system.
[0095] Specifically, as shown in Table 1:
[0096] Table 1
[0097]
[0098] It can be seen that, by using the clock calibration method in the embodiment of the present invention, the mean square error of the clock error is smaller and the maximum value of the clock error is also smaller.
[0099] For more details, please refer to Figure 3 and Figure 4 , Figure 3 is a clock error distribution diagram provided by an embodiment of the present invention without using the method of the embodiment of the present invention, Figure 4 is a clock difference distribution diagram provided by an embodiment of the present invention that is faster than the method of the embodiment of the present invention, such as Figure 3 and Figure 4 As shown, obviously, Figure 4 The clock difference in is more converged, indicating that the clock synchronization is more stable.
[0100] It should be noted that the clock calibration method provided in the embodiment of the present invention can be applied to devices such as smart phones, computers, and servers.
[0101] Optional, see Figure 5 , Figure 5 is a schematic diagram of the structure of a clock calibration device provided by an embodiment of the present invention, such as Figure 5 As shown, the device comprises:
[0102] An acquisition module 501 is used to acquire a current clock difference between a master clock device and a slave clock device, a first historical clock difference sequence, and a second historical clock difference sequence, wherein the length of the first historical clock difference sequence is greater than the length of the second historical clock difference sequence;
[0103] A calculation module 502, configured to calculate a current adjustment value of the slave clock device according to the current clock difference, the first historical clock difference sequence and the second historical clock difference sequence;
[0104] The calibration module 503 is configured to calibrate the clock of the slave clock device based on the current adjustment value and the clock of the master clock device.
[0105] Optionally, the current clock error is the clock error during the i-th clock error measurement, and the acquisition module 501 includes:
[0106] The first acquisition submodule is used to obtain the clock error during the previous i-1 clock error measurements;
[0107] The first arrangement submodule is used to arrange the clock errors during the previous i-1 clock error measurements in time sequence to obtain the first historical clock error sequence.
[0108] Optionally, the acquisition module 501 includes:
[0109] The second acquisition submodule is used to obtain the clock difference during the previous n clock difference measurements;
[0110] The second arrangement submodule is used to arrange the clock errors during the previous n clock error measurements in time sequence to obtain the second historical clock error sequence, where n is less than i-1.
[0111] Optionally, the calculation module 502 includes:
[0112] A first calculation submodule, configured to calculate a first adjustment factor according to the current clock difference and the first historical clock difference sequence;
[0113] A second calculation submodule, configured to calculate a second adjustment factor according to the second historical clock difference sequence;
[0114] The third calculation submodule is used to calculate the current adjustment value based on the current clock difference, the first adjustment factor and the second adjustment factor.
[0115] Optionally, the first adjustment factor includes a sensitivity factor, a direction adjustment factor, and a weight factor between the current clock error and the first historical clock error sequence, and the first calculation submodule includes:
[0116] A first calculation unit, configured to calculate an average value of the absolute values of the first historical clock error sequence;
[0117] an updating unit, configured to update the direction adjustment factor when the current clock error is greater than an average of absolute values of the first historical clock error sequence;
[0118] The second calculation unit is used to calculate the first adjustment factor according to the updated direction adjustment factor, the sensitivity factor and the weight factor.
[0119] Optionally, the second calculation submodule includes:
[0120] The third calculation unit is used to calculate the average value of the second historical clock error sequence as the second adjustment factor.
[0121] Optionally, the third calculation submodule includes:
[0122] a fourth calculation unit, configured to calculate a first adjustment item according to the first adjustment factor and the second adjustment factor;
[0123] A fifth calculation unit, configured to calculate a second adjustment item by calculating the weight factor and the current clock difference;
[0124] A determining unit is used to obtain the current adjustment value according to the first adjustment item and the second adjustment item.
[0125] It should be noted that the clock calibration device provided in the embodiment of the present invention can be applied to smart phones, computers, servers and other devices that can perform business analysis at the map level.
[0126] The clock calibration device provided in the embodiment of the present invention can implement each process implemented by the clock calibration method in the above method embodiment and can achieve the same beneficial effect. To avoid repetition, it will not be described here.
[0127] See also Figure 6 , Figure 6 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention, such as Figure 6 As shown, it includes: a memory 602, a processor 601, and a computer program of a clock calibration method stored in the memory 602 and executable on the processor 601, wherein:
[0128] The processor 601 is used to call the computer program stored in the memory 602 and execute the following steps:
[0129] Acquire a current clock difference between a master clock device and a slave clock device, a first historical clock difference sequence, and a second historical clock difference sequence, wherein a sequence length of the first historical clock difference sequence is greater than a sequence length of the second historical clock difference sequence;
[0130] Calculating a current adjustment value of the slave clock device according to the current clock difference, the first historical clock difference sequence and the second historical clock difference sequence;
[0131] The clock of the slave clock device is calibrated based on the current adjustment value and the clock of the master clock device.
[0132] Optionally, the current clock difference executed by the processor 601 is the clock difference at the i-th clock difference measurement, and the step of acquiring a first historical clock difference sequence between the master clock device and the slave clock device includes:
[0133] Get the clock error during the previous i-1 clock error measurements;
[0134] The clock errors during the previous i-1 clock error measurements are arranged in time sequence to obtain the first historical clock error sequence.
[0135] Optionally, the step of acquiring a second historical clock difference sequence between the master clock device and the slave clock device executed by the processor 601 includes:
[0136] Get the clock difference during the previous n clock difference measurements;
[0137] The clock errors during the previous n clock error measurements are arranged in time sequence to obtain the second historical clock error sequence, where n is less than i-1.
[0138] Optionally, the step of calculating the current adjustment value of the slave clock device according to the current clock difference, the first historical clock difference sequence, and the second historical clock difference sequence, performed by the processor 601 includes:
[0139] Calculating a first adjustment factor according to the current clock difference and the first historical clock difference sequence;
[0140] Calculating a second adjustment factor according to the second historical clock difference sequence;
[0141] The current adjustment value is calculated based on the current clock difference, the first adjustment factor, and the second adjustment factor.
[0142] Optionally, the first adjustment factor includes a sensitivity factor, a direction adjustment factor, and a weight factor between the current clock error and the first historical clock error sequence, and the step of calculating the first adjustment factor according to the current clock error and the first historical clock error sequence performed by the processor 601 includes:
[0143] Calculating the average of the absolute values of the first historical clock error sequence;
[0144] When the current clock error is greater than the average of the absolute values of the first historical clock error sequence, updating the direction adjustment factor;
[0145] A first adjustment factor is calculated according to the updated direction adjustment factor, the sensitivity factor and the weight factor.
[0146] Optionally, the step of calculating a second adjustment factor according to the second historical clock difference sequence performed by the processor 601 includes:
[0147] An average value of the second historical clock error sequence is calculated as the second adjustment factor.
[0148] Optionally, the step of calculating the current adjustment value based on the current clock difference, the first adjustment factor, and the second adjustment factor, performed by the processor 601 includes:
[0149] Calculating a first adjustment item according to the first adjustment factor and the second adjustment factor;
[0150] Calculate a second adjustment item based on the weight factor and the current clock difference;
[0151] The current adjustment value is obtained according to the first adjustment item and the second adjustment item.
[0152] It should be noted that the electronic device provided in the embodiment of the present invention can be applied to devices such as smart phones, computers, servers, etc. that can perform clock calibration.
[0153] The electronic device provided by the embodiment of the present invention can implement each process implemented by the clock calibration method in the above method embodiment and can achieve the same beneficial effect. To avoid repetition, it will not be described here.
[0154] An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the clock calibration method or the application-end clock calibration method provided in the embodiment of the present invention are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.
[0155] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.
[0156] The above disclosure is only the preferred embodiment of the present invention, which certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.
Claims
1. A clock calibration method, characterized in that: The following steps are involved: Acquire a current clock difference between a master clock device and a slave clock device, a first historical clock difference sequence, and a second historical clock difference sequence, wherein a sequence length of the first historical clock difference sequence is greater than a sequence length of the second historical clock difference sequence; Calculating a current adjustment value of the slave clock device according to the current clock difference, the first historical clock difference sequence and the second historical clock difference sequence; calibrating the clock of the slave clock device based on the current adjustment value and the clock of the master clock device; The step of calculating the current adjustment value of the slave clock device according to the current clock difference, the first historical clock difference sequence and the second historical clock difference sequence comprises: Calculating a first adjustment factor according to the current clock difference and the first historical clock difference sequence; Calculating a second adjustment factor according to the second historical clock difference sequence; Calculate the current adjustment value based on the current clock difference, the first adjustment factor, and the second adjustment factor; The first adjustment factor includes a sensitivity factor, a direction adjustment factor, and a weight factor between the current clock error and the first historical clock error sequence. The step of calculating the first adjustment factor according to the current clock error and the first historical clock error sequence includes: Calculating the average of the absolute values of the first historical clock error sequence; When the current clock error is greater than the average of the absolute values of the first historical clock error sequence, updating the direction adjustment factor; A first adjustment factor is calculated according to the updated direction adjustment factor, the sensitivity factor and the weight factor.
2. The method according to claim 1, characterized in that The current clock error is the clock error at the time of the i-th clock error measurement, and the step of obtaining the first historical clock error sequence between the master clock device and the slave clock device includes: Get the clock error during the previous i-1 clock error measurements; The clock errors during the previous i-1 clock error measurements are arranged in time sequence to obtain the first historical clock error sequence.
3. The method according to claim 2, characterized in that The step of obtaining a second historical clock difference sequence between the master clock device and the slave clock device comprises: Get the clock difference during the previous n clock difference measurements; The clock errors during the previous n clock error measurements are arranged in time sequence to obtain the second historical clock error sequence, where n is less than i-1.
4. The method according to claim 1, characterized in that The step of calculating the second adjustment factor according to the second historical clock difference sequence comprises: An average value of the second historical clock error sequence is calculated as the second adjustment factor.
5. The method according to claim 4, characterized in that The step of calculating the current adjustment value based on the current clock difference, the first adjustment factor and the second adjustment factor comprises: Calculating a first adjustment item according to the first adjustment factor and the second adjustment factor; Calculate a second adjustment item based on the weight factor and the current clock difference; The current adjustment value is obtained according to the first adjustment item and the second adjustment item.
6. A clock calibration device, characterized in that: include: An acquisition module, used to acquire a current clock difference between a master clock device and a slave clock device, a first historical clock difference sequence, and a second historical clock difference sequence, wherein the sequence length of the first historical clock difference sequence is greater than the sequence length of the second historical clock difference sequence; A calculation module, configured to calculate a current adjustment value of the slave clock device according to the current clock difference, the first historical clock difference sequence and the second historical clock difference sequence; a calibration module, configured to calibrate the clock of the slave clock device based on the current adjustment value and the clock of the master clock device; Wherein, the calculation module is specifically used for: Calculating a first adjustment factor according to the current clock difference and the first historical clock difference sequence; Calculating a second adjustment factor according to the second historical clock difference sequence; Calculate the current adjustment value based on the current clock difference, the first adjustment factor, and the second adjustment factor; The first adjustment factor includes a sensitivity factor, a direction adjustment factor, and a weight factor between the current clock error and the first historical clock error sequence. The step of calculating the first adjustment factor according to the current clock error and the first historical clock error sequence includes: Calculating the average of the absolute values of the first historical clock error series; When the current clock error is greater than the average of the absolute values of the first historical clock error sequence, updating the direction adjustment factor; A first adjustment factor is calculated according to the updated direction adjustment factor, the sensitivity factor and the weight factor.
7. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps in the clock calibration method according to any one of claims 1 to 5 when executing the computer program.
8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the clock calibration method according to any one of claims 1 to 5 are implemented.