35results about How to "Reduce time skew" patented technology

Semiconductor integrated circuit devices that operate under different power supply voltages are directly interconnected by a bidirectional bus which is a transmission line. A driver is of a push-pull type and a reception side is CTT-terminated. If a terminating resistor is in conformity with the characteristic impedance of the transmission line, the on resistance of the driver is equal to or lower than the characteristic impedance. If the on resistance of the driver is in conformity with the characteristic impedance of the transmission line, the value of the terminating resistor is equal to or lower than the characteristic impedance of the transmission line. If the reception side is VTT-terminated, the value of the VTT is ½ of a lower one of power supply voltages that are supplied to the respective semiconductor integrated circuit devices. The value of the terminating resistor is in conformity with the characteristic impedance of the transmission line. The semiconductor integrated circuit devices use a common reference voltage for determining the signal voltage.

The invention relates to an audio and video playing method and device, a computer device and a storage medium. The method comprises the steps of obtaining target playing position information; when a target decoded audio and video frame is found from a decoded cache queue according to the target playing position information, deleting the decoded audio and video frame before the target decoded audioand video frame in the decoded cache queue; and taking out the decoded audio and video frames in the decoded cache queue, rendering the taken-out decoded audio and video frames, and displaying a rendering result. Since rendering playing can be started from the position of the target decoded audio and video frame corresponding to the target playing position information in the decoded cache queue,the time deviation between the actual playing position and the target playing position can be reduced.

A coherent light receiving device includes a coherent receiving unit which mixes a received optical signal with local light and performs optical coherent detection to output a digital signal, a wavelength dispersion compensation unit which compensates for waveform distortion in the digital signal and outputs a digital signal after compensation, and a frequency difference detection unit which detects the frequency difference between the received optical signal and local light and notifies the wavelength dispersion compensation unit of the frequency difference, wherein the wavelength dispersion compensation unit performs compensation using a transfer function which is based on the frequency difference notified from the frequency difference detection unit and represents waveform distortion due to wavelength dispersion.

The invention provides a whole network clock synchronization method and a whole network clock synchronization device applied to an LTE rail traffic network. The method comprises the following steps: aGPS clock adopted by a clock source server is used as a reference time reference source of the whole network NTP clock synchronization. The NTP client uses the network management platform as the clock source server, and synchronizes the NTP clock with the clock source server based on the reference time reference source. The core network, base station and log server are used as the NTP client of the network management platform to synchronize the NTP clock with the network management platform, and the vehicle terminal is used as the NTP client of the network management platform to synchronize the NTP clock with the network management platform. The method of the invention realizes the technical effect of clock synchronization of the whole rail transit network.

A sheet processing apparatus includes a hole punching section arranged downstream from a skew detecting unit and orthogonally to a conveying path of a sheet, and a control unit configured to change the tilt angle of the hole punching section in accordance with each of the quantity of skew at the forward edge and the quantity of skew at the rear edge of the sheet, carry out skew correction at the forward edge within a first correction range w1, and carry out skew correction at the rear edge within a second correction range w2 (where w1>w2≧w1/2). The control unit carries out skew correction at the forward edge within the correction range w2, in the case where the detected quantity of skew at the forward edge is a tilt angle exceeding the correction range w2, and then carries out skew correction at the rear edge in accordance with the difference between the quantity of skew at the forward edge after the correction and the quantity of skew at the rear edge.

The invention provides a camera and laser radar synchronization method and system of an intelligent driving control system, and the method comprises the steps: calculating the synchronization delay time of the exposure time of the camera according to the frame rate and the installation angle of the camera, and enabling the exposure time to be just the same as the time when the laser radar scans the angle; at the moment, laser radar data and camera data can be subjected to fusion processing, and accurate time and space information is obtained.

In a system and method for feature alignment in chromatographic systems, the system runs a first sample through a first separation column. The system determines a first set of features for the first sample run. The system runs a second sample through a second separation column and detects a second set of features for the second sample run. The system estimates a systematic shift in features between the first sample run through the first separation column and the second sample run through the second separation column. The system adjusts the second set of features detected for the second sample run through the second separation column based on the estimated systematic shift to obtain a third set of adjusted features.

The invention provides a pulse arrival timestamp marking method based on secondary zero crossing point detection and judgment. According to the method, a time synchronization-based time difference measurement principle is adopted, each of a main station and various secondary stations sets a high-stability and unified time reference, receives a target response signal, detects, judges and digitalizes the target response signal, searches for a signal crossing point, marks a time stamp and acquires the time of arrival of the target response signal, and the main station and the various secondary stations calculate the time of arrival of the target response signal according to the respective time stamps and then transmit the time of arrival to a data processing center; and the data processing center calculates the time difference of arrival according to the time of arrival, and then the position of a target is estimated. The method has the advantages that the time deviations between the marking positions of the time of arrival and the correct time of arrival (the zero crossing points) can be minimized maximally, the purpose of suppressing time of arrival estimation errors caused by zerocrossing point detection is achieved, and the precision of TOA measurement of the base stations can be significantly improved in the environment which is bad in signal-to-noise ratio.

The invention relates to the technical field of semiconductor integrated circuits, in particular to a memory read data test circuit structure and a design method thereof. The structure comprises a read signal path which comprises a clock gating unit and a first combinational logic circuit unit; the clock end of the clock gating unit is connected with a synchronous clock signal; the address path comprises an address register unit, a logic control circuit unit, an address latch unit and a second combinational logic circuit unit; wherein the clock end of the address register unit is connected with a synchronous clock signal, the data output end of the address register unit is connected with the input end of the logic control circuit unit, the output end of the logic control circuit unit is connected with the data input end of the address latch unit, and the clock end of the address latch unit is connected with the synchronous clock signal. By means of the read signal generation step, theaddress signal generation step and the address latch step, a synchronous clock is adopted, and the problem that in the related technology, it is complex and difficult to guarantee high-precision timesequence balance can be solved.

An ink ribbon cassette is provided. The ink ribbon cassette includes a ribbon outlet provided near a first ribbon-receiving part of an ink ribbon cassette of the invention in a head insertion opening. A ribbon winding opening is provided near a second ribbon-receiving part in the head insertion opening. A first paper guide is provided at the ribbon outlet and a second paper guide is provided at the ribbon winding opening so that a recording paper to be fed is guided by the first and second paper guides.

The invention discloses a time calibration method, apparatus and system for realizing time alignment of a server. The method is applied to a time server and comprises the following steps: when a standard time obtaining request sent by an application server is received, sending a standard time to the application server; receiving a time sampling result and/or a time correction result sent by the application server, wherein the time sampling result comprises a current server time of the application server and a difference between the current server time and the standard time, the time correctionresult is generated after the application server satisfies a preset condition and corrects a local server time according to the time sampling result, and the time correction result comprises a time before being corrected by the application server and a time corrected by the application server; and when a query result comprising a log time sent by a log time query terminal is received, sending thetime sampling result and/or the time correction result corresponding to the log time to the log time query terminal.

Disclosed herein is a scan optimizer system and method designed to generate optimal ATE input/output timing with small margin but yielding stable results. Therefore the scan test time is greatly improved.

The invention discloses a phase adjustment method for a cesium and hydrogen atom frequency standard, wherein the method does not adopt a classical mode and method in the industry to regulate and control the phase performance of an atomic clock group and does not need to adopt a plurality of expensive cesium clocks and hydrogen clocks, and can remarkably reduce the time deviation relative to UTC and enable the performance index to reach the nanosecond or subnanosecond level through the method provided by the technical scheme of the invention; and the system investment can be greatly reduced, and similar or higher performance can be obtained only by a million yuan level. The system is small in size, high in performance, suitable for rapid arrangement, capable of being applied to ships, vehicles, common machine rooms and other environments, and wider in application range.