The invention relates to the technical field of
semiconductor integrated circuits, in particular to a memory read data test circuit structure and a design method thereof. The structure comprises a read
signal path which comprises a
clock gating unit and a first
combinational logic circuit unit; the
clock end of the
clock gating unit is connected with a synchronous
clock signal; the address path comprises an address register unit, a
logic control circuit unit, an address latch unit and a second
combinational logic circuit unit; wherein the clock end of the address register unit is connected with a synchronous
clock signal, the data output end of the address register unit is connected with the input end of the
logic control circuit unit, the output end of the
logic control circuit unit is connected with the
data input end of the address latch unit, and the clock end of the address latch unit is connected with the synchronous
clock signal. By means of the read
signal generation step, theaddress
signal generation step and the address latch step, a synchronous clock is adopted, and the problem that in the related technology, it is complex and difficult to guarantee high-precision timesequence balance can be solved.