Memory read data test circuit structure and design method thereof

Abstract

The invention relates to the technical field of semiconductor integrated circuits, in particular to a memory read data test circuit structure and a design method thereof. The structure comprises a read signal path which comprises a clock gating unit and a first combinational logic circuit unit; the clock end of the clock gating unit is connected with a synchronous clock signal; the address path comprises an address register unit, a logic control circuit unit, an address latch unit and a second combinational logic circuit unit; wherein the clock end of the address register unit is connected with a synchronous clock signal, the data output end of the address register unit is connected with the input end of the logic control circuit unit, the output end of the logic control circuit unit is connected with the data input end of the address latch unit, and the clock end of the address latch unit is connected with the synchronous clock signal. By means of the read signal generation step, theaddress signal generation step and the address latch step, a synchronous clock is adopted, and the problem that in the related technology, it is complex and difficult to guarantee high-precision timesequence balance can be solved.

Description

technical field [0001] The present application relates to the technical field of semiconductor integrated circuits, in particular to a memory read data test circuit structure and a design method thereof. Background technique [0002] The memory is the main medium used for data storage in the computer, and the reading and writing speed of the memory greatly affects the working speed of the computer. In recent years, with the rapid development of Internet technologies such as cloud computing, the requirements for the read and write speed of the memory are getting higher and higher; the memory read data circuit is used to read the data stored in the storage unit corresponding to the specific address according to the read signal. data. [0003] When reading data on a specific address according to the read signal, it is necessary to ensure that the read signal transmitted on the read signal path and the address signal transmitted on the address path arrive at the memory at the s...

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Problems solved by technology

[0005] This application provides a memory read data test circuit structure and its design method, which can solve the complex and difficult problem of ensuring high-precision timing balance in related technologies

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