31 results about "DDR2 SDRAM" patented technology

A high-density DDR-1 / DDR-2 compatible SDRAM chip with a reduced output circuit area is provided. When the SDRAM is a DDR1 SDRAM, an output signal output from an output circuit (14) is output to an output terminal (17) as a main output signal. When the SDRAM is a DDR2 SDRAM, an output signal output from an output circuit (15) is output to the output terminal (17) as the main output signal and, at the same time, the output signal output from the output circuit (14) is output as a sub-output signal to perform operation for adjusting the slew rate or the amount of output current of the main output signal or for adjusting the impedance of the output terminal as viewed from an external point.

The invention discloses an object detection method of a system on chip based on FPGA. The method comprises the following steps: an analog receiver acquiring an analog signal and converting the acquired analog signal to an I-path analog signal and a Q-path analog signal, a data acquisition and analog-digital conversion module separately sampling the I-path analog signal and the Q-path analog signal, then conducting analog-digital conversion to obtain a digital complex signal, then transmitting a receiving identification to a state machine; a DDR2-SDRAM conducting cache on the digital complex signal; the state machine, based on the receiving identification, reading the cached digital complex signal from the DDR2-SDRAM, recording the coordinate of each data in a data matrix; a data processing module acquiring a window of the shape of the Chinese character mi, calculating the mean value of reference data of the data matrix so as to determine the object in the data matrix and the position coordinate of the object, at the same time acquiring data calculation completion identification, and transmitting the data calculation completion identification to the state machine, thus completing data processing.

The present invention relates to a data pass control device for masking a ringing of a data strobe that occurs when a write operation in a DDR SDRAM is completed. The data pass control device for masking the write ringing in the DDR SDRAM can be advantageously used for masking only a section with the ringing problem during the write operation, so that any unnecessary operations during the write operation can be eliminated and a more stable write operation can be realized by eliminating a write fail.

The present invention discloses a method for short cycle data storage based on a DDR2 SDRAM (Double Data Rate 2 SDRAM, the second generation double data rate synchronous dynamic random access memory, DDR2 for short). The method comprises the steps of determining a read-write short cycle and read-write operation execution times in the short cycle according to the storage rate requirement and DDR2 model; designing a few-row-multiple-column storage structure according to a read-write scheme and DDR2 storage space; and controlling the DDR2 to alternatively perform the read-write operation in the short cycle by a user through an MIG (Memory Interface Generator). The problem that in the prior art, continuous in and out of data are restricted by a storage method that read-write operation is individually executed for a long time is solved, and data access efficiency is improved when the DDR2 processes data under the condition that read-write sequences are not consistent.

A double-data-rate two synchronous dynamic random access (DDR2) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core having a common output wherein a high-speed output path and a low-speed output path are coupled together by an output coupling and further coupled to the common output of the memory core.

The invention discloses a DDR2-SDRAM controller and a corresponding low-delay optimization method for a high-performance RF automatic test platform. The DDR2-SDRAM controller is characterized in that, first, it does not regard the external storage module as a single resources, but according to the rank and bank structure of the DRAM module, the memory storage space is divided into several independent logical resources, each resource is private to a task with memory access requirements, and on this basis, the present invention designs corresponding Arbitration method and instruction sequence. The second is that it improves the refresh mechanism. The controller arranges a refresh cycle at the end of 60 memory access instruction cycles, and refreshes the specified row in the storage array through row access, which reduces the refresh time to zero and reduces memory access requests. The impact of conflicting with refresh requests on memory access latency. Ultimately, the maximum memory access latency performance of each task in the system is greatly improved.

The invention relates to a Sudoku based fine motion estimation data reading method. When an H.264 high-definition video coding core carries out fine motion estimation, data in a search box are great in size and disordered, and relatively multiple cross-row operations are required, so the reading-writing efficiency is low, and a plenty of time is taken for writing the data into an off-chip DDR2 SDRAM. According to the invention, a macro-block reading method for visiting according to a fixed sequence is provided. As the visiting speed of fine motion is increased by adopting a method in which a Sudoku form is adopted for buffer-on-chip of data, an address prejudgment method, a redundancy data early termination method and the like, data of fine motion estimation can be taken back rapidly and exactly, and the speed required by high-definition real-time coding is realized.

The invention relates to a switchboard based extensible DSPEED-DSP_Q6474 signal processing board, which belongs to the field of high-speed real-time signal processing. The processing board comprises a single-core DSP processing node, four three-core DSP processing nodes, an FPGA (Field Programmable Gate Array) processing node, a serial Rapid IO (Input-Output) switchboard module and a CPCI 6U standard board type, wherein the single-core DSP processing node consists of a TMS320C6455 and a set of DDR2 SDRAMs of which the volume is 512MB; the three-core DSP processing node consists of a TMS320C6474 and a set of DDR2 SDAMs of which the volume is 512MB; and the FPGA processing node consists of an XC5VSX95 or an XC5VLX110T and two sets of DDR2SDRAMs of which the volume is 512MB. The invention solves the problems of small data exchange bandwidth between the traditional high-speed real-time signal processing board processors, non-uniform interface protocols and poor intra-board extendibility.

The invention relates to a double data rate (DDR) 2 synchronous dynamic random access memory (SDRAM) controller. Due to the fact that the DDR2SDRAM controller follows a DDR2SDRAM interface protocol, data transmission between the DDR2SDRAM controller and an outside DDR2SDRAM is achieved. The DDR2SDRAM controller comprises a DDR2SDRAM interface, a system data bus interface, an order arbiter and a command queuing and reordering module, wherein the DDR2SDRAM interface achieves various signals a DDR2SDRAM interface protocol definition; the system data bus interface achieves an interface function of the sides of system data buses and can be copied to meet requirements of the connection of a plurality of data buses; the order arbiter aims at requests of the plurality of data buses and enables only one route of data bus to visit the outside DDR2SDRAM within the same time; the command queuing and reordering module receives a reading / writing request command which is output by the order arbiter, the reading / writing request command is reordered according to relevancy of an address, and thereby the use ratio of the DDR2SDRAM interface is improved.

The invention discloses an embedded infrared real-time signal processing system, which is mainly used for an infrared detection system. The system mainly comprises an embedded signal processing board card, wherein an FPGA (Field Programmable Gate Array) with an embedded Power PC (Personal Computer) microprocessor is used as a core controller and is externally connected with a large-capacity DDR2 SDRAM (Double Data Rate 2 Synchronous Dynamic Random Access Memory) and embedded peripheral equipment. An embedded real-time operating system Vx Works based software platform is established on the Power PC microprocessor; and embedded infrared real-time signal processing can be realized by rationally selecting software and hardware of an infrared signal processing algorithm. The system has the main advantages that: a design scheme of the embedded system is adopted; a hardware structure of the embedded Power PC microprocessor in the FPGA and the embedded real-time operating system Vx Works based software platform are used; the entire infrared signal processing system is integrated on one board card; and the entire system is provided with various external interfaces, has high real-time property and a small size and is convenient to carry.