Field programmable gate array (FPGA) and digital signal processor (DSP) data transmission system based on Ping Pong mechanism

Abstract

The invention provides a field programmable gate array (FPGA) and digital signal processor (DSP) data transmission system based on a Ping Pong mechanism. The FPGA and DSP data transmission system based on the Ping Pong mechanism comprises a two-channel selector switch, an FPGA, a DSP and two memories. The on-off state of the two-channel selector switch is controlled by the FPGA so as to realize the alternate operation of a first read/write channel and a second read/write channel, and therefore, alternate storage and read of data is realized; the first read/write channel is characterized in that cache current data of the FPGA are written into a first memory, and meanwhile, the data written in at the previous moment are read from a second memory by the DSP; the second read/write channel is characterized in that the cache current data of the FPGA are written into the second memory, and meanwhile, the data written in at the previous moment are read from the first memory by the DSP. The continuous data are alternately stored and read in turn between the two memories [double data rate 2 synchronous dynamic random access memory] (DDR2 SDRAM) through a Ping Pong way, and therefore, the waiting time is saved, and the data transmission efficiency is improved.

Description

Technical field [0001] The invention relates to the field of high-speed data transmission, in particular to an FPGA and DSP data transmission system based on a ping-pong mechanism, and is particularly suitable for high-speed transmission of image data between FPGA and DSP. Background technique [0002] For a long time, most of the work of high-speed image transmission and processing was performed on a microcomputer using a single machine or a cluster joint mechanism. The microprocessor of the special-purpose computer is only oriented to the general application level, and it is not efficient for the special data-intensive application of high-speed digital processing. At the same time, the cluster working mode has problems such as high power consumption and complex system, which restrict its application. The use of DDR as the interface of FPGA and DSP cooperative operation mode to achieve high-speed signal transmission and processing has become a hot topic in recent years. This t...

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Problems solved by technology

[0005] However, both of the above two schemes adopt the single-bus transmission mode of DDR2 SDRAM, which has low efficiency and is difficult to meet the transmission requirements of high-speed data.

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