DDR2-SDRAM controller and low latency optimization method therefor

A DDR2-SDRAM and controller technology, applied in the field of automatic test platform design, to improve real-time performance, reduce memory access delay, and avoid address correlation

Active Publication Date: 2015-11-11
SOUTHEAST UNIV
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  • Abstract
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  • Claims
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Problems solved by technology

In the RF automatic test platform, due to the limitation of the application occasion, the response and proc

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  • DDR2-SDRAM controller and low latency optimization method therefor
  • DDR2-SDRAM controller and low latency optimization method therefor
  • DDR2-SDRAM controller and low latency optimization method therefor

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Embodiment Construction

[0027] The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0028] Such as figure 1 As shown, for the functions to be realized by the DDR2-SDRAM controller, using the concept of modularization, the control logic of the entire controller can be divided into 5 modules, which are initialization module, user interface module, instruction generation module, main control module and Data path module.

[0029] The AD / DA data acquisition and sending system in the RF automatic test platform targeted by the present invention requires at least 4 data paths that can work in parallel, so the controller is designed with 4 user interfaces for serving the front-end ADC / DAC memory access requests. When collecting work, each AD occupies a user interface to achieve parallel access to the memory. AD collection is a continuous data stream, and the data is stored in a continuous logical address space, and the priority of...

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Abstract

The invention discloses a DDR2-SDRAM controller used for a high-performance RF automatic testing platform, and a corresponding low latency optimization method. The DDR2-SDRAM controller is characterized in that firstly, an external storage module is not considered as a single resource; however, a storage space of a storage is divided into a plurality of independent logic resources according to rank and bank structures of a DRAM module; each resource belongs to a task with a fetching requirement, based on which, corresponding arbitration manner and instruction sequence are designed; secondly, a refreshing mechanism is improved and one refreshing period is arranged at the tail of 60 fetching instruction periods by the controller; an appointed rank in a storage array is refreshed through rank accessing to break up refreshing time into parts, so that the influence on access latency by the conflict of the fetching requirement and a refreshing request are reduced; and finally, the maximum fetching latency performance of each task of the system can be more greatly improved.

Description

technical field [0001] The invention relates to the field of automatic test platform design, in particular to the design of a DDR2-SDRAM storage controller, which is used to provide storage services for system memory access tasks. Background technique [0002] At present, the DDR2-SDRAM controller products launched by various companies are all oriented to general applications. However, in general applications, the bandwidth requirement of the storage controller is higher than the delay, so these controllers currently released mainly focus on the optimization of the storage bandwidth. In the RF automatic test platform, due to the limitation of the application occasion, the response and processing of the task have strict timing requirements, so the memory access delay of the memory controller is also important. [0003] With the wide application of RF automatic test platform, there is an urgent need for a memory controller designed for similar system application characteristi...

Claims

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Application Information

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IPC IPC(8): G06F12/02
Inventor 刘昊何雅乾黄成
Owner SOUTHEAST UNIV
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