Loosely-coupled Lockstep processor system

A processor system and processor technology, applied in the computer field, can solve problems such as synchronous comparison and monitoring of processor bus device interfaces, large limitations, and difficult expansion, and achieve high integrity and reliability, high integrity, and easy expansion Effect

Active Publication Date: 2015-04-01
AVIC NO 631 RES INST
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AI Technical Summary

Problems solved by technology

The current technology is difficult to realize the synchronous comparison and monitoring of the processor bus and the device interface; the fault detection rate is difficult to guarantee; Lockstep technology is a method to realize high-integrity computing, which detects faults in real time with a high probability and prevents faults from spreading , to ensure the high reliability of the system
The traditional Lockstep system is difficult to expand and has great limitations

Method used

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  • Loosely-coupled Lockstep processor system
  • Loosely-coupled Lockstep processor system
  • Loosely-coupled Lockstep processor system

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Embodiment Construction

[0018] The core part of the system of the present invention is to design resources such as PLB bus and synchronously coupled processors, memory interfaces, etc., and the remaining parts can be realized by general-purpose devices and circuits. The designed Lockstep system synchronizes, compares and detects faults in real time for all bus cycle operations and memory operations of the two processors through FPGA logic.

[0019] Real-time detection of system coupling by using bus lockstep and monitoring modules on the PLB bus to perform synchronous comparison of coupled dual-processor bus cycle operations (reading, writing, etc.), and synchronous comparison of reading and writing of coupled memory device interfaces Once an inconsistency is found in the working status of the resources, an interrupt signal is sent at the same time, and a fault indication signal is sent out to isolate the fault.

[0020] The composition of the Lockstep computer for bus monitoring is as attached figu...

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Abstract

The invention provides a loosely-coupled Lockstep processor system which comprises a processor with a 60x bus interface, a processor bus interface, a PLB, a DDR2 SDRAM storage interface and an asynchronous bus peripheral interface. The processor bus interface realizes timing conversion between the PLB and a 60X bus, the PLB is realized by an FPGA (field programmable gate array), the DDR2 SDRAM storage interface and an MIG interface in the FPGA realize access, of the PLB, to a synchronously-coupled DDR2, and the asynchronous bus peripheral interface accesses a coupled peripheral through the PLB. The bus synchronous comparing Lockstep processor system can realize realtime high-probability fault detection and isolation of a computer, DMA operation and slave equipment operation of the system can be guaranteed, the loosely-coupled Lockstep processor system has the advantages of expandability, convenience in realization and the like, and high reliability in data processing of the computer can be guaranteed.

Description

technical field [0001] The invention belongs to computer technology, and relates to a highly reliable bus and memory monitoring lockstep (Lockstep) computer system. Background technique [0002] The high fault detection rate of computer is very important for its application in safety-critical fields. The current technology is difficult to realize the synchronous comparison and monitoring of the processor bus and the device interface; the fault detection rate is difficult to guarantee; Lockstep technology is a method to realize high-integrity computing, which detects faults in real time with a high probability and prevents faults from spreading , to ensure the high reliability of the system. The traditional Lockstep system is difficult to expand and has great limitations. Contents of the invention [0003] In order to solve the technical problems existing in the background technology, the present invention provides a kind of Lockstep computer system of bus synchronous com...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38
CPCG06F11/008G06F13/4063
Inventor 周啸李鹏邓豹段小虎邹晨袁迹
Owner AVIC NO 631 RES INST
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