A ddr2-sdram controller and its low-latency optimization method

A technology of DDR2-SDRAM and controller, which is applied in the field of automatic test platform design to achieve the effect of improving real-time performance, avoiding address correlation, and reducing memory access delay

Active Publication Date: 2018-06-05
SOUTHEAST UNIV
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Problems solved by technology

In the RF automatic test platform, due to the limitation of the application occasion, the response and processing of the task have strict timing requirements, so the storage controller access delay is also important

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  • A ddr2-sdram controller and its low-latency optimization method
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  • A ddr2-sdram controller and its low-latency optimization method

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Embodiment Construction

[0027] The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0028] Such as figure 1 As shown, for the functions to be realized by the DDR2-SDRAM controller, using the concept of modularization, the control logic of the entire controller can be divided into 5 modules, which are initialization module, user interface module, instruction generation module, main control module and Data path module.

[0029] The AD / DA data acquisition and sending system in the RF automatic test platform targeted by the present invention requires at least 4 data paths that can work in parallel, so the controller is designed with 4 user interfaces for serving the front-end ADC / DAC memory access requests. When collecting work, each AD occupies a user interface to achieve parallel access to the memory. AD collection is a continuous data stream, and the data is stored in a continuous logical address space, and the priority of...

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Abstract

The invention discloses a DDR2-SDRAM controller and a corresponding low-delay optimization method for a high-performance RF automatic test platform. The DDR2-SDRAM controller is characterized in that, first, it does not regard the external storage module as a single resources, but according to the rank and bank structure of the DRAM module, the memory storage space is divided into several independent logical resources, each resource is private to a task with memory access requirements, and on this basis, the present invention designs corresponding Arbitration method and instruction sequence. The second is that it improves the refresh mechanism. The controller arranges a refresh cycle at the end of 60 memory access instruction cycles, and refreshes the specified row in the storage array through row access, which reduces the refresh time to zero and reduces memory access requests. The impact of conflicting with refresh requests on memory access latency. Ultimately, the maximum memory access latency performance of each task in the system is greatly improved.

Description

technical field [0001] The invention relates to the field of automatic test platform design, in particular to the design of a DDR2-SDRAM storage controller, which is used to provide storage services for system memory access tasks. Background technique [0002] At present, the DDR2-SDRAM controller products launched by various companies are all oriented to general applications. However, in general applications, the bandwidth requirement of the storage controller is higher than the delay, so these controllers currently released mainly focus on the optimization of the storage bandwidth. In the RF automatic test platform, due to the limitation of the application occasion, the response and processing of the task have strict timing requirements, so the memory access delay of the memory controller is also important. [0003] With the wide application of RF automatic test platform, there is an urgent need for a memory controller designed for similar system application characteristi...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/02
Inventor 刘昊何雅乾黄成
Owner SOUTHEAST UNIV
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