4results about How to "Improve memory access performance" patented technology

The invention relates to a memory access request control method, a cache, a computing device and a system, the method is applied to a memory access request control unit of the cache, and the method comprises the following steps: in a first clock period, aiming at at least one level of buffer area at the upstream of the memory access request control unit, determining a read request load and a write request load in each level of buffer area; according to the read request load and the write request load corresponding to each level of buffer area, determining the back pressure cycle number of the read request arriving at the first clock cycle; and when the waiting duration of the read request reaches the back pressure cycle number, receiving the read request.

The invention discloses a compression device, a chip, computer equipment and a compression method, and relates to the field of chips. The compression device comprises an arithmetic unit, a statistical unit and a generation unit, the arithmetic unit is connected with the statistical unit, and the statistical unit is connected with the generation unit. The arithmetic unit is used for executing operation on at least two memory access addresses in the memory access request to obtain an operation result, the operation result is used for indicating the interval between every two memory access addresses executed in sequence in the at least two memory access addresses, and the at least two memory access addresses respectively correspond to one cache line of the memory; the statistical unit is used for counting the operation result to obtain a statistical result, and the statistical result is used for indicating the condition that every two adjacent intervals in the intervals are equal; and the generation unit is used for generating at least one equidistant compression request based on the statistical result and the memory access request, and the equidistant compression request is used for indicating to sequentially execute read-write operation on at least two cache lines of the memory.

This invention discloses a data prefetching method, product, device, and medium based on multiple memory access patterns, relating to the field of computer architecture technology. The method includes: monitoring for L2 cache memory access miss events in the processor; if the miss status register hits the event, splitting the miss address to obtain the base address of the spatial region and the offset address within the region. When the program counter pattern training table hits the base address, stride and spatiotemporal pattern training is performed on the offset address to obtain a fixed stride, space / time related access pattern. Valid memory access patterns are filtered by confidence level and stored in the corresponding LLC pattern table, with an index recorded in the prefetch pattern record table. Subsequently, based on the memory access miss event and index information, the target pattern is read from the corresponding pattern table to calculate the prefetch address, generate a request, and execute the prefetch. Through this scheme, it is possible to adapt to multiple scenarios and accurately identify memory access patterns for more precise data prefetching.

The application provides a Cache write cache device and a control method thereof, and relates to the technical field of artificial intelligence chips. The device comprises: a write cache table for storing a plurality of write cache entries, each write cache entry corresponding to attribute information of a Cache line; a memory for storing data of the Cache line corresponding to each write cache entry; a write cache control unit for processing storage requests and loading requests based on the write cache table, and for writing the data of the Cache line corresponding to the write cache entry from the memory to a data storage unit when a preset write-back condition is met; a loading request queue for buffering loading request information from a previous execution unit or a previous Cache; and an effective address generation module for generating a corresponding effective write-back address according to a write data effective flag signal recorded in the write cache entry when performing a write-back operation. The application effectively reduces the write-back pressure on the lower-level storage, eliminates the structural blockage of the storage backend to the computing frontend, and significantly improves the overall memory access efficiency and computing throughput.