Access-memory control device and method of memorizer, processor and north-bridge chip

Abstract

Provided are an access-memory control device and method of a memorizer, a processor and a north-bridge chip. The access-memory control device of the memorizer comprises an analysis requesting unit for accessing and analyzing a request to form an operation command sequence including a plurality of operation commands, and an arbitration unit for performing arbitration of the operation commands in the operation command sequence according to arbitration conditions so as to send the operation commands to the memorizer. Compared with the prior art, the access-memory control device concurrently sends the operation command sequence through the analysis requesting unit and utilizes first temporal constraint, second temporal constraint and third temporal constraint to control a time interval from the sending time of an existing operation command to the sending time of a previous operation command adjacent to the existing operation command in the same operation command sequence, and concurrent accessing of multiple memorizers can be performed. In addition, multiple memorizer groups can be concurrently accessed, multi-dimensional concurrent accessing is achieved, the average handling time of request accessing and memorizing is remarkably shortened, and the overall access-memory performance of a system is improved.

Description

technical field [0001] The invention relates to the field of computer memory control, in particular to a memory access control device and method, a processor and a north bridge chip of the memory. Background technique [0002] Memory is an important factor affecting the overall performance of the computer system, and the improvement of its data transfer rate has a positive effect on improving the performance of the processor. Processor speed doubles approximately every 18 months, while memory speed doubles approximately every 10 years, so processor and memory performance improvements are not synchronized. With the progress of the technological level, the speed of the processor has far exceeded the speed of the memory, resulting in the bottleneck of the "storage wall". [0003] In order to alleviate the technical bottleneck caused by the "memory wall", memory manufacturers have adopted many new memory architectures. Taking DRAM (Dynamic Random Access Memory, DRAM) as an exa...

AI Technical Summary

Problems solved by technology

The above device arbitrates the data read and write requests of the client module according to the requirements of the decoding pipeline architecture, controls the data read and write access operations, and utilizes the data bandwidth of the memory more likely. However, the improvement of the memory access efficiency of the system is limited and still Did not solve the above technical problems

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