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Method of managing register file units

A register file and register technology, applied in register devices, machine execution devices, etc., can solve problems such as performance loss, unbearable cost and complexity of implementation

Active Publication Date: 2020-07-28
SHANGHAI DENGLIN TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The implementation cost and complexity of this multi-port SRAM design will be unbearable, and if multiple cycles are used to complete the write-back operation, it will cause performance loss

Method used

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  • Method of managing register file units

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Embodiment Construction

[0042] In order to make the purpose, technical solution, design method and advantages of the present invention clearer, the present invention will be further described in detail through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0043] In all examples shown and discussed herein, any specific values ​​should be construed as exemplary only, and not as limitations. Therefore, other instances of the exemplary embodiment may have different values.

[0044] Techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods and devices should be considered part of the description.

[0045] The following will take the GPGPU processor as an example to introduce the structure and scheduling strategy of the regist...

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Abstract

The invention provides a method for managing register file units. The register file unit is composed of a single-port memory, the single-port memory is a register used for providing operands associated with threads, and the method comprises: allocating associated registers to a plurality of threads, and organizing the allocated registers into a plurality of register groups; uniformly distributingregisters associated with each thread in a plurality of register groups, wherein associated data of different threads is stored at the same position of the plurality of register groups; and for the read-write operation of the register, scheduling the arrangement mode of operands associated with a plurality of threads, so that a plurality of register groups of the register file unit only have one read operation or one write operation in the same clock period. By utilizing the method provided by the invention, the function of the multi-port memory can be simulated by using single-port storage, so that the design cost of the register file unit is reduced, and the memory access performance is improved.

Description

technical field [0001] The invention relates to the field of processor design, in particular to a method for managing register file units. Background technique [0002] The register file unit (Register File), also known as the register file, is an array composed of multiple registers in processors such as CPU or GPU, which can be implemented by flip-flops or static random access memory (SRAM). [0003] General-Purpose Graphic Processing Unit (GPGPU) is a massively parallel processor that has been successfully applied in the field of high-performance computing with significant thread parallelism, and each clock cycle can process multiple threads simultaneously. In this parallel processing, each thread independently processes different data sets, and these data and intermediate operation results need to be temporarily stored in the on-chip register file unit. Due to the large number of supported threads and the large number of registers required by each thread, GPGPU uses sta...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30
CPCG06F9/30141
Inventor 王刚王震宇王平李晶晶
Owner SHANGHAI DENGLIN TECH CO LTD
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