Novel STT-MRAM cache design method

Abstract

A novel STT-MRAM cache design method includes the three major steps. The relation among the size of MTJ, write currents and write energy consumption is utilized, a novel STT-MRAM cache structure is designed, and an L1Cache and an L2Cache are achieved through MTJ memory units with different sizes respectively. Compared with the mode that MTJ memory units only with the same size are used, write energy consumption is reduced, and performance is improved. Compared with the structure that an SRAM and an STT-MRAM are mixed, static power consumption is remarkably reduced. Due to the fact that the L1Cache is composed of the MTJ memory units with the small size, the L1Cache is smaller in size and higher in memory density, the miss rate of the Cache is remarkably lower than that of an SRAM Cache, and the memory access performance is improved. In addition, only the STT-MRAM production process is adopted, the yield of chips is increased, and production cost is reduced.

Description

technical field [0001] The present invention uses STT-MRAM storage devices to replace traditional SRAM devices as the cache memory of the chip, and proposes a novel STT-MRAM cache (Cache) design method, which reduces chip power consumption and improves chip performance. The invention belongs to the technical field of nonvolatile memory design. Background technique [0002] With the continuous improvement of on-chip transistor integration density, multi-core processors have begun to be widely used. For example, IBM Power7, Intel's Core series processors and Tilera's Tile-GX series processors. Although the multi-core processor greatly improves the performance of the computer, it needs the support of large-capacity on-chip cache to solve the "memory wall" bottleneck. At present, random static memory (SRAM) is generally used as an on-chip cache (Cache) in the industry. To reduce processor power consumption, the on-chip supply voltage is continuously reduced. The subthreshold...

AI Technical Summary

Problems solved by technology

[0009] First, the production processes of SRAM and STT-MRAM are different, and integrating them on the same chip will reduce the chip yield and increase production costs;

[0010] Second, the existence of SRAM will increase the static power consumption of the chip;

[0011] Third, how to determine the respective capacities of STT-MRAM and SRAM is also a difficult problem to solve, because different applications and programs have different memory access behaviors, so it is difficult to have a universally effective solution

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