DDR4 performance balance scheduling structure and method for multiple request sources

A scheduling method and multi-request technology, applied in resource allocation, multi-program device, program startup/switching, etc., can solve problems such as unfavorable chip overall performance and insufficient consideration of source characteristics, so as to reduce the impact of memory access delay and improve Memory access bandwidth and the effect of improving comprehensive memory access performance

Inactive Publication Date: 2020-01-21
JIANGNAN INST OF COMPUTING TECH
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Problems solved by technology

However, the traditional scheduling mechanism does not consider the source characteristics enough. Although it can maximize bandwidth utilization, it is not conducive to the overall performance of the chip.

Method used

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  • DDR4 performance balance scheduling structure and method for multiple request sources

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Embodiment 2

[0050] In the second embodiment, on the basis of the first embodiment, the memory access request scheduling buffer includes a bandwidth-sensitive memory access scheduling buffer and a delay-sensitive memory access scheduling buffer.

[0051] Among them, the bandwidth-sensitive memory access scheduling buffer includes

[0052] Storage entry, used to record the information of the fetch request. The information of the fetch request includes the fetch request information, the left sub-pointer of the entry, and the right sub-pointer of the entry

[0053] Empty entry queue, used to mount storage entries in the form of a queue.

[0054] The scheduling binary tree is used to organize storage entries in the form of a binary tree.

[0055] First, each storage entry in the bandwidth-sensitive memory fetch scheduling buffer includes three pieces of information: fetch request information, the left sub-pointer of the entry, and the right sub-pointer of the entry. These storage entries are organized...

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Abstract

The invention relates to the technical field of computer system structures and processor microstructures, in particular to a DDR4 performance balance scheduling structure and method for multiple request sources. A DDR4 performance balance scheduling structure for multiple request sources comprises a plurality of memory access request scheduling buffers used for improving memory access bandwidths corresponding to the memory access request sources; a multi-source continuous arbitration component used for selecting one memory access request to be transmitted; and a DDR4 storage device used forreceiving the memory access request transmitted by the multi-source continuous arbitration component. The invention discloses a DDR4 performance balance scheduling method for multiple request sources.The DDR4 performance balance scheduling method comprises the following steps: L1, setting a memory access request scheduling buffer for a memory access request of each memory access request source; and L2, enabling the multi-source continuous arbitration component to select one memory access request to transmit through an arbitration strategy. A plurality of memory access request scheduling buffers are respectively set for multiple request sources, so that the influence on memory access delay can be reduced while the memory access bandwidth is improved, and the comprehensive memory access performance of a system is improved.

Description

Technical field [0001] The invention relates to the technical field of computer architecture and processor microstructures, in particular to a DDR4 performance balance scheduling structure and method for multiple request sources. Background technique [0002] With the continuous progress of processor manufacturing technology and practical application needs, many-core architecture has become the current development trend of high-performance microprocessors. The memory access bandwidth and memory access latency of many-core processor systems cannot match the "memory wall" of computing performance. "The problem is a hot topic in today's computer architecture. [0003] In order to increase memory access bandwidth, many-core processors will use large-scale memory access request scheduling buffers. However, large-scale memory access scheduling buffers will greatly increase memory access latency. For multi-source memory access request sequences, some sources require higher memory access...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/48G06F9/50
CPCG06F9/4881G06F9/5016
Inventor 吕晖石嵩刘骁吴铁彬赵冠一王迪王吉军
Owner JIANGNAN INST OF COMPUTING TECH
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