Combination system of computing chip and memory chip based on high-speed serial channel interconnection

Abstract

The invention relates to the field of computer system structure and integrated circuit design, a system for combining a computing chip and a memory chip base on high speed serial channel interconnection is disclosed, includes a plurality of computing chips and a plurality of memory chipsets, a memory chipset includes a plurality of memory chips, the system architecture based on the algorithm dataflow graph mapping divides the computational chip into n groups of computational chip sets, each computing chipset comprises a plurality of computing chips, and a plurality of memory chipsets are arranged between the computing chipsets requiring data sharing and exchange. The computing chips in the computing chipset are connected with all adjacent memory chipsets through a plurality of high-speedserial channels. The computing chips in the computing chipsets are connected with all adjacent memory chipsets through a plurality of high-speed serial channels. A system for combine computing chip and memory chip base on high-speed serial channel interconnection can flexibly increase that number of high-speed serial channels to increase the memory access bandwidth accord to requirements, the overall system structure is flexible in design, effectively adapts to the scene of computing inter-chip streaming data processing, and the storage cost is low.

Description

technical field [0001] The invention relates to the field of computer system structure and integrated circuit design, in particular to a combination system of computing chips and memory chips based on high-speed serial channel interconnection. Background technique [0002] Among various types of algorithms, a large number of algorithms are memory-intensive algorithms, that is, memory access operations account for a higher proportion in the algorithm execution process, and the memory access performance largely determines the runtime performance of the algorithm. Especially for algorithms with irregular memory access patterns, that is, algorithms with poor locality of memory access, Cache (high-speed cache) cannot effectively accelerate the algorithm execution process. In this case, memory access bandwidth and latency play a decisive role in the runtime performance of the algorithm. [0003] At present, in order to improve the performance of the storage system, the industry h...

AI Technical Summary

Problems solved by technology

First, the bandwidth improvement of these storage technologies is limited. They use a multi-bit parallel interface bus. The main way to further increase the bandwidth is to use a wider interface bus or increase the interface rate, but the multi-bit parallel bonded transmission requires signal integrity. It is becoming more and more difficult to implement higher, wider and higher-speed interfaces; if the main processor wants to further increase the memory access bandwidth, it must integrate more memory access interfaces, which are limited by the chip size and the number of pins, and the wide bus type It is difficult to greatly increase the number of integrated memory access interfaces

Second, the implementation cost of new storage technology is relatively high. For example, the engineering cost of advanced HBM technology is as high as tens of millions of dollars.

The third is that the above-mentioned new storage technologies do not have a sharing mode, or the sharing granularity is very low. For example, DDR4 / DDR5, GDDR5, and HBM storage media can only be accessed by the main control chip directly connected to them, and cannot realize multiple storage. Direct shared access of multiple main control chips; although HMC can connect multiple main control chips, it does not support the shared use of more than four main control chips

The weak shared use characteristics of the above-mentioned various new storage technologies make the cost of adopting new storage higher to a certain extent

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