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Multi-core multi-thread microprocessor-oriented virtual active page buffer method and device

A microprocessor and multi-threading technology, applied in machine execution devices, electrical digital data processing, instruments, etc., can solve problems such as frequent opening and closing of active pages, frequent physical active pages, and impact on memory access bandwidth, and achieve a breakthrough in access storage bandwidth, balance multi-body load, and improve service time

Active Publication Date: 2014-07-30
NAT UNIV OF DEFENSE TECH
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Break through the bottleneck of traditional off-chip storage bandwidth optimization methods in multi-core multi-thread processors, and solve the problem of frequent opening and closing of active pages in SDRAM caused by the small correlation of address flows between threads in multi-core multi-thread processors. The problem of limited actual effective bandwidth optimization space
For multi-core multi-thread processors, the correlation between address streams is small. When the number of threads is large, multi-base address streams access external memory concurrently, resulting in frequent opening and closing of physical active pages of external memory. The request interval time when accessing different pages is 10 times the request interval time when accessing the same page, so the page switching between consecutive accesses seriously affects the memory access bandwidth, so there is a cost of low memory access performance and activation after the active page is closed higher disadvantage

Method used

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  • Multi-core multi-thread microprocessor-oriented virtual active page buffer method and device
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Embodiment Construction

[0042] Such as figure 1 , figure 2 with image 3 As shown, the implementation steps of the virtual active page buffer method for multi-core multi-threaded microprocessors in this embodiment are as follows:

[0043] 1) Build a virtual active page buffer (Virtual Open Page Buffer, referred to as VOP buffer) between the on-chip memory access part of the processor and the memory controller, obtain the memory access request from the on-chip memory access part of the processor and judge the access The type of storage request, if the storage request is a read request, then jump to step 2); if the storage request is a prefetch read request, then jump to step 4); if the storage request is a write request, then jump Execute step 7);

[0044] 2) According to the request address of the memory access request and the request address of the historical memory access request, it is judged whether the memory access mode of the memory access request conforms to the preset rule access charact...

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Abstract

The invention discloses a multi-core multi-thread microprocessor-oriented virtual active page buffer method and device. The method comprises the following steps of: constructing a virtual active page buffer; managing construction, memory and deletion of a virtual active page in the virtual active page buffer according to an access memory request of an on-chip access memory component of a processor; and directly reading the virtual active page from the virtual active page buffer to improve the access memory performance when the access memory request is a read request and hit occurs in the virtual active page buffer. The device comprises a page predictor (1), an arbitrator (2), a virtual active page mark array (3), a virtual active page data array (4), a read-write queue (5), a command queue (6), a data return queue (7), a pending table (8) and a multi-path selector (9). According to the method and the device, the integral active page number of the memory can be increased, the cost for re-excitation after closing of the active page is reduced, and the access memory bandwidth is increased; and the method and the device have the advantages of high access memory performance and high extensibility.

Description

technical field [0001] The invention relates to the technical field of off-chip storage bandwidth optimization in the architecture design of multi-core multi-thread microprocessors, in particular to a method for virtual active page buffering for multi-core multi-thread microprocessors when the number of processor threads is large and devices. Background technique [0002] The mainstream off-chip memory uses DDR2 and DDR3 memory (hereinafter collectively referred to as DDR), which are all based on SDRAM. DDR SDRAM is a four-dimensional storage structure indexed by rank, bank, row and column. The memory controller generally transmits memory access instructions to SDRAM in the order of first-in-first-out. This method of scheduling according to program order is simple to implement, but due to memory bank competition, continuous access to the same memory bank must wait for the previous access to complete. Memory bandwidth utilization is low. [0003] The active page in the SDR...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/08G06F9/38G06F12/0882G06F12/0895
Inventor 窦强周宏伟邓让钰晏小波李永进衣晓飞张英曾坤谢伦国唐遇星
Owner NAT UNIV OF DEFENSE TECH
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