43 results about "Partial word" patented technology

A text input method is described for an electronic apparatus having a user interface with a touch-sensitive display screen. A virtual keyboard is presentable on the display screen so as to facilitate text input for a user by pointing at different virtual keys of the virtual keyboard. Word completion functionality is provided for predicting full word candidates for partial word inputs made by the user on the virtual keyboard. The method involves receiving a partial word input from said user and deriving a set of full word candidates using the word completion functionality, each of the full word candidates in said set having a prefix and a suffix, wherein the prefix corresponds to said partial word input. The suffices for at least a sub set of the full word candidates are presented in a predetermined area on the display screen, wherein each of the presented suffices is made selectable for the user.

Virtual keyboards become efficient and ergonomic by typing with small, incremental partial word completions, using fewest but largest possible keys, presented in highly condensed layouts, retaining familiar structural patterns of standard keyboards like QWERTY, and utilizing curved thumb typing formats. The keyboard continuously adjusts numbers of keys, key sizes, predictive values and layouts, to minimize keystrokes, reduce errors, and maximize potential words entered, while providing the most ergonomic, minimalist interface possible at any moment, scaling to any size device. Keys display normal default characters concatenated with supplemental predictive characters, forming incremental partial word completions; each represents the longest common building block shortcut of likely intended words derivable from a key's default value. The most relevant keys can generate larger numbers of highly predicted words; the more relevant, the larger the key. Only the most relevant keys are displayed, in stripped down, but familiar layouts, allowing only valid text entry options.

Cyclic redundancy checking operations may be performed on a message made up of full words and a partial word. An accumulator value for the cyclic redundancy checking operations may be updated as the full words and partial word are processed. The partial word may be padded with pad bits. The effects of the partial word padding can be removed by performing polynomial division on the accumulator. Polynomial division may be performed using an arrangement where each polynomial division involves half as many bits as its predecessor. Iterative division schemes in which a fixed number of bits are processed in multiple passes may also be used. Hybrid arrangements involving cascaded divisions of different orders and iterative fixed-size division can be used. Unpadded partial words may also be processed using cascaded, iterative, and hybrid schemes.

A decoder for a non-volatile semiconductor memory device includes a level shifter configured to generate a negative first voltage at an output thereof responsive to a first state of a global word line and to generate a second voltage more positive than the first voltage responsive to a second state of the global word line. The decoder further includes a local word line driver having an input coupled to the output of the level shifter and configured to apply a voltage on a partial word line to a local word line when the output of the level shifter is at the first voltage and to apply the first voltage to the local word line when the output of the level shifter is at the second voltage.

A method for text prediction for cell phone text messaging or for other applications. The preferred embodiment for predictive text involves the use of weighted positional digrams and a partial word dataset as well as optional elements involving three different types of voice recognition. Alternative embodiments involve the use of trigrams and quadgrams. The use of this text prediction system for a crossword game application is also described.

A given data packet is parsed into words and a final partial word that are processed (depending on size) in each of multiple successive stages of logic circuitry. Similarly sized words are processed at one stage of the logic circuit. Smaller and smaller modulo-2 components of the final partial word are processed at successive stages of logic circuitry. Based on this technique of processing modulo-2 components in different stages, the corresponding multi-stage logic circuit can be implemented in a low cost logic circuit such as an FPGA device instead of a custom-masked ASIC.

A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform a partial word write operation in which an error correction code encode process for the given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word. If the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word. The error correction code decode process and an associated correct process are thereby removed from a critical timing path of the partial word write operation.

Scalable and unified multipliers for multiplication of cryptographic parameters represented as elements of either of the prime field (GF(p)) and the binary extension field (GF(2^m)) include processing elements arranged to execute in pipeline stages. The processing elements are configurable to perform operations corresponding to either the prime field or the binary extension field. In an example, the processing elements include a dual-field adder having a field-select input that permits selection of a field arithmetic. In a representative example, multipliers are implemented as integrated circuits having processing units that each receive a single bit of one operand and partial words of the remaining operand.

A semiconductor integrated circuit device for speech recognition includes a conversion candidate setting unit that receives text data indicating words or sentences together with a command and sets the text data in a conversion list in accordance with the command; a standard pattern extracting unit that extracts, from a speech recognition database, a standard pattern corresponding to at least a part of the words or sentences indicated by the text data that is set in the conversion list; a signal processing unit that extracts frequency components of an input speech signal and generates a feature pattern indicating distribution of the frequency components; and a match detecting unit that detects a match between the feature pattern generated from at least a part of the speech signal and the standard pattern and outputs a speech recognition result.

Various enhancements may be made to a DMA controller (34) to optimize the DMA controller (34) for use in non-uniform DMA applications such as Universal Serial Bus (USB) applications. First, a DMA count register (54) that is used to store a count value that controls the length of a data transfer over a DMA channel (24) may be capable of being selectively disabled, such that when the DMA count register (54) is disabled, a DMA control circuit (38) may perform a data transfer independent of the DMA count register (54). An endpoint watchdog timer (40) may also be coupled to a DMA control circuit (38) and configured to generate an interrupt if no data is received by the DMA channel (24) within a predetermined period of time. In addition, a DMA control circuit (38) may incorporate partial word hold off functionality to delay transmission of a final word of data from a data packet if the final word is a partial word. FUrthermore, a USB profile circuit (26) may be coupled to the DMA control circuit (38) and configured to control at least one operational parameter of the DMA control circuit (38) to selectively optimize the DMA control circuit (38) for use with a selected USB protocol among a plurality of USB protocols supported by the USB profile circuit (26).

The present invention discloses converting a text form into a speech. In the present invention, partial word lists of a data source are obtained by parsing the data source in parallel or in series. The partial word lists are then compiled to obtain phoneme graphs corresponding, respectively, to the partial word lists, and then the obtained phoneme graphs are combined. Speech recognition is then conducted according to the combination results. According to the present invention, computational complexity may be reduced and recognition efficiency may be improved during speech recognition.

The invention relates to a machine translation test method. According to the method, a dependency syntax tree is constructed for sentences, pruning is performed on the syntax tree according to a specific rule, validity of the sentences is destroyed based on a group of deletion operators of a dependency syntax tree level, and words or phrases are deleted from the original sentences to generate new sentences with effective grammar and semantics. And inputting the original text and the newly generated sentences into a tested machine translation system, calculating bag-of-word distances, sequencing and amplifying the sentences according to the bag-of-word distances, selecting five sentences with the largest distance, manually labeling the original sentence and the translated sentence results, marking wrong sentences, and completing the test of the machine translation system. The invention aims to solve the problem that the test performance is mainly limited by the maturity of an adopted language model due to the fact that a test case is mainly generated by replacing a part of words in a sentence in the current machine translation test. When the data is amplified, the invariance of the basic structure of the sentence is ensured, so that more pairs of errors are found, and most of the errors cannot be found by a previous machine translation test technology.

A decoder for a nonvolatile memory device includes a level shifter configured to produce a first voltage at an output thereof responsive to a first state of a global word line and to produce a second voltage at the output responsive to a second state of the global word line. The decoder further includes a plurality of local word line drivers, each having an input coupled to the output of the level shifter, the respective local word line drivers configured to drive respective local word lines responsive to voltages on respective partial word lines when the output of the level shifter is at the first voltage and to drive the respective local word lines to a common voltage when the output of the level shifter is at the second voltage. The first state of the global word line may generate a third voltage at an input of the level shifter, the second state of the global word line may generate a fourth voltage at the input of the level shifter, and the first and second voltages may have opposite polarities.

Full-duplex memory access systems and methods for improved quality of service (QoS) are disclosed. In one aspect, a primary bus owner will evaluate an output from a secondary bus owner when the primary bus owner takes control of the bus to determine if the secondary bus owner has data to send to the primary bus owner and/or is in the midst of a bulk data transfer. If the evaluation determines that there is still data to be transferred, the primary bus owner may refrain from draining an internal register unless a full word is present in the register. By reducing memory access for a partial word in the register, QoS may be improved.