Circuit structure and method for transmitting data in DMA passage by DMA control circuit

Abstract

Various enhancements may be made to a DMA controller (34) to optimize the DMA controller (34) for use in non-uniform DMA applications such as Universal Serial Bus (USB) applications. First, a DMA count register (54) that is used to store a count value that controls the length of a data transfer over a DMA channel (24) may be capable of being selectively disabled, such that when the DMA count register (54) is disabled, a DMA control circuit (38) may perform a data transfer independent of the DMA count register (54). An endpoint watchdog timer (40) may also be coupled to a DMA control circuit (38) and configured to generate an interrupt if no data is received by the DMA channel (24) within a predetermined period of time. In addition, a DMA control circuit (38) may incorporate partial word hold off functionality to delay transmission of a final word of data from a data packet if the final word is a partial word. FUrthermore, a USB profile circuit (26) may be coupled to the DMA control circuit (38) and configured to control at least one operational parameter of the DMA control circuit (38) to selectively optimize the DMA control circuit (38) for use with a selected USB protocol among a plurality of USB protocols supported by the USB profile circuit (26).

Description

technical field [0001] The present invention relates generally to memory access and transfers, and more particularly to direct memory access (DMA) controllers. Background technique [0002] Data transmission within a computer or other electronic system is often an integral factor in the performance of such systems. No matter how fast a computer or electronic device's central processing unit (CPU) can process data, if data cannot be communicated to or from the CPU in a fast enough manner, system performance is bound to suffer. [0003] One technique that has been used to improve data transfer performance is called direct memory access (DMA). DMA uses a dedicated controller or circuitry to handle data transfers independently of the CPU, freeing the CPU to handle other tasks during data transfer operations. Typically, DMA is used to transfer data between memory and peripherals or input / output (I / O) devices such as expansion cards, network ports, storage devices, and the like....

AI Technical Summary

Problems solved by technology

However, by doing so, the amount of supervision required by the CPU often increases, reducing system performance

[0012] Second, many CPUs are too slow to intervene in certain USB-related DMA transfers

As a result, many CPUs cannot reliably intervene in high-bandwidth isochronous transfers

[0013] Third, modern bus structures are often capable of corrupting DMA data content associated with USB

As a result, if the number of bytes received in a packet is not a multiple of the bus word size, a conventional DMA controller performs the transfer of the last byte with only partially valid data

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