Decoders and decoding methods for nonvolatile memory devices using level shifting

A non-volatile, decoder technology, applied in the field of decoders, can solve the problem of increasing the size of the decoder structure

Active Publication Date: 2008-05-07
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

NMOS transistors NM64 and NM66 and complementary partial wordlines nPWL-nPWL that prevent non-selected partial wor

Method used

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  • Decoders and decoding methods for nonvolatile memory devices using level shifting
  • Decoders and decoding methods for nonvolatile memory devices using level shifting
  • Decoders and decoding methods for nonvolatile memory devices using level shifting

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Embodiment Construction

[0031] Hereinafter, the present invention will be described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0032] In the drawings, the size or arrangement of elements may be idealized or exaggerated for clarity. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Like reference numerals refer to ...

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Abstract

A decoder for a nonvolatile memory device includes a level shifter configured to produce a first voltage at an output thereof responsive to a first state of a global word line and to produce a second voltage at the output responsive to a second state of the global word line. The decoder further includes a plurality of local word line drivers, each having an input coupled to the output of the level shifter, the respective local word line drivers configured to drive respective local word lines responsive to voltages on respective partial word lines when the output of the level shifter is at the first voltage and to drive the respective local word lines to a common voltage when the output of the level shifter is at the second voltage. The first state of the global word line may generate a third voltage at an input of the level shifter, the second state of the global word line may generate a fourth voltage at the input of the level shifter, and the first and second voltages may have opposite polarities.

Description

[0001] Comparison of related applications [0002] This application claims priority from Korean Patent Application No. 10-2006-0107554 filed on November 2, 2006, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0003] The present invention relates to non-volatile memory devices, and more particularly, to decoders for non-volatile memory devices. Background technique [0004] Flash memory devices are typically electrically erasable and / or programmable, and are often used for relatively large units of data storage. For example, flash memory is widely used to store the basic input output system (BIOS) somewhere in a hard disk, to store communication protocols in mobile phones, as image memory in digital cameras, and for other storage applications. [0005] NOR-type flash memory devices typically have considerable program and read speeds compared to other types of non-volatile memory devices. A typical NOR-type flash memory device ...

Claims

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Application Information

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IPC IPC(8): G11C16/08
CPCG11C8/10G11C16/08G11C16/10G11C16/26G11C16/30
Inventor 赵志虎
Owner SAMSUNG ELECTRONICS CO LTD
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