Sparse neural network-oriented system on chip

Abstract

The invention discloses a sparse neural network-oriented system on chip, which comprises a main processor, a co-processor, system slave equipment and an off-chip memory, the main processor is in communication connection with the main processor; the system slave equipment is in communication connection with the main processor; the slave system interface of the off-chip memory is in communication connection with the slave system; the main processor decomposes matrix calculation in a neural network algorithm into vector calculation, executes a program to screen and recombine sparse vectors participating in calculation in a sparse neural network, converts the sparse vectors in the sparse neural network into dense vectors, and sends an acceleration instruction to the co-processor. Accelerated computation of dense vectors is performed by the co-processor. According to the invention, the problems that the accelerator parallelism and the memory access efficiency are limited and the utilization efficiency of a processor in the system is low are solved. For the direct index storage of the sparse neural network, the problem of difficult data reuse in the accelerator caused by nonzero element position uncertainty in the sparse neural network is solved.

Description

technical field [0001] The invention relates to the communication field, in particular to a system on chip oriented to a sparse neural network. Background technique [0002] The sparseness of the neural network greatly reduces the amount of calculation and data storage of the algorithm, which helps to deploy large-scale neural network algorithms in embedded devices with limited storage, computing resources and energy consumption. However, the data irregularity caused by sparseness makes the execution efficiency of sparse networks on general platforms very low. In order to make hardware perform sparse neural network algorithms better, researchers have designed a variety of sparse neural network accelerators. In addition, the research on SoCs for sparse neural networks has gradually begun. [0003] There are several problems with existing sparse neural network accelerators and SoCs: [0004] a. The calculation parallelism and memory access efficiency of the accelerator are l...

AI Technical Summary

Problems solved by technology

[0005] b. Uncertainty in the position of non-zero elements in the sparse network leads to difficulties in data reuse in the accelerator;

[0006] c. It is necessary to design a special compiler for the accelerator, and the versatility is poor

[0007] In the system on chip, the utilization rate of the CPU is too low, and the overall acceleration effect of the system is mediocre.

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