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Memory access processing method and device

A memory access and processing method technology, applied in the field of memory access processing methods and devices, can solve the problems of reduced memory access performance and high occupancy rate, and achieve the effects of reducing the probability of occurrence of exceptions, reducing occupancy rate, and improving memory access performance

Active Publication Date: 2017-01-11
ZTE CORP
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  • Claims
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Problems solved by technology

In this way, in actual operation, a large number of TLB miss exceptions will inevitably occur, so it is necessary to continuously load new TLB entries from the page table to complete virtual and real address translation, resulting in reduced memory access performance and CPU usage. higher rate

Method used

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  • Memory access processing method and device

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Embodiment Construction

[0045] It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0046] The present invention provides a memory access processing method, referring to figure 1 , in the first embodiment of the memory access processing method of the present invention, the memory access processing method includes the following steps:

[0047] Step S10, dividing the memory area into a low-end area and a high-end area according to preset rules;

[0048] The memory access processing method provided by the embodiment of the present invention is mainly applied in a computer system to control memory address access. Specifically, the above-mentioned memory division method can be set according to actual needs. In a LINUX system, it is usually divided into a low-end area (LOW area) and a high-end area (HIGH area) according to addresses. For example, when the system memory is initialized, a part of the prese...

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Abstract

The invention discloses a memory access processing method. The memory access processing method comprises the following steps: partitioning a memory area into a low area and a high area according to a preset rule; building a fixed translation lookaside buffer (TLB) mapping entry corresponding to the low area and a dynamic TLB mapping entry corresponding to the high area in a TLB table entry, wherein the dynamic TLB mapping entry is used for replacing a mapping relationship according to a preset page table; and when a memory access request of a preset interface function is received, accessing a memory address of the low area according to the fixed TLB mapping entry, and accessing a memory address of the high area according to the dynamic TLB mapping entry. The invention also discloses a memory access processing device. Through adoption of the memory access processing method and device, the memory access performance of a system is enhanced, and the occupancy rate of a CPU (Central Processing Unit) is reduced.

Description

technical field [0001] The invention relates to the field of computer technology, in particular to a memory access processing method and device. Background technique [0002] As we all know, in a 64-bit computer system, the memory supported by the CPU can theoretically reach a maximum size of 2^64, but there are relatively few TLB (Translation Lookaside Buffer) mapping entries as the actual page table cache. Therefore, when the kernel accesses the physical address of the entire memory area, because different modules have different memory requirements, the address access will be randomly distributed in the entire memory space. In this way, in actual operation, a large number of TLB miss exceptions will inevitably occur, so it is necessary to continuously load new TLB entries from the page table to complete virtual and real address translation, resulting in reduced memory access performance and CPU usage. The rate is higher. [0003] The above content is only used to assist ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/12
CPCG06F12/12
Inventor 武八一刘强
Owner ZTE CORP
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