RISC-V vector memory access processing system and processing method

Abstract

The invention discloses an RISC-V vector memory access processing system and method, and the system comprises a scalar-vector dispatching unit, a scalar-vector instruction lag monitoring unit and a scalar-vector memory access unit which can transmit data mutually, and a decoding unit and a system state register which are connected with the scalar-vector dispatching unit. The decoding unit is also connected with an instruction memory, a vector register and a scalar register; the scalar-vector access unit is connected with a data bus and a vector write-back arbitration unit, and the vector write-back arbitration unit is also connected with the vector register and the scalar register. On the basis of an existing scalar processing system, only a small number of hardware function units are added, the memory access capacity of the scalar processor for the vector data is improved, the invalid dispatching-logout time of the processor is shortened, and the processing efficiency of the scalar processor for the vector data is greatly improved.

Description

technical field [0001] The invention belongs to the technical field of processor hardware, and in particular relates to a RISC-V vector memory access processing system and processing method. Background technique [0002] With the rapid development of artificial intelligence and big data today, the scalar processor inside the embedded chip usually needs to perform real-time and adaptive processing on digital signals such as images and audio. The efficiency of parallel processing of big data directly determines the overall performance of the chip. Such tasks usually tend to be computationally intensive, and the performance of traditional general-purpose scalar processors is difficult to meet the needs of real-time vector computing. [0003] At present, the commercial vector processors started late. In order to improve the performance of the processors, the data bus width and data interface protocols are selected from the most cutting-edge standards, which makes this type of ve...

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Problems solved by technology

As a result, benefiting from the simplification of the RISC-V vector instruction set design, the memory access logic required by the RISC-V processor to expand the vector path can be implemented more simply and efficiently, but currently the extension in the scalar processor is for the RISC-V vector There is no general implementation scheme for the support of memory access instructions

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