172 results about "Data layout" patented technology

The present invention discloses an artificial intelligence-based adaptive big data storage and retrieval optimization system and method designed to intelligently manage and optimize large-scale distributed data environments. The system integrates data acquisition, distributed storage, metadata processing, adaptive learning, and retrieval optimization units configured to work collaboratively for continuous self-optimization. The invention employs deep reinforcement learning and predictive neural network techniques to dynamically analyze system telemetry, workload behavior, and data access patterns in real time, enabling proactive adjustment of data placement, caching, replication, and compression parameters across distributed nodes. The metadata processing framework utilizes graph-based dependency modeling to maintain semantic and contextual relationships among datasets, facilitating intelligent and context-aware data retrieval. The retrieval optimization unit interprets user queries semantically and computes the optimal retrieval route using latency prediction models and dynamic routing techniques.

The invention relates to the technical field of data processing, in particular to a load awareness and data dynamic layout method and system based on deep learning, and the method comprises the steps: collecting hardware load indexes of all nodes in a distributed cluster in real time, and carrying out the preprocessing of the hardware load indexes; based on the preprocessed hardware load index, calculating a comprehensive load score of each node through a weighted fuzzy logic algorithm; dividing load intervals according to the comprehensive load score and matching a predefined strategy combination; and dynamically adjusting a compression algorithm, a compression ratio and a fragment merging parameter based on the current service flow peak-valley state of the target data block and a matched predefined strategy combination, the service flow peak-valley state being determined through a request processing rate and response time. The objective of the invention is to realize dynamic and fine-grained load sensing and data layout.

The invention discloses a brain-like chip-oriented spiking neural network compiling method, which comprises the following steps of: expanding a spiking neural network Relay operator in a TVM, accessing and binding to a hardware operator library, automatically realizing intermediate representation conversion and optimization from a spiking neural network model to brain-like chip adaptation, and realizing compilation of a brain-like chip-oriented spiking neural network. In combination with optimization methods such as pulse neural network model-oriented operator fusion optimization and brain-like chip-oriented data layout conversion, the method is realized by fully utilizing high performance of a hardware operator library; and finally, generating a deployment file package based on a TVM infrastructure and an LLVM compiler, and efficiently completing compiling and deployment of the spiking neural network model on a brain-like chip. According to the invention, the technical problems of high learning cost and low development efficiency of the existing neural network compiling method based on DSL and the neural network compiling method based on hardware intra function or operator API can be solved.

The invention relates to the field of data storage, in particular to a storage and calculation separation multi-dimensional data block indexing method based on adaptive learning. Comprising the steps of receiving original multi-dimensional data and a query load, and outputting a low-dimensional key set through a first model; the low-dimensional key set and the historical query load generate a partitioning scheme through a second model, and the partitioning scheme performs physical recombination on the original multi-dimensional data to output a plurality of physical data blocks; constructing a learning type index through the physical data blocks and the corresponding partitioning schemes; identifying hot spot and cold spot areas through the query frequency of each node of the learning type index and the real-time query load continuous monitoring index; when the access mode changes, adjusting the index structure, and outputting a self-adaptive index; and quickly positioning and reading the target data block through the self-adaptive index to complete access. According to the method, the index of adaptive learning is provided, and the index structure and the physical data layout are adjusted, so that the query accuracy and efficiency in a complex scene are improved, and the data storage overhead is reduced.

The invention provides a method for improving a cache hit strategy and a response speed, and relates to the technical field of cache management policies, the method comprises the following steps: monitoring the use state of a cache in real time, obtaining a cache hit rate, a cache capacity and a data validity index, and generating a real-time monitoring report of the use state of the cache; according to the real-time monitoring report of the cache use state, a cache management strategy is determined from a preset strategy library, and cache data updating is triggered; and when a data request is received, adjusting cache data according to a cache management strategy, including replacing old data and updating data layout, and recording a final access record and a cache state. According to the method, the cache hit rate and the response speed are improved by monitoring the cache state in real time, intelligently selecting the cache strategy, optimizing data access and prefetching, concurrent processing and dynamically adjusting the cache hierarchy, so that the overall performance of the computer is enhanced.

The present application provides a TVM-based NPU neural network model deployment method and device, including: obtaining the neural network model to be deployed and the hardware attribute information of the current NPU; determining the convolution operator to be deployed to the current NPU based on the computational logic of the neural network model; determining the optimal parameter configuration of each convolution operator in the current NPU based on the hardware attribute information of the current NPU and the parameter information of each convolution operator; adjusting the data layout and convolution weight of the TIR layer and modifying the parameters of the relay layer based on the optimal parameter configuration and the hardware attribute information of the current NPU to obtain a target TVM adapted to the current NPU; generating a deployment file for the neural network model suitable for the current NPU based on the target TVM. By adjusting the parameters of the TVM's TIR layer and relay layer accordingly, the obtained target TVM can be adapted to the NPU.

The invention discloses an NUMA (Non Uniform Memory Access) architecture perceived high-scalability learning index construction method and system and an operation method. According to the construction method, a mixed node tree structure is adopted to organize data, the structure comprises internal nodes accurately searched by a linear model and leaf nodes for storing data, the leaf nodes are composed of ordered gap nodes and segment nodes, and the segment nodes support dynamic evolution from an ordered stage to a semi-ordered stage based on data density. Conflict data is managed using hierarchical benchmark buckets. According to the system, a self-adaptive node evolution mechanism based on an operation cost model is realized, index performance is optimized through node reconstruction triggered by foreground write operation and background hot and cold node compression, a multi-thread concurrency control strategy is adopted, and a memory management and thread scheduling framework perceived by NUMA is adopted. The operation method provides an efficient point query and point insertion operation process. The data layout can be dynamically optimized, the operation cost is reduced, and the method is suitable for high-performance database and memory management scenes.

Tensor multiplication operations in a deep neural network (DNN) may be performed based on weight dequantization with shuffled data lay out. A tensor multiplication operation may have a weight tensor including weights in a floating-point data point. The weight tensor may be quantized to generate an integer weight block that has a smaller storage size than the weight tensor. The integer weight tensor may be divided into weight blocks. A weight block may be further partitioned into weight groups based on a predetermined group size. A weight group may be packed through bit right shifting. The data layout in the packed weight group may be changed by shuffling the data elements in the weight group. The packed and shuffled weight group may be dequantized to produce a floating-point weight block. The tensor multiplication operation may be executed on the floating-point weight block.

Techniques for determining a compatible data layout for a computational flow being executed on an integrated circuit device may include obtaining a representation of a set of connected nodes representing loopnests in a compute flow graph. Those of the nodes in the set of connected nodes that are associated with operators having a fixed data layout can be initialized into a set of layout groups. A set of merging operations can then be iteratively performed to form a single layout group from the set of connected nodes. The set of merging operations may include identifying a set of frontier nodes adjacent to the set of layout groups, determining an initialization cost of each of the frontier nodes, selecting a frontier node having a lowest initialization cost, and merging the selected frontier node with one or more adjacent layout groups to form a new layout group having a compatible data layout.

The invention discloses an optimization method, system and device for a ReLee filtering algorithm based on a CUDA platform, and relates to the technical field of signal processing.The optimization method comprises the following steps that a first memory and a second memory are applied in a global memory of a GPU, image data to be filtered in a memory of a CPU is copied to the first memory, and the second memory is copied to the second memory; according to the to-be-filtered image data layout block stored in the first memory, after a CUDA kernel function is started, all threads in the block are allowed to execute the kernel function so as to obtain a filtering result, the filtering result is stored in the second memory, and the filtering result is copied to the memory of the CPU. Through the steps, the optimization method is favorable for improving the calculation efficiency.

The invention discloses a data layout optimization method and device applied to NPU code compilation and a medium. The method comprises the steps that an intermediate representation IR input by an upper layer is split into an operation type OP and an operand, and the operand input by the upper layer is divided into logic data and a logic mask; converting the logic data of the upper layer into data vector representation of the abstraction layer, and converting the logic mask of the upper layer into mask vector representation of the abstraction layer; obtaining a corresponding bottom hardware instruction capability according to an operation type OP input by an upper layer, and performing legalization operation on the operation type OP; and performing legalization processing on the converted abstract data vector type representation and mask vector representation according to the target hardware capability, performing instruction mapping on the processed abstract instruction according to the underlying hardware pair operation type OP, and generating a target LLVM instruction compatible with the underlying hardware. Register layout abstraction and conversion can be carried out on the NPU code under mixed precision input, and the utilization efficiency of the NPU bottom layer register is improved.

The invention provides an operator fusion mechanism distribution method and system for a vector quantization large language model, and the method comprises the following steps: obtaining layout data which comprises a dequantization data layout and a layout needed by a calculation kernel; calculating the number of data shuffling times based on the layout data, comparing the number of data shuffling times with a preset threshold value to dynamically respond to a decision mechanism, and when the number of data shuffling times is smaller than the preset threshold value, adopting a first decision mechanism which at least comprises a register level operator fusion mechanism; and when the number of data shuffling times is greater than or equal to a preset threshold value, adopting a second decision mechanism which at least comprises a shared memory level operator fusion mechanism. According to the operator fusion mechanism allocation method and system for the vector quantization large language model, the problems of bandwidth bottleneck and delay caused by frequent transmission of data between a shared memory and a register are solved, and therefore more efficient dequantization and calculation fusion are achieved.

According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input / output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.SPL

Columnar storage provides many performance and space saving benefits for analytic workloads, but previous mechanisms for handling single row update transactions in column stores suffer from poor performance. A columnar data layout facilitates both low-latency random access capabilities together with high-throughput analytical access capabilities, simplifying Hadoop architectures for use cases involving real-time data. In disclosed embodiments, mutations within a single row are executed atomically across columns and do not necessarily include the entirety of a row. This allows for faster updates without the overhead of reading or rewriting larger columns.

The invention provides a graph data communication intensity mapping method and system based on optical transport network topology. According to the method, an adjacent matrix is established by extracting graph data structure information, vertex centrality and a clustering coefficient are calculated, and a graph data communication feature matrix is generated; oTN network equipment information and optical link topology are collected, link parameters and wavelength resource states are measured, and an OTN physical network feature matrix is obtained; establishing a double-layer mapping relation matrix through a resource mapping algorithm; integrating the communication frequency, the time delay sensitivity, the bandwidth requirement, the wavelength resource and the topological matching degree, and calculating a communication strength weight matrix; generating a candidate layout scheme, performing multi-dimensional evaluation, and determining an optimized data layout scheme; and dynamically adjusting the mapping relation by adopting an incremental updating algorithm. According to the invention, the efficient collaboration of the graph computing task and the optical transport network resource is realized, and the performance and resource utilization efficiency of the distributed graph computing system are obviously improved.

The invention relates to a mask generation method and device, computer equipment, a readable storage medium and a program product. The method comprises the following steps: after obtaining first matrix data, loading the first matrix data to a first memory in response to a target access instruction to adjust a data arrangement mode of the first matrix data to obtain second matrix data; determining a multiplication result matrix of the second matrix data, and statically distributing the multiplication result matrix to a second memory corresponding to the corresponding calculation thread; and determining a mask register according to the thread identifier and the mask boundary of the calculation thread. In the process of loading the first matrix data to the first memory, the complex high-dimensional tensor first matrix data is adjusted into a regularly linearly arranged two-dimensional matrix, so that optimization and recombination of data layout are realized, a large number of access instructions across calculation units are prevented from being generated during data access in the mask calculation process, and the data access efficiency is improved. The utilization efficiency of the memory broadband is improved, and the overall calculation performance of the chip is improved.

The invention discloses a generation method and device for a mixed precision quantization operator, and relates to the field of deep learning, and the method comprises the steps: converting a quantization program inputted by a user into an initial Qtile calculation graph based on Qtile tensor representation; performing equivalent transformation on the initial Qtile calculation graph to generate a plurality of candidate Qtile calculation graphs which are equivalent to the initial Qtile calculation graph; according to the reuse frequency of operator input data in each candidate Qtile calculation graph, determining an optimal data layout position and an optimal data loading strategy of each candidate Qtile calculation graph; on the basis of the optimal data layout, the optimal data loading strategy and a code generation technology based on a template, codes of all the candidate Qtile computational diagrams are generated, and the codes of the candidate Qtile computational diagrams are achieved through codes of mixed precision quantization operators. According to the invention, an optimized high-performance mixing precision quantization operator can be output.

Client data layout retention across server disruption can be performed and managed. In response to a data layout request from a client device (CD), a server can communicate, to CD, metadata, comprising a mapping of a group of blocks, in a data store of the server, to which CD is able to write data to the file, a file offset associated with the file, and a filesystem block number (FSBN) associated with the file offset. CD can write data to the group of blocks. CD can communicate data layout commit request, comprising the metadata relating to data layout, including file offset and FSBN, to the server. If server disruption occurs prior to committing data layout, CD can communicate reclaim request, comprising the metadata, to server, and server can recreate the data layout and commit the data layout to the data store based on the metadata.

The invention discloses a solid state disk-based data transmission method and device, a medium and a product, and relates to the field of solid state disks. According to the method, a data layout description header is obtained from a host memory in a direct memory access mode according to a target memory initial address; analyzing the data layout description header through a flash translation layer of the solid state disk, identifying each data segment entry, and extracting length information and life cycle attribute tags of corresponding data segments from each data segment entry; based on the life cycle attribute tag, planning a corresponding physical flash memory page for each data segment as a target write address of the data segment; and based on the target write-in address, controlling the solid state disk to execute DMA operation segment by segment according to the sequence of data segment entries in the data layout description head until the write-in of the total data length is completed. By implementing the technical scheme provided by the invention, the data storage efficiency of the solid state disk is improved.

This paper proposes a data layout method for a cloud-edge-device collaborative environment, and studies and designs a data placement strategy tailored to the characteristics of the cloud-edge-device environment and application requirements. The overall approach of the present invention is to analyze the node, network, and data characteristics of the cloud-edge-device environment, extract and calculate the key factors affecting data distribution, and construct a node-data model for subsequent analysis and use; establish an overall optimization objective with constraints to provide mathematical tools for data layout tasks; based on the node-data model, achieve rapid initial data layout, reduce the overhead of large-scale optimization calculations, and alleviate the storage pressure on nodes connected to the terminals collecting data; and perform data rearrangement and layout optimization based on the actual user needs.

A drive placement or placement functionality can enable initial copies of data to be placed on a drive in reclaim unit (HRUs) in a manner which is probabilistically more efficient from a garbage collection (GC) perspective and leverages knowledge of a host or application using the data. The placement functionality enables the advantages of fine-grained placement functionality while simultaneously allowing a storage device or storage drive to maintain NAND or other management responsibility, and not allocate that responsibility to an application or host device using the device.

The invention provides a memory management method and a memory controller, and aims to solve the problem of storage mismatch caused by dynamic change of a data access mode. The method comprises the following steps: acquiring target data stored in a target entity page in a plurality of entity pages; determining a data attribute of the target data and an offset attribute of the target entity page; and if the data attribute of the target data is not matched with the offset attribute of the target entity page, selecting a matched entity page of which the offset attribute is matched with the data attribute from the plurality of entity pages, and moving the target data from the target entity page to the matched entity page. Through the technical scheme of the invention, the memory controller can actively and periodically identify and correct the attribute mismatch between the stored data and the physical position thereof, and the continuous dynamic optimization of the data layout is realized, so that the data reliability and the overall performance of the storage device in the long-term use process are improved.

This invention discloses a method, system, and storage medium for verifying instrument data records. Based on a received data verification command, each record in the instrument data record table is sequentially retrieved. The corresponding screen layout information is retrieved from the instrument information database according to the instrument model. Then, the display features in the screen image are identified and analyzed, and compared with the screen area shape and measurement data layout information stored in the instrument information database. If they are not similar, an instrument model entry error message is triggered. If they are similar, the identified instrument measurement parameters are compared with the recorded parameters in the data record. If they are not the same, a measurement parameter entry error message is triggered. By using screen image content to automatically verify and verify the instrument model and measurement parameters in electronic experimental records, the inefficiency and error-prone nature of existing manual verification methods are overcome.

The invention relates to a method, a computing device, a medium and a program product for moving tensor data. The method comprises the steps that in response to the fact that a source object is determined to be multi-dimensional tensor data, initialization about parameters of a minimum repetitive unit is conducted on the source object, so that a repetitive layout mode about the minimum repetitive unit of the source object is obtained, and the minimum repetitive unit at least describes the organization mode of the multi-dimensional tensor data in a register; traversing the registers based on the repetition layout mode of the minimum repetition unit so as to generate an access sequence of the registers related to the source object and an access sequence of the registers related to the target object; and executing a moving operation of tensor data from the source object to the target object at least based on the generated access sequence of the register related to the source object and the access sequence of the register related to the target object. The method can adapt to complex and irregular tensor data layout modes and characteristics of different hardware platforms, and is beneficial to parallel computing efficiency.

The invention discloses an observable method and system for a unified log index and tracking data, and the method comprises the steps: collecting various types of original observation data, carrying out the unified formatting, constructing a column type storage structure, and carrying out the hierarchical storage; then optimizing data layout by utilizing column-level metadata and a query mode feature library, and implementing a multi-level index strategy; meanwhile, through data cleaning, structured enhancement and contextual information association, a causal atlas between heterogeneous observation data is established, and observation data with rich contexts is generated; and finally, a high-performance query processing system is constructed based on a unified query engine and a sub-linear algorithm, and progressive result return and visual analysis are realized. According to the method, the data retrieval efficiency and the analysis depth are remarkably improved, operation and maintenance personnel can more quickly position the root cause of the system problem, and the average time of fault diagnosis is effectively shortened.

The invention relates to the technical field of heterogeneous environment task migration, and particularly provides a heterogeneous environment task migration method and system and a medium. According to the method, a uniform data layout and a virtual address space structure are constructed to unify state representation modes among different instruction set architectures; the extensible executable file is expanded on the basis of a fat binary file, and a symbol table is split into a basic symbol table shared across instruction set architectures and an independent extended symbol table of each instruction set architecture; and executing task migration across the instruction set architecture by the runtime environment in combination with the basic symbol table and the extended symbol table based on the migration points and the trigger pages embedded in the construction process. According to the method, the mobility, the cross-platform compatibility and the system analyzability are balanced, and systematic support is provided for task migration in a heterogeneous environment.

The present disclosure proposes a communication method and a distributed system for distributed training of mixed expert models. The method comprises: collecting gating network routing decision information corresponding to each input data; generating mapping information for each input data to be transmitted according to the deployment information of the expert module and the collected gating network routing decision information, wherein the mapping information is used to indicate the reading position of the input data in the sending end buffer and the writing position in the receiving end buffer; and performing a communication operation based on the mapping information to send the input data to be transmitted to the corresponding expert module. By introducing the mapping information for indicating the address relationship of the input data in the memory in the communication operation, the data rearrangement is synchronized in the communication process, thereby realizing the cooperative execution of the communication path and the data layout. Further, a two-stage mapping structure across machines and within machines can be constructed to realize efficient training based on topology hierarchical communication.

The invention discloses a graph structure data layout optimization method for a Qt tree layering and dynamic force oriented graph, which comprises the following steps of: loading graph structure data and carrying out data preprocessing, converting original data into a structured data table containing node attributes and connection relationships, dividing node levels through a depth-first traversal algorithm, and carrying out layout optimization on the structured data table; and dynamically generating a fan-shaped initial layout according to the degrees of the nodes, carrying out layout iterative optimization calculation by adopting a force-oriented layout algorithm, determining the position information and topological connection relationship of each primitive after optimization, and carrying out visual implementation and interaction on the optimized graph structure data layout. According to the scheme of the invention, through cooperation of hierarchical and elastic constraint mechanisms, the readability of a graph containing circulation / multiple father nodes is improved, a dynamic updating strategy enables layout to maintain overall stability during interaction, the structure confusion degree is reduced, and pre-layout processing and a parameter dynamic attenuation strategy effectively improve the convergence speed of a force steering algorithm.

The application discloses a kind of dynamic resource adaptation multilayer cache architecture systems, it is related to computer system architecture and data storage cache technical field.The system includes: resource state perception module, for real-time acquisition system performance index data and load characteristics in running, performance index data includes the access delay of each cache level, cache hit rate, data access frequency, cache medium read-write speed and system concurrent connection quantity.The application is through resource state perception module comprehensive acquisition each cache level performance index and load characteristics, combined with the deep reinforcement learning algorithm of cache strategy decision module dynamically generates cache strategy parameter, solves the problem that static configuration is difficult to adapt complex load in prior art;Data layout optimization module is through hot data identification, hot and cold data asynchronous migration and cross-level data block size adaptation, accurately match the characteristics of heterogeneous cache medium, make up the defect that traditional architecture is not enough to perceive medium difference.

The application provides a convolution calculation method, an electronic device, a storage medium and a program product, and belongs to the technical field of artificial intelligence, and comprises the following steps: performing feature extraction on input information to obtain an input tensor; folding the input tensor along a target dimension direction to a batch dimension to obtain a plurality of batch target tensors; performing complete convolution calculation on each target tensor to obtain a first convolution result; and obtaining a convolution result of the input information according to the first convolution result; wherein the target dimension of the input tensor is greater than a first threshold under the limitation of a hardware size, the target dimension of the target tensor is less than or equal to the first threshold, and the target dimension is height or width. When the target dimension of the input tensor exceeds the limitation of the hardware size, the input tensor is folded along the target dimension to the batch dimension, the convolution calculation of the over-limit tensor can be realized based on the native hardware and the native data layout, the data layout does not need to be replaced, and the performance of the convolution calculation is improved.