Headphone chip circuit, TWS earphone and control method

Abstract

The embodiment of the present invention discloses an earphone chip circuit, a TWS earphone, and a control method, wherein the earphone chip circuit includes: a pulse generating circuit connected to the VBUS terminal, for sending a high-frequency pulse sequence; a pulse detecting circuit connected to the VBUS terminal, for detecting the high-frequency pulse sequence. If the original high-frequency pulse sequence is detected, a first message is sent to the power-on / off circuit; the power-on / off circuit is used to receive the first message to turn on the earphone, and after the power-on is completed, a second message is fed back to the pulse generating circuit to stop the pulse generating circuit from sending the high-frequency pulse sequence. The embodiment of the present invention can solve the problem of turning on the earphone in the 0V compartment at zero cost and zero risk.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular to an earphone chip circuit, a TWS earphone, and a control method. Background Art

[0002] TWS stands for True Wireless Stereo Bluetooth Headsets. Their breakthrough over traditional Bluetooth headsets lies in their true wireless nature, eliminating the wired connection between the left and right earbuds. Apple's release of the first TWS in 2016 ushered in a new era for TWS earbuds, and the entire TWS industry has experienced seven years of rapid development from 2016 to 2022. Generations of products have been continuously iterating with technological updates, addressing early pain points such as poor RF performance, frequent lags, slow left-to-right earbud connectivity, and single-ear usage limitations. With increasing user experience requirements, the industry's focus has become increasingly refined.

[0003] In addition to a pair of earphones, the TWS system also has a storage box, which is what we call a charging bin. Literally, it means something similar to a power bank that can charge earphones. The mobile phone is paired with a power bank, and the TWS earphones are paired with a charging bin. Indeed, the early definition of a charging bin was simply to charge earphones. Users can listen to songs after taking out the earphones and turning them on. After listening to the songs, they can turn off the earphones and put them into the charging bin to charge the earphones. However, as mentioned earlier, after technological updates and iterations, the function of the charging bin is far more than just charging the earphones. The current hot spot is the intelligent charging bin to achieve intelligent interaction with the earphones. The charging bin not only charges the earphones, but also interacts with the earphones to turn them on and off. It communicates with the earphones in real time to exchange various information, allowing the bin and the earphones to achieve intelligent interconnection. The key technology here is the intelligent interaction between the bin and the earphones. The bin and the earphones have only two contact points, one for signal and one for ground, to achieve communication, charging, and power-on interaction. The focus of this invention is the power-on control interaction between the charging bin and the earphones. Currently, the power-on interaction between the bin and the earphones is divided into the following four types:

[0004] The first button power on / off technology: after taking the earphones out of the compartment, you need to press the button on the earphones to turn them on. After using the earphones, press the button to turn them off and then put them back into the compartment to charge. This is an early technology with a cumbersome user experience. It is now basically eliminated. The compartment and earphones are completely independent and have no interaction. There are no special technical requirements for either the compartment or the earphones.

[0005] The second technology of power on and off is code communication: the earphones will be turned on immediately when the lid of the charging case is opened, and will be turned off when the lid is closed after use. For example, Apple's AirPods is this method. The user experience is very good and no additional manual button pressing is required to turn it on and off. This usually requires the charging case to be equipped with a Hall switch and the charging case and earphones to be able to communicate with each other via a single line (single-line bidirectional UART communication, single-line unidirectional VBUS communication). After the case lid is opened, a power-on command is sent to the earphones. After the case lid is closed, a shutdown command is sent to the earphones. After the earphones are fully charged, a power-off command is sent to the earphones to enter ultra-low power consumption mode. This case design is the most complex and the cost is the highest.

[0006] The third type is intermediate level power on / off technology: after the cover is opened, the earphones are taken out and turned on. After the earphones are turned off for use, they are placed in the cover and turned off for charging. After they are fully charged, the cover and earphones enter ultra-low power mode. This type of cover and earphones usually do not communicate with each other, and the output level of the earphones is entirely controlled by the cover. When the cover is dormant, the output 5V is reduced to an intermediate level (usually around 3V) to save power. The cover has a headphone plug-in detection function. When the cover detects the earphones entering the cover, it turns on 5V to charge the earphones. After the earphones are fully charged, the 5V is reduced to an intermediate level. For the earphones, the 5V is turned off and charged when it encounters 5V. When the 5V drops to the intermediate level, it enters ultra-low power mode. When it encounters 5V or the intermediate level, it turns on when it is unplugged. This type of cover without communication is usually costly, but the user experience is also very good, so it is widely used.

[0007] The fourth type is the 5V normally-on level power on / off technology: after the cover of the compartment is opened, the earphones are taken out and turned on, and after the earphones are turned off for use, they are put back into the compartment and turned off for charging. After they are fully charged, the compartment and earphones enter the ultra-low power consumption mode. This is only slightly different from the third type. This technology compartment will not have an intermediate level and will always output 5V. For the earphones, they will shut down and charge when they encounter 5V. The earphones themselves will enter the ultra-low power consumption mode when they detect that they are fully charged. The earphones will turn on when they encounter 5V and are unplugged. This type of compartment has very high requirements for the compartment's boost module, and the boost module needs to have low power consumption (less than 10ua) when lightly loaded. This type of compartment is stable, reliable, and simple in design, but requires the chip manufacturer to provide an excellent low-power boost module.

[0008] From the previous introduction, we can see that there is a boundary scenario for the intermediate level switch or 5V normally open switch: when the power supply is completely out of the warehouse, that is, when the warehouse is 0V, if the earphones are in the warehouse, the power on inside the warehouse will appear. However, power on inside the warehouse is a taboo for all manufacturers at present. Summary of the Invention

[0009] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes an earphone chip circuit, a TWS earphone and a control method, which can solve the problem of starting up the earphone in the 0V compartment at zero cost and zero risk.

[0010] On one hand, an embodiment of the present invention provides an earphone chip circuit, including: a pulse generating circuit, connected to the VBUS end, for sending a high-frequency pulse sequence; a pulse detection circuit, connected to the VBUS end, for detecting the high-frequency pulse sequence, and if the original high-frequency pulse sequence is detected, sending first information to a power-on / off circuit; the power-on / off circuit is used to receive the first information to turn on the earphone, and after the power-on is completed, feedback second information to the pulse generating circuit to cause the pulse generating circuit to stop sending the high-frequency pulse sequence.

[0011] According to some embodiments of the present invention, the pulse detection circuit includes: a first comparator, used to detect whether the voltage of VBUS is removed. If so, a third signal is output to the pulse generating circuit through the first output terminal to start the pulse generating circuit; a second comparator, used to detect the pulse sequence on VBUS and compare it with the original high-frequency pulse sequence, obtain a comparison result and feed it back to the power on / off circuit through the second output terminal.

[0012] According to some embodiments of the present invention, the pulse generating circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor: the first transistor has a drain connected to the VBUS terminal, a gate connected to the first output terminal of the pulse detection circuit, and a source connected to the second transistor; the second transistor has a source connected to the source of the first transistor, a gate connected to the first output terminal of the pulse detection circuit, and a drain connected to the third transistor and the fourth transistor; the third transistor has a source connected to the power supply terminal, a gate connected to the output terminal of the data selector, and a drain connected to the fourth transistor; the fourth transistor has a source connected to the ground terminal, a gate connected to the output terminal of the data selector, and a drain connected to the third transistor.

[0013] According to some embodiments of the present invention, the data selector includes: a first input terminal connected to the bidirectional communication unit; a second input terminal connected to the pulse logic control unit; and a third input terminal connected to the unidirectional communication unit.

[0014] Another aspect of an embodiment of the present invention provides a TWS headset, comprising: the headset chip circuit as described above.

[0015] Another aspect of an embodiment of the present invention provides a control method for the headphone chip circuit described above, comprising the following steps: a pulse generating circuit sends a high-frequency pulse sequence; a pulse detection circuit detects the high-frequency pulse sequence, and if the original high-frequency pulse sequence is detected, sends a first information to a power-on / off circuit; the power-on / off circuit receives the first information to turn on the headphones; after the power-on is completed, the power-on / off circuit feeds back a second information to the pulse generating circuit; and the pulse generating circuit stops sending the high-frequency pulse sequence.

[0016] According to some embodiments of the present invention, before the pulse generating circuit sends a high-frequency pulse sequence, the method includes: a first comparator of the pulse detection circuit detects whether the voltage of VBUS is removed; if so, outputs a third signal to the pulse generating circuit through a first output terminal to start the pulse generating circuit.

[0017] According to some embodiments of the present invention, the pulse detection circuit detects the high-frequency pulse sequence, including: the second comparator of the pulse detection circuit detects the pulse sequence on VBUS, and compares it with the original high-frequency pulse sequence, obtains the comparison result and feeds it back to the switch circuit through the second output terminal.

[0018] According to some embodiments of the present invention, the method further includes: the first comparator detects the high voltage on VBUS in real time, and when the high voltage is detected, sends a fourth signal to control the first transistor and the second transistor of the pulse generating circuit, so that the first transistor and the second transistor block the pulse from being sent out.

[0019] The embodiments of the present invention have at least the following beneficial effects: the present invention can detect partial capacitive loads through the VBUS pin of the headphone chip, and send an adjustable pulse sequence through the VBUS pin to implement external capacitive load detection to determine whether the headphones are truly out of the warehouse, achieving true zero cost.

[0020] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0022] Figure 1 Schematic diagram of the structure of an embodiment of the present invention;

[0023] Figure 2 Schematic diagram of the structure of the pulse generating circuit and the pulse detecting circuit according to an embodiment of the present invention;

[0024] Figure 3 Schematic diagram of a control method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0026] In the description of the present invention, "several" means one or more, "more" means two or more, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0027] In the prior art, there are two solutions to the problem of turning on the 0V headset in the compartment:

[0028] Solution 1 to the problem of turning on the 0V earphones in the warehouse: The warehouse has three contacts, VBUS / GND / CTR pins, of which VBUS and GND are the two commonly used pins, namely power / communication and ground. The added POGO pin is CTR. This pin has a fixed pull-down resistor in the warehouse to pull it to a low level. Here we analyze in detail how to solve the problem of turning on the 0V earphones in the warehouse. When the earphones are in the warehouse, the VBUS at the headphone end is 5V and it is in the shutdown charging mode. If the VBUS is in the middle level, it is in the ultra-low power mode. The CTR at the earphone end is pulled down by the warehouse end. If the earphones are taken out of the warehouse, there are two events at the earphone end: the first event is that the VBUS of the earphone detects that the level is pulled out, and the second event is that the CTR of the earphone detects that the pull-down is released. When these two events occur at the same time, you know that the earphones have left the warehouse and can be turned on. If the warehouse is completely out of power but the earphones are still in the warehouse, the earphones can only see one event, that is, VBUS detects the level and is unplugged but CTR is still in the pull-down state. In this way, the earphones know that they have not left the warehouse and may not start up because the warehouse is out of power. This perfectly solves the problem of turning on the earphones in the 0V state of the warehouse. However, it is obvious that three POGO contacts are used, which increases the cost and also puts higher requirements on the control of production line yield. After all, three contacts are definitely more difficult to control quality than two contacts. Therefore, this solution is not widely used and is generally adopted by some manufacturers with certain strength.

[0029] Solution 2 to the problem of turning on the earphones inside the warehouse when they are at 0V: This solution is similar to solution 1, except that the added POGO contact is replaced with Hall detection, so the user still sees two contacts (VBUS and GND). There is a Hall sensor inside the earphones, and there is a small magnet at the corresponding position in the warehouse. When the earphones enter and exit the warehouse, the Hall sensor of the earphones will indicate the entry and exit actions to the earphones. Therefore, even if the warehouse is 0V and the earphones see the VBUS level is unplugged, the Hall indicator indicates that the earphones are still in the warehouse, so the earphones will not turn on in this case. Only when the Hall sensor detects that the earphones are leaving the warehouse and the VBUS is unplugged will it be considered as a true exit and will it turn on. This solution is actually similar to solution 1, both of which are achieved at the cost of cost and quality control. There are already two magnets in the warehouse to attract the earphones. Adding two more magnets also requires considering the problems of spatial magnetic lines of force to prevent the Hall sensor from being interfered with by other magnets. Therefore, it is not as simple as adding two small magnets. This solution is actually not adopted by many manufacturers and is generally adopted by some manufacturers with certain strengths.

[0030] As described above, the existing technical shortcomings mainly include the following two points:

[0031] 1. Increased costs: Whether adding POGO contacts or adding Hall sensors will increase additional costs.

[0032] Second, it increases the difficulty of quality control. Currently, the mainstream is two-contact POGO. Increasing it to three POGO contacts will obviously increase the risk of poor contact. Currently, both earphones and charging cases are developing towards miniaturization. Adding POGO contacts also poses certain challenges to the overall mold design. Adding Hall sensors also poses similar problems. It is necessary to add two more magnets to the charging case. Because the magnets affect the inductance of the boost module and the magnetic field distribution within the case, many factors need to be weighed to determine the placement of the additional magnets, which greatly increases the difficulty of the entire design.

[0033] The present invention aims to solve a boundary scenario of the level power on / off solution, namely the problem of turning on the earphones in the 0V state inside the compartment. An adjustable high-frequency pulse is sent through the VBUS pin to detect the VBUS load at the earphone end to determine whether the earphones are actually out of the compartment. No additional materials are required, and the problem can be solved by simply adding the function of the present invention inside the earphone chip.

[0034] The earphone chip circuit of an embodiment of the present invention includes: a pulse generating circuit, connected to the VBUS end, for sending a high-frequency pulse sequence; a pulse detection circuit, connected to the VBUS end, for detecting the high-frequency pulse sequence, and if the original high-frequency pulse sequence is detected, sending a first information to the power-on / off circuit; the power-on / off circuit is used to receive the first information to turn on the earphone, and after the power-on is completed, feed back a second information to the pulse generating circuit to cause the pulse generating circuit to stop sending the high-frequency pulse sequence.

[0035] Reference Figure 1 The dotted box shows the internal circuitry of the headphone chip. The POGO+ is connected to the VOUT output of the charging compartment's boost circuit. The charging compartment's VOUT can output 5V and intermediate voltage levels. Once the headphones are in the compartment, the POGO+ contacts the headphones' VBUS pin. The VBUS pin on the headphone side can detect the voltage level, such as whether it is 5V or intermediate voltage. The core idea of this invention is that the headphone VBUS pin sends an adjustable pulse to the POGO, which then uses an internal detection circuit to detect the transmitted pulse. By comparing the transmitted pulses, it can accurately determine whether there is a capacitive load on the POGO+ and thus whether the headphones have truly left the compartment.

[0036] Usually, the output of the boost module of the charging case will have a 1UF~10UF capacitor. After the VBUS pin on the headphone end detects the level and is unplugged, it needs to further determine whether it has left the case. Here, the pulse sending circuit will send a high-frequency pulse sequence. If the headphone has not left the case, because there is a capacitor on the case end connected to VBUS, the charging and discharging of the capacitor will distort the output high-frequency pulse or directly eliminate it. In this way, the pulse detection circuit inside the headphone chip cannot receive the original pulse or receives a distorted pulse sequence, which can be considered as 0 battery in the case. Then, the information is passed to the power-on / off circuit to prevent the headphone from turning on. If the pulse detection circuit detects the original pulse sequence, it can be considered that the VBUS level of the headphone was unplugged due to leaving the case. In this way, the pulse detection circuit can pass information to the power-on / off circuit to turn on the headphone. After the power-on is completed, the power-on / off circuit feedback information to the pulse generating circuit to stop sending pulses.

[0037] Another key design feature is that the VBUS pulse generator circuit must be triggered when there is no voltage on VBUS. This prevents conflicts between the pulse generator circuit and the VBUS voltage when the headphones are charging (i.e., when VBUS is at 5V). Furthermore, even if a pulse sequence is incorrectly generated due to improper software processing while the headphones are charging (i.e., when VBUS is at 5V), a protection mechanism within the headphone chip prevents damage to the internal pulse transmission circuitry, leading to malfunction.

[0038] The pulse width of the pulse generating circuit can be flexibly adjusted by software according to the size of the capacitor. The smaller the capacitance, the higher the pulse frequency required. The present invention can support a minimum POGO+ capacitor of 0.1UF, which basically covers all current mainstream charging warehouse designs.

[0039] The entire detection process of the present invention is completed automatically by hardware. It only needs to inform the software of the final detection result, and then the software determines the power on and off behavior. The entire process is stable and reliable and does not require excessive software participation.

[0040] In some embodiments, the pulse detection circuit includes: a first comparator, used to detect whether the voltage of VBUS is removed. If so, a third signal is output to the pulse generating circuit through the first output terminal to start the pulse generating circuit; a second comparator, used to detect the pulse sequence on VBUS and compare it with the original high-frequency pulse sequence, obtain the comparison result and feed it back to the power on / off circuit through the second output terminal.

[0041] In some embodiments, the pulse generating circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor: the first transistor, the drain is connected to the VBUS terminal, the gate is connected to the first output terminal of the pulse detection circuit, and the source is connected to the second transistor; the second transistor, the source is connected to the source of the first transistor, the gate is connected to the first output terminal of the pulse detection circuit, and the drain is connected to the third transistor and the fourth transistor; the third transistor, the source is connected to the power supply terminal, the gate is connected to the output terminal of the data selector, and the drain is connected to the fourth transistor; the fourth transistor, the source is connected to the ground terminal, the gate is connected to the output terminal of the data selector, and the drain is connected to the third transistor.

[0042] Reference Figure 2 , pulse generation circuit and pulse detection circuit, where Q0, Q1, Q2, Q3, and U2 form the pulse generation circuit, and U0 and U1 form the pulse detection circuit. Here we will describe the whole process in detail from the circuit level:

[0043] exist Figure 2 In the circuit, U0 and U1 form the pulse detection circuit. Function 0 of U0's comparator detects whether the VBUS voltage has been removed. If so, the U0 comparator outputs the Vbus_detec signal to the pulse generator circuit, enabling it to operate. Function 1 of U0's comparator prevents the pulse generator circuit from generating pulses that conflict with the 5V voltage when high voltage is present on VBUS. This works by U0 detecting high voltage on VBUS in real time. Upon detection, the Protect_detect signal controls Q0 and Q1, blocking the pulse from being sent.

[0044] U1 is the pulse comparison part of the pulse detection circuit. It detects the pulse sequence on VBUS and compares it with the original pulse. The comparison result is fed back to the power on / off circuit, and the software decides whether to turn the machine on or off. At the same time, the power on / off circuit also feeds back the power on / off result to the pulse generation circuit to let it shut down or continue sending pulses.

[0045] Q0, Q1, Q2, Q3, and U2 form a pulse generation circuit. U2 selects the pulse logic control unit by setting MODE_SEL by software. The digital pulse sequence is converted into a VCC-IO voltage domain pulse after passing through Q2 / 3, and then sent to the VBUS pin through the bidirectional switch composed of Q0 / Q1.

[0046] Reference Figure 3 The control method of an embodiment of the present invention includes the following steps: a pulse generating circuit sends a high-frequency pulse sequence; a pulse detecting circuit detects the high-frequency pulse sequence, and if the original high-frequency pulse sequence is detected, sends a first information to the power-on / off circuit; the power-on / off circuit receives the first information to turn on the headset; after the power-on is completed, the power-on / off circuit feeds back a second information to the pulse generating circuit; and the pulse generating circuit stops sending the high-frequency pulse sequence.

[0047] It can be understood that before the pulse generating circuit sends a high-frequency pulse sequence, the control method includes: detecting whether the voltage of VBUS is removed through the first comparator of the pulse detection circuit; if so, outputting a third signal to the pulse generating circuit through the first output terminal to start the pulse generating circuit.

[0048] The pulse detection circuit detects the high-frequency pulse sequence, including: the second comparator of the pulse detection circuit detects the pulse sequence on VBUS, compares it with the original high-frequency pulse sequence, obtains the comparison result and feeds it back to the switch circuit through the second output terminal.

[0049] In some embodiments, the control method of the embodiment of the present invention also includes: the first comparator detects the high voltage on VBUS in real time, and when the high voltage is detected, sends a fourth signal to control the first transistor and the second transistor of the pulse generating circuit, so that the first transistor and the second transistor block the pulse from being sent out.

[0050] Although specific embodiments are described herein, those skilled in the art will recognize that many other modifications or alternative embodiments are also within the scope of the present disclosure. For example, any of the functions and / or processing capabilities described in conjunction with a particular device or component may be performed by any other device or component. In addition, although various exemplary implementations and architectures have been described in accordance with the embodiments of the present disclosure, those skilled in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of the present disclosure.

[0051] The embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in the relevant technical field without departing from the scope of the present invention.

Claims

1. A headphone chip circuit, characterized in that: include: A pulse generating circuit is connected to the VBUS terminal and is used to send a high-frequency pulse sequence; a pulse detection circuit connected to the VBUS terminal, configured to detect the high-frequency pulse sequence, and send first information to the power on / off circuit if the original high-frequency pulse sequence is detected; The switch circuit is used to receive the first information to turn on the headset, and after the power-on is completed, feedback the second information to the pulse generating circuit to stop the pulse generating circuit from sending the high-frequency pulse sequence; The pulse detection circuit includes a first comparator, which is used to detect whether the voltage of VBUS is removed. If so, the comparator outputs a third signal to the pulse generating circuit through the first output terminal to start the pulse generating circuit; The pulse detection circuit includes a second comparator, which is used to detect the pulse sequence on VBUS and compare it with the original high-frequency pulse sequence to obtain a comparison result and feed it back to the switch circuit through a second output terminal.

2. The earphone chip circuit according to claim 1, characterized in that: The pulse generating circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor: The first transistor has a drain connected to the VBUS terminal, a gate connected to the first output terminal of the pulse detection circuit, and a source connected to the second transistor; The second transistor has a source connected to the source of the first transistor, a gate connected to the first output terminal of the pulse detection circuit, and a drain connected to the third transistor and the fourth transistor; The third transistor has a source connected to the power supply terminal, a gate connected to the output terminal of the data selector, and a drain connected to the fourth transistor; The fourth transistor has a source connected to the ground terminal, a gate connected to the output terminal of the data selector, and a drain connected to the third transistor.

3. The earphone chip circuit according to claim 2, characterized in that: The data selector comprises: A first input terminal connected to the bidirectional communication unit; The second input terminal is connected to the pulse logic control unit; The third input terminal is connected to the unidirectional communication unit.

4. A TWS headset, characterized in that: include: The earphone chip circuit according to any one of claims 1 to 3.

5. A control method for the earphone chip circuit according to any one of claims 1 to 3, characterized in that: The following steps are involved: The first comparator of the pulse detection circuit detects whether the voltage of VBUS is removed, and if so, outputs a third signal to the pulse generating circuit through the first output terminal to enable the pulse generating circuit to start working; The pulse generating circuit sends a high-frequency pulse train; The pulse detection circuit detects the high-frequency pulse sequence, and the second comparator of the pulse detection circuit detects the pulse sequence on VBUS and compares it with the original high-frequency pulse sequence, obtains a comparison result, and feeds it back to the power-on / off circuit through the second output terminal. If the original high-frequency pulse sequence is detected, the first information is sent to the power-on / off circuit; The power on / off circuit receives the first information and turns on the headset; After the power-on is completed, the power-on / off circuit feeds back the second information to the pulse generating circuit; The pulse generating circuit stops sending the high-frequency pulse sequence.

6. The control method according to claim 5, characterized in that: The method further comprises: The first comparator detects the high voltage on VBUS in real time, and when the high voltage is detected, sends a fourth signal to control the first transistor and the second transistor of the pulse generating circuit, so that the first transistor and the second transistor block the pulse from being sent out.

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