Clock Synchronization Method and System for Marine Seismic Exploration

Abstract

The present invention discloses a clock synchronization method and system for marine seismic exploration. This method transmits an external high-speed clock to a sensor, and a phase-locked loop inside the sensor locks the high-speed clock as an internal clock, and uses this internal clock as the sampling clock of an analog-to-digital converter, rather than using the local clock of the sensor as the sampling clock, thereby ensuring that the sampling clocks of all sensors are synchronized from the same source, and thus eliminating the frequency error between different sensors.

Description

Technical Field

[0001] The present invention relates to the field of exploration technology, and particularly to a clock synchronization method and system for marine seismic exploration. Background Art

[0002] The principle of a marine seismic exploration system is to obtain geophysical information data by applying acoustic energy from a sound source to the earth and detecting the seismic energy reflected from the interfaces between different layers in the underground formation.

[0003] In a marine seismic exploration system, an air gun array is usually used as the sound source, and a seismic streamer is used to collect seismic energy. The air gun array and the seismic streamer are generally towed behind a recording vessel, at a depth between six and nine meters in the water. The air gun array is about two hundred meters away from the recording vessel, while the seismic streamer is six to fifteen kilometers long.

[0004] Normally, there are multiple sensors distributed along the seismic streamer inside the seismic streamer, which are used to detect the seismic signals reflected from the formation by the sound source excited by the air gun array, and to transmit the digitalized seismic signals to the on-board indoor recording system.

[0005] Since multiple sensors are distributed in a six- to fifteen-kilometer streamer, and the number can reach 480 to 1200. As the continuous working time increases, the local clock frequencies of each sensor will drift respectively. If the sampling clock for analog-to-digital conversion of each sensor is its internal local clock, it will cause each sensor to collect seismic data at different times, that is, a frequency deviation occurs. This directly leads to a decline in the quality of seismic data. Therefore, it is crucial to synchronize the sampling clocks of multiple sensors in multiple streamers. Summary of the Invention

[0006] In view of the above problems, the present invention is proposed to provide a clock synchronization method and system for marine seismic exploration that overcomes the above problems or at least partially solves the above problems.

[0007] According to one aspect of the present invention, a clock synchronization method for marine seismic exploration is provided. The on-board console is connected to the streamer transmission line, and m-level sensors are distributed on the streamer transmission line. The method includes:

[0008] The on-board console obtains a high-speed clock according to the GNSS signal, and sends the high-speed clock to the first-level sensor on the streamer transmission line in real time through the streamer transmission line;

[0009] While transmitting the high-speed clock to the next-level sensor, the first-level sensor locks the received high-speed clock as the internal clock of the sensor through the clock phase-locked loop inside the sensor, and uses the internal clock as the sampling clock of the analog-to-digital converter inside the sensor;

[0010] Starting from i = 2, the i-th level sensor receives the high-speed clock relayed without delay from the previous level sensor. While transmitting the high-speed clock to the next level sensor, the received high-speed clock is locked as the internal clock of the sensor through the clock phase-locked loop inside the sensor, and the internal clock is used as the sampling clock of the analog-to-digital converter inside the sensor. Assign i = i + 1, and repeat this step until i = m - 1;

[0011] The m-th level sensor receives the high-speed clock relayed without delay from the previous level sensor, locks the received high-speed clock as the internal clock of the sensor through the clock phase-locked loop inside the sensor, and uses the internal clock as the sampling clock of the analog-to-digital converter inside the sensor to complete clock synchronization.

[0012] According to another aspect of the present invention, there is provided a clock synchronization system for marine seismic exploration, including: a shipborne console, a tow cable transmission line connected to the shipborne console, and m-level sensors are distributed on the tow cable transmission line;

[0013] The shipborne console is used to obtain the high-speed clock according to the GNSS signal and transmit the high-speed clock to the first-level sensor on the tow cable transmission line in real time through the tow cable transmission line;

[0014] The first-level sensor is used to lock the received high-speed clock as the internal clock of the sensor through the clock phase-locked loop inside the sensor while transmitting the high-speed clock to the next level sensor, and use the internal clock as the sampling clock of the analog-to-digital converter inside the sensor;

[0015] Starting from i = 2, the i-th level sensor is used to receive the high-speed clock relayed without delay from the previous level sensor, lock the received high-speed clock as the internal clock of the sensor through the clock phase-locked loop inside the sensor while transmitting the high-speed clock to the next level sensor, and use the internal clock as the sampling clock of the analog-to-digital converter inside the sensor. Assign i = i + 1, and repeat this step until i = m - 1;

[0016] The m-th level sensor is used to receive the high-speed clock relayed without delay from the previous level sensor, lock the received high-speed clock as the internal clock of the sensor through the clock phase-locked loop inside the sensor, and use the internal clock as the sampling clock of the analog-to-digital converter inside the sensor to complete clock synchronization.

[0017] According to the solution provided by the present invention, by transmitting an external high-speed clock to the sensor, and locking the high-speed clock as the internal clock by the phase-locked loop inside the sensor, and using the internal clock as the sampling clock of the analog-to-digital converter, instead of using the local clock of the sensor as the sampling clock, it ensures that the sampling clocks of all sensors are synchronized from the same source, thereby eliminating the frequency error between different sensors.

[0018] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the specification. And in order to make the above and other objects, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention are hereinafter specifically exemplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0020] Figure 1 shows a schematic flow chart of a clock synchronization method for marine seismic exploration according to an embodiment of the present invention;

[0021] Figure 2 shows a schematic diagram of a clock synchronization system for marine seismic exploration according to an embodiment of the present invention;

[0022] Figure 3 is a schematic diagram of a sensor. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The exemplary embodiments of the present invention will be described in more detail below with reference to the drawings. Although the exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention can be more thoroughly understood and the scope of the present invention can be fully conveyed to those skilled in the art.

[0024] Figure 1 shows a schematic flow chart of a clock synchronization method for marine seismic exploration according to an embodiment of the present invention. The on-board console is connected to the tow cable transmission line, and m-level sensors are distributed on the tow cable transmission line, such as Figure 1 shown, the method includes the following steps:

[0025] Step S101, the on-board console obtains a high-speed clock according to the GNSS signal and sends the high-speed clock to the first-level sensor on the tow cable transmission line in real time through the tow cable transmission line.

[0026] Specifically, the on-board console obtains a high-speed clock through an indoor GNSS clock reference source device. The indoor GNSS clock reference source device provides a 10 MHz clock interface, and the high-speed clock can be obtained through this 10 MHz clock interface. Optionally, in order to improve the transmission quality, the 10 MHz clock is used as the standard clock source here, and then the high-speed clock is extracted from this standard clock source. For example, a 2 MHz high-speed clock is obtained. After the high-speed clock is extracted, the on-board console transmits the high-speed clock to the first-stage sensor on the tow cable transmission line in real time through the tow cable transmission line. The GNSS signals include: GPS signals, Beidou signals (Compass signals), GLONASS signals, Galileo signals. Here, it is only for illustration and has no restrictive effect.

[0027] Step S102, while the first-stage sensor transmits the high-speed clock to the next-stage sensor, the received high-speed clock is locked as the internal clock of the sensor through the clock phase-locked loop inside the sensor, and the internal clock is used as the sampling clock of the analog-to-digital converter inside the sensor.

[0028] Step S103, starting from i = 2, the i-th stage sensor receives the high-speed clock relayed without delay from the previous-stage sensor. While transmitting the high-speed clock to the next-stage sensor, the received high-speed clock is locked as the internal clock of the sensor through the clock phase-locked loop inside the sensor, and the internal clock is used as the sampling clock of the analog-to-digital converter inside the sensor. Assign i to i + 1, and repeat this step until i = m - 1.

[0029] Step S104, the m-th stage sensor receives the high-speed clock relayed without delay from the previous-stage sensor, locks the received high-speed clock as the internal clock of the sensor through the clock phase-locked loop inside the sensor, and uses the internal clock as the sampling clock of the analog-to-digital converter inside the sensor to complete clock synchronization.

[0030] Each stage of the sensor on the tow cable transmission line is the same. There is a receiving chip, a clock phase-locked loop PLL, and a transmitting chip inside each stage of the sensor. As Figure 3 shown, during the process of realizing clock synchronization, after the receiving chip of each stage of the sensor (except the last stage of the sensor) receives the high-speed clock, it will process it in two paths simultaneously. One path is to relay the received high-speed clock to the next-stage sensor without delay and transmit it directly through the transmitting chip. This transmission is not processed, so the transmission time is negligible. The other path is to lock the high-speed clock as the internal clock through the internal clock phase-locked loop PLL, and use the internal clock as the sampling clock of the analog-to-digital converter inside the sensor. Therefore, the sampling clock of the analog-to-digital converter becomes the high-speed clock latched by the PLL, rather than the local clock inside the sensor.

[0031] The last - stage sensor, after receiving the high - speed clock, locks the received high - speed clock as the internal clock of the sensor through the clock phase - locked loop inside the sensor, and uses the internal clock as the sampling clock of the analog - to - digital converter inside the sensor to complete clock synchronization.

[0032] In this embodiment, the clock transmitted to the next - stage sensor is the clock that has not been processed by the current - stage sensor. Since it is not processed first and then transmitted as in the prior art, the transmission of the high - speed clock between sensors is a delay - free relay transmission. Thus, it can be determined that each sensor synchronously executes locking the received high - speed clock as the internal clock of the sensor and using the internal clock as the sampling clock of the analog - to - digital converter inside the sensor. The acquisition clocks of all sensors are from the same source, thereby ensuring clock synchronization.

[0033] In an alternative embodiment of the present invention, after the high - speed clock is transmitted through multiple - stage sensors, it may become a jittery clock, which may cause the high - speed clock to be unable to be locked by the clock phase - locked loop (PLL) inside the next - stage sensor. Therefore, the method further includes: setting a controller every n stages of sensors on the tow - cable transmission line, transmitting the high - speed clock output by the n - th stage sensor to the next - stage controller connected to the n - th stage sensor. The next - stage controller performs de - jitter processing on the received high - speed clock and transmits the de - jitter - processed high - speed clock to the sensor connected to the next - stage controller.

[0034] Specifically, after every n stages of sensors, the high - speed clock transmitted by the n - th stage sensor is input to the next - stage controller of the n - th stage sensor. After receiving the high - speed clock, the next - stage controller performs de - jitter processing on the received high - speed clock, and then outputs the de - jitter - processed high - speed clock to the next - stage sensor behind it, thereby ensuring that all sensors on the tow - cable transmission line can use the PLL inside them to latch the high - speed clock, that is, lock the high - speed clock as the internal clock of the sensor. The sensor uses the internal clock as the sampling clock of the analog - to - digital converter inside the sensor, so that each sensor can be synchronized with the clock of the indoor clock source, thereby eliminating the frequency error between sensors. Among them, the empirical value of n can be 24. When it is greater than 24, it is very likely that the PLL inside the sensor cannot lock the high - speed clock. In this embodiment, m is much larger than n.

[0035] In an alternative embodiment of the present invention, each sensor using the internal clock as the sampling clock of the analog - to - digital converter inside the sensor can be further realized by the following method: each sensor performs frequency - doubling processing on the internal clock and uses the processed internal clock as the sampling clock of the analog - to - digital converter inside the sensor.

[0036] Specifically, in order to improve the clock stability and reliability, meet the frequency requirements of the sampling clock, and further improve the quality of seismic data collected by the sampling clock based on the analog-to-digital converter, after each sensor locks the high-speed clock to the internal clock of the sensor, it is also necessary to perform frequency doubling processing on the internal clock, multiply the frequency of the internal clock by a preset frequency doubling coefficient according to the frequency doubling requirement to obtain the internal clock after frequency doubling processing, where the frequency of the internal clock is 2 MHz and the frequency of the sampling clock is 4 MHz.

[0037] In an alternative embodiment of the present invention, the method further includes: after each sensor locks the high-speed clock to the internal clock of the sensor, it feeds back the locking status information to the on-board console.

[0038] Specifically, after each sensor successfully locks the high-speed clock to the internal clock of the sensor, it feeds back the locking status information to the on-board console. The locking status information is used to notify the on-board console that the internal clock has been successfully locked, achieving clock synchronization, so that the on-board console can further issue data acquisition commands according to the locking status information to realize seismic data acquisition by each sensor at the same moment.

[0039] In this embodiment, the on-board console can drag multiple tow cable transmission lines, and multiple sensors are distributed on each tow cable transmission line. The on-board console can send the high-speed clock to the first-level sensors on the tow cable transmission line in real time through each tow cable transmission line.

[0040] In an alternative embodiment of the present invention, the method further includes: before the on-board console transmits the high-speed clock through the tow cable transmission line, it sends a clock notification instruction to each level of sensors through the tow cable transmission line. Each level of sensors prepares to receive the high-speed clock according to the clock notification instruction and relays the received high-speed clock without delay. Specifically, after each level of sensors receives the clock notification instruction, it parses the clock notification instruction and transmits it to the next level of sensors until it is transmitted to the last level of sensors. When the clock is not sent, the link between the receiving chip and the sending chip inside the sensor is disconnected. Each level of sensors knows that the on-board console is about to transmit the high-speed clock by parsing the instruction, so the link between the receiving chip and the sending chip inside the sensor is connected.

[0041] In this embodiment, the parsing of the GNSS external time reference signal into a high-speed clock is completed indoors on the on-board console and sent to the underwater sensors through the tow cable transmission line, so that there is no need for the sensors to parse the GNSS external time reference signal. Parsing the GNSS external time reference signal indoors into a high-speed clock, rather than time message information, has a fast transmission rate and can be directly broadcast to each sensor in each tow cable transmission line, providing a long-term stable clock.

[0042] The solution provided by the present invention is to transmit an external high-speed clock to the sensor, and the phase-locked loop inside the sensor locks the high-speed clock as the internal clock, and uses this internal clock as the sampling clock of the analog-to-digital converter, rather than using the local clock of the sensor as the sampling clock, thereby ensuring that the sampling clocks of all sensors are synchronized from the same source, and thus eliminating the frequency error between different sensors.

[0043] Figure 2 FIG. shows a schematic structural diagram of a clock synchronization system for marine seismic exploration according to an embodiment of the present invention. As Figure 2 shown, the system includes: a shipborne console 201, a tow cable transmission line 202 connected to the shipborne console, and m-level sensors 203 are distributed on the tow cable transmission line;

[0044] The shipborne console is used to obtain a high-speed clock according to the GNSS signal, and transmit the high-speed clock to the first-level sensor on the tow cable transmission line in real time through the tow cable transmission line;

[0045] The first-level sensor is used to lock the received high-speed clock as the internal clock of the sensor through the clock phase-locked loop inside the sensor while transmitting the high-speed clock to the next-level sensor, and use the internal clock as the sampling clock of the analog-to-digital converter inside the sensor;

[0046] Starting from i = 2, the i-th level sensor is used to receive the high-speed clock relayed without delay from the previous-level sensor, lock the received high-speed clock as the internal clock of the sensor through the clock phase-locked loop inside the sensor while transmitting the high-speed clock to the next-level sensor, and use the internal clock as the sampling clock of the analog-to-digital converter inside the sensor, assign i to i + 1, and repeat this step until i = m - 1;

[0047] The m-th level sensor is used to receive the high-speed clock relayed without delay from the previous-level sensor, lock the received high-speed clock as the internal clock of the sensor through the clock phase-locked loop inside the sensor at the same time, and use the internal clock as the sampling clock of the analog-to-digital converter inside the sensor to complete clock synchronization.

[0048] Each level of sensor on the tow cable transmission line is the same, and there is a receiving chip, a clock phase-locked loop PLL, and a transmitting chip inside each level of sensor. As Figure 3As shown in the figure, during the process of achieving clock synchronization, after receiving the high-speed clock, the receiving chip of each level of sensor (except the last level of sensor) will process it in two paths simultaneously. One path is to relay the received high-speed clock to the next level of sensor without delay and directly transmit it through the transmitting chip. Since this transmission is not processed, the transmission time is negligible. The other path is to lock the high-speed clock as the internal clock through the internal clock phase-locked loop (PLL), and use the internal clock as the sampling clock of the analog-to-digital converter inside the sensor. Therefore, the sampling clock of the analog-to-digital converter becomes the high-speed clock latched by the PLL, rather than the local clock inside the sensor.

[0049] For the last level of sensor, after receiving the high-speed clock, it locks the received high-speed clock as the internal clock of the sensor through the internal clock phase-locked loop of the sensor, and uses the internal clock as the sampling clock of the analog-to-digital converter inside the sensor to complete clock synchronization.

[0050] In this embodiment, the clock transmitted to the next level of sensor is the clock that has not been processed by the current level of sensor. Since it is not processed first and then transmitted as in the prior art, the transmission of the high-speed clock between sensors is a non-delay relay transmission. Therefore, it can be determined that each sensor synchronously executes locking the received high-speed clock as the internal clock of the sensor and using the internal clock as the sampling clock of the analog-to-digital converter inside the sensor. The acquisition clocks of all sensors are from the same source, thus ensuring clock synchronization.

[0051] Optionally, a controller is set every n levels of sensors on the tow cable transmission line, and the high-speed clock output by the nth level of sensor is transmitted to the next-level controller connected to the nth level of sensor. The next-level controller performs de-jitter processing on the received high-speed clock and transmits the de-jitter processed high-speed clock to the sensor connected to this next-level controller.

[0052] Specifically, after every n levels of sensors, the high-speed clock transmitted by the nth level of sensor is input to the next-level controller of the nth level of sensor. After receiving the high-speed clock, the next-level controller performs de-jitter processing on the received high-speed clock, and then outputs the de-jitter processed high-speed clock to the next-level sensor behind it, so as to ensure that all sensors on the tow cable transmission line can use the PLL inside them to latch the high-speed clock, that is, lock the high-speed clock as the internal clock of the sensor, and the sensor uses the internal clock as the sampling clock of the analog-to-digital converter inside the sensor, so that each sensor can be synchronized with the clock of the indoor clock source, thereby eliminating the frequency error between sensors. Among them, the empirical value of n can be 24. When it is greater than 24, it is very likely that the PLL inside the sensor cannot lock the high-speed clock. In this embodiment, m is much larger than n.

[0053] Optionally, each sensor is further configured to: multiply the frequency of the internal clock, and use the processed internal clock as the sampling clock of the analog-to-digital converter inside the sensor.

[0054] Optionally, the frequency of the internal clock is 2 MHz, and the frequency of the sampling clock is 4 MHz.

[0055] Optionally, each sensor is further configured to: after locking the high-speed clock as the internal clock of the sensor, feedback the locking status information to the on-board console.

[0056] In an optional embodiment of the present invention, before transmitting the high-speed clock through the tow cable transmission line, the on-board console sends a clock notification instruction to each level of sensors through the tow cable transmission line. Each level of sensors prepares to receive the high-speed clock according to this clock notification instruction and relays the received high-speed clock without delay. Specifically, after receiving the clock notification instruction, each level of sensors parses the clock notification instruction and transmits it to the next level of sensors until it is transmitted to the last level of sensors. When not sending the clock, the link between the receiving chip and the transmitting chip inside the sensor is disconnected. Each level of sensors knows through parsing the instruction that the on-board console is about to transmit the high-speed clock. Therefore, the link between the receiving chip and the transmitting chip inside the sensor is connected.

[0057] The solution provided by the present invention transmits an external high-speed clock to the sensor, and the phase-locked loop inside the sensor locks the high-speed clock as the internal clock, and uses this internal clock as the sampling clock of the analog-to-digital converter, rather than using the local clock of the sensor as the sampling clock. Thus, it is ensured that the sampling clocks of all sensors are synchronized from the same source, thereby eliminating the frequency error between different sensors.

[0058] The algorithms or displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings based herein. The structure required to construct such systems will be apparent from the above description. In addition, the embodiments of the present invention are not directed to any specific programming language. It should be understood that the content of the present invention described herein can be implemented using various programming languages, and the description of the specific language above is for disclosing the best mode of the present invention.

[0059] In the specification provided herein, a large number of specific details are set forth. However, it can be understood that the embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures, and technologies have not been shown in detail so as not to obscure the understanding of this specification.

[0060] Similarly, it should be understood that, in order to streamline the present invention and assist in understanding one or more of the various inventive aspects, in the foregoing description of the exemplary embodiments of the present invention, the various features of the embodiments of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the disclosed method should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, the inventive aspects lie in less than all the features of the single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate embodiment of the present invention.

[0061] Those skilled in the art can understand that the modules in the devices in the embodiments can be adaptively changed and disposed in one or more devices different from the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all the features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) can be replaced by an alternative feature that provides the same, equivalent, or similar purpose.

[0062] In addition, those skilled in the art can understand that although some of the embodiments herein include certain features included in other embodiments rather than other features, the combination of the features of different embodiments means that it is within the scope of the present invention and forms different embodiments. For example, in the following claims, any one of the claimed embodiments can be used in any combination.

[0063] The various component embodiments of the present invention can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art should understand that a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components according to the embodiments of the present invention. The present invention can also be implemented as a device or apparatus program (for example, a computer program and a computer program product) for executing part or all of the methods described herein. Such a program for implementing the present invention can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0064] It should be noted that the above embodiments illustrate the present invention rather than limit the present invention, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim listing several devices, several of these devices may be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words may be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be construed as limiting the order of execution.

Claims

1. A clock synchronization method for marine seismic exploration, where an on-board console is connected to a towed cable transmission line, and m-level sensors are distributed on the towed cable transmission line. The method includes: The on-board console obtains a high-speed clock according to the GNSS signal, and sends the high-speed clock to the first-level sensor on the towed cable transmission line in real time through the towed cable transmission line; While transmitting the high-speed clock to the next-level sensor, the first-level sensor locks the received high-speed clock as the internal clock of the sensor through the clock phase-locked loop inside the sensor, and uses the internal clock as the sampling clock of the analog-to-digital converter inside the sensor; Starting from i = 2, the i-th level sensor receives the high-speed clock relayed without delay from the previous-level sensor. While transmitting the high-speed clock to the next-level sensor, the i-th level sensor locks the received high-speed clock as the internal clock of the sensor through the clock phase-locked loop inside the sensor, and uses the internal clock as the sampling clock of the analog-to-digital converter inside the sensor. Assign i to i + 1, and repeat this step until i = m - 1; The m-th level sensor receives the high-speed clock relayed without delay from the previous-level sensor, locks the received high-speed clock as the internal clock of the sensor through the clock phase-locked loop inside the sensor, and uses the internal clock as the sampling clock of the analog-to-digital converter inside the sensor to complete clock synchronization; Among them, the method further includes: setting a controller every n levels of sensors on the towed cable transmission line, transmitting the high-speed clock output by the n-th level sensor to the next-level controller connected to the n-th level sensor, and the next-level controller performs de-jitter processing on the received high-speed clock and transmits the de-jitter processed high-speed clock to the sensor connected to the next-level controller.

2. The method according to claim 1, wherein, Each sensor using the internal clock as the sampling clock of the analog-to-digital converter inside the sensor further includes: Each sensor performs frequency doubling processing on the internal clock and uses the processed internal clock as the sampling clock of the analog-to-digital converter inside the sensor.

3. The method according to claim 2, wherein The frequency of the internal clock is 2MHz, and the frequency of the sampling clock is 4MHz.

4. The method according to claim 1 or 2, wherein The method further includes: after each sensor locks the high-speed clock as the internal clock of the sensor, it feeds back the lock status information to the on-board console.

5. A clock synchronization system for marine seismic exploration, comprising: An on-board console, a towed cable transmission line connected to the on-board console, and m-level sensors are distributed on the towed cable transmission line; The on-board console is used to obtain a high-speed clock according to the GNSS signal and send the high-speed clock to the first-level sensor on the towed cable transmission line in real time through the towed cable transmission line; The first-level sensor is used to lock the received high-speed clock as the internal clock of the sensor through the clock phase-locked loop inside the sensor while transmitting the high-speed clock to the next-level sensor, and use the internal clock as the sampling clock of the analog-to-digital converter inside the sensor; Starting from i = 2, the i-th level sensor is used to receive the high-speed clock relayed without delay from the previous level sensor. While transmitting the high-speed clock to the next level sensor, the received high-speed clock is locked as the internal clock of the sensor through the clock phase-locked loop inside the sensor, and the internal clock is used as the sampling clock of the analog-to-digital converter inside the sensor. Assign i = i + 1, and repeat this step until i = m - 1; The m-th level sensor is used to receive the high-speed clock relayed without delay from the previous level sensor, lock the received high-speed clock as the internal clock of the sensor through the clock phase-locked loop inside the sensor, and use the internal clock as the sampling clock of the analog-to-digital converter inside the sensor to complete clock synchronization; Among them, a controller is set every n-level sensors on the tow cable transmission line, and the high-speed clock output by the n-th level sensor is transmitted to the next-level controller connected to the n-th level sensor. The next-level controller performs de-jitter processing on the received high-speed clock and transmits the de-jitter processed high-speed clock to the sensor connected to this next-level controller.

6. The system according to claim 5, wherein Each sensor is further used for: performing frequency doubling processing on the internal clock and using the processed internal clock as the sampling clock of the analog-to-digital converter inside the sensor.

7. The system according to claim 6, wherein, The frequency of the internal clock is 2 MHz, and the frequency of the sampling clock is 4 MHz.

8. The system according to claim 5 or 6, wherein, Each sensor is further used for: after locking the high-speed clock as the internal clock of the sensor, feeding back the locking status information to the on-board console.

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