Method for manufacturing a cis

Abstract

The application discloses a CIS manufacturing method, comprising the following steps: providing a substrate, wherein the substrate comprises a first area, a second area and a third area, the first area is used for forming a clamping photodiode, the second area is used for forming a logic device, and the third area is used for forming a CIS; forming a first oxide layer on the substrate; forming a first gate on the first oxide layer of the second area, and the first gate is a gate of the logic device; covering photoresist on other areas except the second area; forming a first side wall on both sides of the first gate; forming a second side wall outside the first side wall; and removing the photoresist. In the manufacturing process of the CIS containing the clamping photodiode, the other areas except the area where the logic device is located are covered with the photoresist, so that the damage of the wafer surface caused by the etching process thinning the first oxide layer in the process of forming the side wall of the gate of the logic device is avoided, and the white noise of the CIS is reduced to a certain extent.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and specifically to a method for manufacturing a CIS (CMOS Image Sensor). Background Technology

[0002] Complementary metal oxide semiconductor (CIS) image sensors are image sensors made using CMOS devices. Due to their advantages such as high integration, low power supply voltage, and low technical barriers, they are widely used in fields such as photography and videography, security systems, smartphones, and medical electronics.

[0003] During the fabrication of CIS, processes such as plasma and wet etching can damage the surface of the wafer, leading to dark current and affecting its performance. In view of this, related technologies introduce pinned-photodiodes (PDs) on the CIS wafer to solve the dark current problem.

[0004] refer to Figures 1 to 3 This illustrates a schematic diagram of the fabrication process of a CIS including a clamped photodiode, as provided in the related art. For example, such as... Figure 1 As shown, the substrate 110 includes a first region 101 and a second region 102. Figure 1 , Figure 2 and Figure 3 (The area for forming the CIS is not shown in the diagram). The first region 101 is used to form a clamping photodiode, and the second region 102 is used to form a logic device. An oxide layer 120 is formed on the substrate 110, and the gate 131 of the logic device is formed on the oxide layer of the second region 102; as shown... Figure 2 As shown, first sidewalls 141 are formed on both sides of the gate 131. During the formation of the first sidewalls 141, the oxide layer 120 is thinned due to the need for etching; as Figure 3 As shown, after the second sidewall 142 is formed on the outside of the first sidewall 141, an oxide thickening oxide layer 120 is deposited.

[0005] For CIS, the white noise problem has always been an important research point for its performance improvement. The performance of white noise directly determines the performance of CIS. The root cause of white noise is the damage to the wafer surface caused by the process. Since the oxide layer is thinned during the formation of the first sidewall, plasma and other substances in the process can damage the wafer surface, resulting in dark current and causing white noise in the device. Summary of the Invention

[0006] This application provides a method for fabricating a CIS (CMOS Image Sensor), which can solve the problem of high white noise caused by the fabrication method of CIS including clamped photodiodes provided in the related art. The method includes...

[0007] A substrate is provided, the substrate including a first region, a second region and a third region, the first region being used to form a clamping photodiode, the second region being used to form a logic device, the third region being used to form a CIS, a first oxide layer being formed on the substrate, a first gate being formed on the first oxide layer in the second region, the first gate being the gate of the logic device;

[0008] Cover the areas other than the second region with optical resist;

[0009] First sidewalls are formed on both sides of the first gate;

[0010] A second sidewall is formed on the outside of the first sidewall;

[0011] Remove light resistance.

[0012] In some embodiments, after the first sidewall is formed, the thickness of the first oxide layer in the other regions is greater than 80 angstroms.

[0013] In some embodiments, the first sidewall includes a second oxide layer.

[0014] In some embodiments, the second sidewall includes a nitrided layer.

[0015] In some embodiments, after removing the photoresist, the method further includes:

[0016] The clamping photodiode is formed in the first region;

[0017] The clamping photodiode includes a second gate formed on the substrate, and a doped region, a first heavily doped region, and a second heavily doped region formed in the substrate;

[0018] The doped region and the first heavily doped region are located on opposite sides of the bottom of the second gate and are in contact with the bottom of the second gate. The second heavily doped region is located on the same side as the doped region and is located above the doped region. The impurity concentration in the first heavily doped region and the second heavily doped region is greater than the impurity concentration in the doped region.

[0019] In some embodiments, the impurity types in the doped region and the first heavily doped region are the same, while the impurity types in the doped region and the second heavily doped region are different.

[0020] In some embodiments, the substrate comprises, from bottom to top, a silicon substrate and an epitaxial layer formed on the silicon substrate, wherein the doped region, the first heavily doped region and the second heavily doped region are formed in the epitaxial layer.

[0021] The technical solution of this application has at least the following advantages:

[0022] By covering areas other than the logic device area with photoresist after forming the gate of the logic device during the fabrication of a CIS containing clamped photodiodes, damage to the wafer surface caused by the etching process thinning the first oxide layer during the formation of the sidewall of the logic device gate is avoided. This reduces the white noise of the CIS to a certain extent and improves the reliability of the device. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figures 1 to 3 This is a schematic diagram of the fabrication process of a CIS containing a clamping photodiode provided in related technologies;

[0025] Figure 4 This is a flowchart of a method for creating a CIS provided in an exemplary embodiment of this application;

[0026] Figures 5 to 7 This is a schematic diagram illustrating the manufacturing process of a CIS provided in an exemplary embodiment of this application;

[0027] Figure 8 This is a cross-sectional schematic diagram of a clamped photodiode provided in an exemplary embodiment of this application. Detailed Implementation

[0028] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0031] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0032] refer to Figure 4 It illustrates a flowchart of a method for manufacturing a CIS provided in an exemplary embodiment of this application, such as... Figure 4 As shown, the method includes:

[0033] Step S1: A substrate is provided, which includes a first region, a second region and a third region. The first region is used to form a clamped photodiode, the second region is used to form a logic device, and the third region is used to form a CIS. A first oxide layer is formed on the substrate, and a first gate is formed on the first oxide layer in the second region. The first gate is the gate of the logic device.

[0034] refer to Figure 5 This illustrates a cross-sectional view after the first gate is formed in the second region. For example, as shown... Figure 5 As shown, the substrate 510 includes a first region 501, a second region 502, and a third region ( Figure 5 (Not shown in the image), the first region 501 is used to form a clamping photodiode, the second region 502 is used to form a logic device, and the third region is used to form a CIS. A first oxide layer 520 is formed on the substrate 510, and a first gate 531 is formed on the first oxide layer 520 in the second region 502. The first gate 531 is the gate of the logic device. The thickness of the first oxide layer 520 is greater than 80 angstroms.

[0035] Step S2: Cover the areas other than the second region with optical resist.

[0036] Step S3: Form first sidewalls on both sides of the first gate.

[0037] refer to Figure 6 It shows a schematic cross-sectional view after the first sidewall has been formed. For example, as shown... Figure 6 As shown, photoresist 600 can be used to cover areas other than the second region 502 using a photolithography process, exposing the second region 502. First sidewalls 541 are formed on both sides of the first gate 531. Since etching is required during the formation of the first sidewalls 541, the first oxide layer 520 in the areas of the second region 502 other than the areas below the first gate 531 and the first sidewalls 541 is thinned. The first sidewalls 541 include a second oxide layer. Because the other areas are covered by photoresist 600, the thickness of the first oxide layer 520 in the other areas remains unchanged after the formation of the first sidewalls 541, still greater than 80 angstroms.

[0038] Step S4: Form a second side wall on the outside of the first side wall.

[0039] Step S5: Remove photoresist.

[0040] refer to Figure 7 It shows a schematic cross-sectional view after the second sidewall has been formed. For example, as shown... Figure 7 As shown, after the second sidewall 542 is formed on the outside of the first sidewall 541, the second oxide layer 520 of the second region 502 can be thickened to a certain extent, and then the photoresist 600 is removed by the ashing process.

[0041] For example, after step S5, the method further includes: forming a clamping photodiode in the first region 501.

[0042] like Figure 8 As shown, the clamped photodiode includes a second gate 532 formed on a substrate 510, and a doped region 511, a first heavily doped region 512, and a second heavily doped region 513 formed in the substrate 510.

[0043] Doped region 511 and first heavily doped region 512 are located on opposite sides of the bottom of second gate 531 and are in contact with the bottom of second gate 532. Second heavily doped region 513 is located on the same side as doped region 511 and is located above doped region 511. The impurity concentration in first heavily doped region 512 and second heavily doped region 513 is greater than the impurity concentration in doped region 511. The impurity types in doped region 511 and first heavily doped region 512 are the same, while the impurity types in doped region 511 and second heavily doped region 513 are different.

[0044] In some embodiments, the substrate 510 includes, from bottom to top, a silicon substrate and an epitaxial layer formed on the silicon substrate. A doped region 511, a first heavily doped region 512, and a second heavily doped region 513 are formed in the epitaxial layer. The doped region 511 and the epitaxial layer have the same type of impurities, but the impurities in the silicon substrate are different.

[0045] If the impurity type in doped region 511 is N (negative), then the impurity type in the first doped region 512 is N-type, the impurity type in the second doped region 513 is P (positive), the impurity type in the epitaxial layer is N-type, and the impurity type in the silicon substrate is P-type; if the impurity type in doped region 511 is P-type, then the impurity type in the first doped region 512 is P-type, the impurity type in the second doped region 513 is N-type, the impurity type in the epitaxial layer is P-type, and the impurity type in the silicon substrate is N-type.

[0046] In summary, in the embodiments of this application, by covering the area other than the area where the logic device is located with photoresist after forming the gate of the logic device during the fabrication of the CIS including the clamped photodiode, damage to the wafer surface caused by the etching process thinning the first oxide layer during the formation of the sidewall of the gate of the logic device is avoided, thereby reducing the white noise of the CIS to a certain extent and improving the reliability of the device.

[0047] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for manufacturing a CIS, characterized in that, include: A substrate is provided, the substrate including a first region, a second region and a third region, the first region being used to form a clamping photodiode, the second region being used to form a logic device, the third region being used to form a CIS, a first oxide layer being formed on the substrate, a first gate being formed on the first oxide layer in the second region, the first gate being the gate of the logic device; Cover the areas other than the second region with optical resist; A first sidewall is formed on both sides of the first gate, and after the first sidewall is formed, the thickness of the first oxide layer in the other regions is greater than 80 angstroms; A second sidewall is formed on the outside of the first sidewall; Remove light resistance.

2. The method according to claim 1, characterized in that, The first sidewall includes a second oxide layer.

3. The method according to claim 2, characterized in that, The second sidewall includes a nitrided layer.

4. The method according to any one of claims 1 to 3, characterized in that, After removing the photoresist, the method further includes: The clamping photodiode is formed in the first region; The clamping photodiode includes a second gate formed on the substrate, and a doped region, a first heavily doped region, and a second heavily doped region formed in the substrate; The doped region and the first heavily doped region are located on opposite sides of the bottom of the second gate and are in contact with the bottom of the second gate. The second heavily doped region is located on the same side as the doped region and is located above the doped region. The impurity concentration in the first heavily doped region and the second heavily doped region is greater than the impurity concentration in the doped region.

5. The method according to claim 4, characterized in that, The impurity types in the doped region and the first heavily doped region are the same, while the impurity types in the doped region and the second heavily doped region are different.

6. The method according to claim 5, characterized in that, The substrate, from bottom to top, includes a silicon substrate and an epitaxial layer formed on the silicon substrate, wherein the doped region, the first heavily doped region and the second heavily doped region are formed in the epitaxial layer.

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