Silicon Carbide MOS Structure Intelligent Thermal Measurement Chip Based on Integrated PIN and Its Layout Structure

Abstract

The present invention discloses a silicon carbide MOS structure intelligent thermal measurement chip based on an integrated PIN and its layout structure, including a source electrode, a cathode, a gate electrode, a first P+ implantation region, a first N+ implantation region, a first P well region, a second P+ implantation region, a second N+ implantation region, an N-epitaxial region, an N+ substrate region, a drain electrode, a gate oxide layer, a second P well region, a passivation layer, a source contact, an N+ source region, and a drain contact. The present invention can integrate a PIN diode in a silicon carbide MOSFET structure, and can monitor the chip temperature in real time through the PIN diode, thereby improving the reliability of the device.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and particularly relates to an intelligent thermal measurement chip based on an integrated PIN silicon carbide MOS structure and its layout structure. Background Art

[0002] In recent years, with the continuous development of power electronic systems, higher requirements have been put forward for power devices in the systems. As a commercially available device in recent years, silicon carbide (SiC) MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices have great potential to replace existing IGBTs (Insulated Gate Bipolar Transistors) in terms of on-resistance, switching time, switching loss, and heat dissipation performance.

[0003] However, the silicon carbide MOSFET devices in the prior art still cannot overcome the adverse effects brought about by temperature changes. For example, the mismatch in the coefficient of thermal expansion of the materials constituting the device package will generate thermal stress during production, manufacturing, testing, etc., which may lead to failure; the drastic temperature fluctuations in different working states and environments will cause fatigue fracture of the packaging materials; the change in temperature will also cause changes in the current gain of transistors and integrated circuits, and further affect the electrical signal transmission characteristics by causing changes in capacitance, resistance, etc. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides an intelligent thermal measurement chip based on an integrated PIN silicon carbide MOS structure and its layout structure. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0005] A silicon carbide MOS structure intelligent thermal measurement chip based on an integrated PIN, the chip comprising: a source electrode (1), a cathode (2), a gate electrode (3), a first P+ implantation region (4), a first N+ implantation region (5), a first P-well region (6), a second P+ implantation region (7), a second N+ implantation region (8), an N-epitaxial region (9), an N+ substrate region (10), a drain electrode (11), a gate oxide layer (12), a second P-well region (13), a passivation layer (14), a source contact (15), an N+ source region (16), and a drain contact (17); wherein, the drain contact (17) is located above the drain electrode (11); the N+ substrate region (10) is located above the drain contact (17); the N-epitaxial region (9) is located above the N+ substrate region (10); the first P-well region (6) is embedded in one side above the N-epitaxial region (9); the second P-well region (13) is embedded in the other side above the N-epitaxial region (9); the first P+ implantation region (4) is embedded in one side above the first P-well region (6); the first N+ implantation region (5) is embedded in the other side above the first P-well region (6); the second P+ implantation region (7) is embedded in one side above the second P-well region (13); the N+ source region (16) is embedded in the other side above the second P-well region (13); the second N+ implantation region (8) is located between the second P+ implantation region (7) and the N+ source region (16); the gate oxide layer (12) is located above the N-epitaxial region (9); the passivation layer (14) is located in one side above the gate oxide layer (12); the gate electrode (3) is located in the other side above the gate oxide layer (12); the cathode (2) is located above the first P+ implantation region (4), and the vertical part is embedded in the passivation layer (14) and the gate oxide layer (12), and the horizontal part is located above the passivation layer (14); the source electrode (1) includes a first source electrode, a second source electrode, and a third source electrode; the structure of the source electrode (1) includes a vertical part and a horizontal part, wherein the width of the horizontal part is greater than the width of the vertical part; the first source electrode is located above the first N+ implantation region (5), and the vertical part is embedded in the passivation layer (14) and the gate oxide layer (12), and the horizontal part is located above the passivation layer (14); the second source electrode is located on one side above the second N+ implantation region (8), and the vertical part is embedded in a partial region of the passivation layer (14), and the horizontal part is located above the passivation layer (14); the second source electrode is located on the other side above the second N+ implantation region (8), and the vertical part is embedded in a partial region of the passivation layer (14), and the horizontal part is located above the passivation layer (14); the vertical parts of the second source electrode and the third source electrode are in contact; the source contact (15) is located above the second N+ implantation region (8), and is located below the vertical parts of the second source electrode and the third source electrode;The gate (3) is located between the first source and the second source and is embedded below the passivation layer (14), and its lower surface is in contact with the gate oxide layer (12); wherein, the first P+ implantation region (4), the first N+ implantation region (5) and the first P well region (6) constitute the cell of the PIN diode; the second P+ implantation region (7), the second N+ implantation region (8), the N+ source region (16), the second P well region (13), the N-epitaxial region (9), the N+ substrate region (10), the drain (11) and the drain contact (17) constitute the MOSFET cell region.

[0006] In one embodiment of the present invention, the interface between the cathode (2) and the first P+ implantation region (5) is an ohmic contact.

[0007] In one embodiment of the present invention, the interfaces between the source (1) and the first P+ implantation region (4), the second N+ implantation region (7) and the second P+ implantation region (8) are ohmic contacts.

[0008] Advantages of the present invention:

[0009] The present invention can integrate a PIN diode in a silicon carbide MOSFET structure, and can improve the reliability of the device by monitoring the chip temperature in real time through the PIN diode.

[0010] The present invention will be further described in detail below with reference to the drawings and embodiments. Description of the Drawings

[0011] Figure 1 is a schematic structural diagram of a silicon carbide MOS structure intelligent thermal measurement chip based on integrated PIN provided by an embodiment of the present invention;

[0012] Figure 2 is a layout structural diagram of a silicon carbide MOS structure intelligent thermal measurement chip based on integrated PIN provided by an embodiment of the present invention. Detailed Embodiments

[0013] The present invention will be further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0014] Embodiment 1

[0015] Please refer to Figure 1 , Figure 1It is a schematic structural diagram of an intelligent thermal measurement chip structure based on an integrated PIN silicon carbide MOS structure provided by an embodiment of the present invention. The chip includes: a source electrode (1), a cathode (2), a gate electrode (3), a first P+ implantation region (4), a first N+ implantation region (5), a first P-well region (6), a second P+ implantation region (7), a second N+ implantation region (8), an N-epitaxial region (9), an N+ substrate region (10), a drain electrode (11), a gate oxide layer (12), a second P-well region (13), a passivation layer (14), a source electrode contact (15), an N+ source region (16), and a drain electrode contact (17).

[0016] The drain electrode contact (17) is located above the drain electrode (11).

[0017] The N+ substrate region (10) is located above the drain electrode contact (17).

[0018] The N-epitaxial region (9) is located above the N+ substrate region (10).

[0019] The first P-well region (6) is embedded on one side above the N-epitaxial region (9).

[0020] The second P-well region (13) is embedded on the other side above the N-epitaxial region (9).

[0021] The first P+ implantation region (4) is embedded on one side above the first P-well region (6).

[0022] The first N+ implantation region (5) is embedded on the other side above the first P-well region (6).

[0023] The second P+ implantation region (7) is embedded on one side above the second P-well region (13).

[0024] The N+ source region (16) is embedded on the other side above the second P-well region (13).

[0025] The second N+ implantation region (8) is located between the second P+ implantation region (7) and the N+ source region (16).

[0026] The gate oxide layer (12) is located above the N-epitaxial region (9).

[0027] The passivation layer (14) is located on one side above the gate oxide layer (12).

[0028] The gate electrode (3) is located on the other side above the gate oxide layer (12).

[0029] The cathode (2) is located above the first P+ implantation region (4), and its vertical part is embedded in the passivation layer (14) and the gate oxide layer (12), while its horizontal part is located above the passivation layer (14).

[0030] The source electrode (1) includes a first source electrode, a second source electrode, and a third source electrode.

[0031] The structure of the source electrode (1) includes a vertical part and a horizontal part, where the width of the horizontal part is greater than that of the vertical part.

[0032] The first source electrode is located above the first N+ implantation region (5), and its vertical part is embedded in the passivation layer (14) and the gate oxide layer (12), while its horizontal part is located above the passivation layer (14).

[0033] The second source electrode is located on one side above the second N+ implantation region (8), and its vertical part is embedded in a partial region of the passivation layer (14), while its horizontal part is located above the passivation layer (14).

[0034] The second source electrode is located on the other side above the second N+ implantation region (8), and its vertical part is embedded in a partial region of the passivation layer (14), while its horizontal part is located above the passivation layer (14).

[0035] The vertical parts of the second source electrode and the third source electrode are in contact.

[0036] The source contact (15) is located above the second N+ implantation region (8) and below the vertical parts of the second source electrode and the third source electrode.

[0037] The gate electrode (3) is located between the first source electrode and the second source electrode and is embedded below the passivation layer (14), and its lower surface is in contact with the gate oxide layer (12).

[0038] The first P+ implantation region (4), the first N+ implantation region (5), and the first P-well region (6) form a cell of the PIN diode.

[0039] The second P+ implantation region (7), the second N+ implantation region (8), the N+ source region (16), the second P-well region (13), the N-epitaxial region (9), the N+ substrate region (10), the drain electrode (11), and the drain contact (17) form a cell region of the MOSFET.

[0040] Optionally, the interface between the cathode (2) and the first P+ implantation region (5) is an ohmic contact.

[0041] Optionally, the interfaces between the source electrode (1) and the first P+ implantation region (4), the second N+ implantation region (7), and the second P+ implantation region (8) are ohmic contacts.

[0042] Optionally, the depth of the first P-well region is 1.1 μm and the width is 5 μm; the first P-well region (6) is uniformly doped with a doping concentration of 5×10 16 cm -3 ; the depth of the second P-well region (13) is 1.1 μm and the width is 6.2 μm; the second P-well region (13) is uniformly doped with a doping concentration of 5×10 16 cm -3 .

[0043] Optionally, the depth of the first N+ implantation region (5) is the same as the depth of the second N+ implantation region (7).

[0044] Optionally, the depth of the first N+ implantation region (5) is 0.2 μm, the width is 1.7 μm, and its doping concentration is 5×10 19 cm -3 ; the depth of the second N+ implantation region (7) is 0.2 μm, the width is 1.8 μm, and its doping concentration is 5×10 19 cm -3 .

[0045] Optionally, the depth of the second P+ implantation region (7) is the same as the depth of the first P+ implantation region (4).

[0046] Optionally, the depths of the first P+ implantation region (4) and the second P+ implantation region (7) are 0.2 μm, and the doping concentration is 5×10 19 cm -3 ; the width of the first P+ implantation region (4) is 1.5 μm, and the width of the second P+ implantation region (7) is 1.5 μm.

[0047] Optionally, the distance between the PIN diode cell and the MOSFET cell region is 1.2 μm.

[0048] That is, the distance between the first P-well region (6) and the second P-well region (13) is 1.2 μm.

[0049] In the prior art, in a MOSFET, since the current flows from the source to the drain, as the point where the current is emitted, the source is prone to current concentration, resulting in an increase in the temperature at the source end, reducing the reliability of the device, and seriously, the device may be burned out. Through the present invention, an ohmic contact is formed between the first N+ implantation region and the source, and the distance from the first P+ implantation region is 0.8 μm. At this time, the PIN diode and the source are integrated in a cell, and the PIN diode is directly in contact with the measured target, which can effectively exclude external interference, thereby accurately monitoring the temperature inside the device.

[0050] In addition, in the present invention, the PIN diodes are evenly distributed around the source, and the distance between the cells of the PIN diodes and the cells of the MOSFET is 1.2 μm in the X, Y, and Z directions and is evenly distributed. In this way, it can effectively ensure that the device will not break down locally in advance, and improve the breakdown voltage of the device. At the same time, the uniform distribution of the PIN diodes can effectively monitor the temperature of the source, prevent the device from being damaged due to excessive temperature, and improve the reliability of the device.

[0051] In summary, the present invention introduces a PIN diode structure into a silicon carbide MOSFET. By utilizing the temperature sensitivity of the diode, the temperature inside the silicon carbide MOSFET device can be effectively monitored and tested by calculating the current flowing through the PIN diode, which is conducive to the system for timely control and protection, preventing the device performance from being reduced or even the device being damaged due to excessive temperature, thereby improving the reliability of the device.

[0052] Embodiment 2

[0053] Please refer to Figure 2 , Figure 2 which is a schematic layout structure diagram of an intelligent thermal measurement chip based on an integrated PIN silicon carbide MOS structure provided by the second embodiment of the present invention. The layout structure includes:

[0054] MOSFET cell region (18), gate electrode region (19), cell of PIN diode (20), source electrode region (21), and cathode region (22).

[0055] Optionally, the PIN diode cells (20) are evenly distributed in the middle of the source electrode region (21) and are connected to the cathode region (22).

[0056] Embodiment 3

[0057] The third embodiment of the present invention provides a method for manufacturing an intelligent thermal measurement chip based on an integrated PIN silicon carbide MOS structure. The method includes:

[0058] Step a: An N-epitaxial region is formed on the N+ substrate region by epitaxial growth.

[0059] Step b: Conduct initial oxidation, photolithography, and field region boron ion implantation on the N-epitaxial layer to form the first P-well region and the second P-well region, i.e., well region formation.

[0060] Step c: Deposit Si3N4 and perform the next photolithography to lithographically pattern the active region, field oxide, photolithography, and again field oxide. At this time, perform gate oxidation, and then start voltage adjustment to grow the gate oxide layer.

[0061] Step d: Deposit polysilicon, etch the gates of the MOSFETs, use photoresist as a mask, and through phosphorus ion implantation and drive-in, form the first N+ implantation region and the second N+ implantation region; through boron ion implantation, form the first P+ implantation region and the second P+ implantation region.

[0062] Step e: Deposit phosphosilicate glass, perform photolithography, etch holes, and reflux the deposited phosphosilicate glass.

[0063] Step f: Successively perform aluminum evaporation, photolithography, aluminum etching, photolithography, backside metallization, and etch the passivation holes to fabricate a silicon carbide MOS structure intelligent thermal measurement chip based on integrated PIN.

[0064] In summary, the present invention introduces a PIN diode structure into a silicon carbide MOSFET. Utilizing the temperature sensitivity of the diode, the temperature inside the silicon carbide MOSFET device can be effectively monitored and tested by calculating the current flowing through the PIN diode, which is beneficial for the system to perform timely control and protection, preventing the device performance from degrading or even damaging the device due to excessive temperature, thereby improving the reliability of the device.

[0065] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. These are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0066] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined.

[0067] In the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may include direct contact between the first and second features, or may include indirect contact between the first and second features through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes the first feature being directly above and diagonally above the second feature, or merely indicating that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly below and diagonally below the second feature, or merely indicating that the horizontal height of the first feature is less than that of the second feature.

[0068] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "exemplifications", "specific exemplifications", or "some exemplifications", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or exemplification are included in at least one embodiment or exemplification of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or exemplification. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or exemplifications in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or exemplifications described in this specification.

[0069] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A silicon carbide MOS structure intelligent heat measurement chip based on an integrated PIN, characterized in that, The chip includes: a source electrode (1), a cathode (2), a gate electrode (3), a first P+ implantation region (4), a first N+ implantation region (5), a first P-well region (6), a second P+ implantation region (7), a second N+ implantation region (8), an N-epitaxial region (9), an N+ substrate region (10), a drain electrode (11), a gate oxide layer (12), a second P-well region (13), a passivation layer (14), a source contact (15), an N+ source region (16), and a drain contact (17); wherein, the drain contact (17) is located above the drain electrode (11); the N+ substrate region (10) is located above the drain contact (17); the N-epitaxial region (9) is located above the N+ substrate region (10); the first P-well region (6) is embedded in one side above the N-epitaxial region (9); the second P-well region (13) is embedded in the other side above the N-epitaxial region (9); the first P+ implantation region (4) is embedded in one side above the first P-well region (6); the first N+ implantation region (5) is embedded in the other side above the first P-well region (6); the second P+ implantation region (7) is embedded in one side above the second P-well region (13); the N+ source region (16) is embedded in the other side above the second P-well region (13); the second N+ implantation region (8) is located between the second P+ implantation region (7) and the N+ source region (16); the gate oxide layer (12) is located above the N-epitaxial region (9); the passivation layer (14) is located in one side above the gate oxide layer (12); the gate electrode (3) is located in the other side above the gate oxide layer (12); the cathode (2) is located above the first P+ implantation region (4), and its vertical part is embedded in the passivation layer (14) and the gate oxide layer (12), and its horizontal part is located above the passivation layer (14); the source electrode (1) includes a first source electrode, a second source electrode, and a third source electrode; the structure of the source electrode (1) includes a vertical part and a horizontal part, wherein the width of the horizontal part is greater than that of the vertical part; the first source electrode is located above the first N+ implantation region (5), and its vertical part is embedded in the passivation layer (14) and the gate oxide layer (12), and its horizontal part is located above the passivation layer (14); the second source electrode is located in one side above the second N+ implantation region (8), and its vertical part is embedded in a partial region of the passivation layer (14), and its horizontal part is located above the passivation layer (14); the second source electrode is located in the other side above the second N+ implantation region (8), and its vertical part is embedded in a partial region of the passivation layer (14), and its horizontal part is located above the passivation layer (14); the vertical parts of the second source electrode and the third source electrode are in contact; the source contact (15) is located above the second N+ implantation region (8), and is located below the vertical parts of the second source electrode and the third source electrode; The gate (3) is located between the first source and the second source, and is embedded under the passivation layer (14), and its lower surface is in contact with the gate oxide layer (12); Wherein, The first P+ implantation region (4), the first N+ implantation region (5) and the first P-well region (6) constitute the cell of the PIN diode; The second P+ implantation region (7), the second N+ implantation region (8), the N+ source region (16), the second P-well region (13), the N-epitaxial region (9), the N+ substrate region (10), the drain (11) and the drain contact (17) constitute the MOSFET cell region.

2. The chip according to claim 1, characterized in that, The interface between the cathode (2) and the first P+ implantation region (5) is an ohmic contact.

3. The chip according to claim 1, wherein The interfaces between the source (1) and the first P+ implantation region (4), the second N+ implantation region (7) and the second P+ implantation region (8) are ohmic contacts.

4. The chip according to claim 1, characterized in that The depth of the first P-well region is 1.1 μm and the width is 5 μm; The first P-well region (6) is uniformly doped with a doping concentration of 5×10 16 cm -3 ; The depth of the second P-well region (13) is 1.1 μm and the width is 6.2 μm; The second P-well region (13) is uniformly doped with a doping concentration of 5×10 16 cm -3 .

5. The chip according to claim 1, characterized in that, The depth of the first N+ implantation region (5) is 0.2 μm, the width is 1.7 μm, and its doping concentration is 5×10 19 cm -3 ; The depth of the second N+ implantation region (7) is 0.2 μm, the width is 1.8 μm, and its doping concentration is 5×10 19 cm -3 .

6. The chip according to claim 1, wherein The depths of the first P+ implantation region (4) and the second P+ implantation region (7) are 0.2 μm, and the doping concentration is 5×10 19 cm -3 ; The width of the first P+ implantation region (4) is 1.5 μm, and the width of the second P+ implantation region (7) is 1.5 μm.

7. The chip according to claim 1, characterized in that, The distance between the PIN diode cell and the MOSFET cell region is 1.2 μm.

8. The layout structure of a silicon carbide MOS structure intelligent thermal measurement chip based on an integrated PIN as described in claim 1, characterized in that, The layout structure includes: The MOSFET cell region (18), the gate electrode region (19), the cell of the PIN diode (20), the source electrode region (21) and the cathode region (22).

9. The layout structure according to claim 8, characterized in that The PIN diode cells (20) are uniformly distributed in the middle of the source electrode region (21) and are connected to the cathode region (22).

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