Regulation of a voltage generation system

Abstract

The voltage generation system can include a resistive voltage divider having a first resistance connected between its output and a first feedback node, and having a second resistance connected between the first feedback node and a first voltage node; a capacitive voltage divider having a first capacitance connected between its output and a second feedback node, and having a second capacitance connected between the second feedback node and the first voltage node; a comparator having an input connected to the second feedback node; and a voltage generation circuit configured to generate a voltage level at its output in response to an output of the comparator and in response to a clock signal, wherein the first feedback node is selectively connected to the second feedback node and to a second voltage node, the first resistance is selectively connected to the first feedback node, and the second resistance is selectively connected to the first voltage node.

Description

Technical Field

[0001] This disclosure generally relates to integrated circuits, and more particularly, in one or more embodiments, to apparatus and methods for regulating a voltage generation system in an integrated circuit (e.g., a memory). Background Technology

[0002] Integrated circuit devices are ubiquitous in a wide range of electronic devices. One specific type includes memory devices, often simply referred to as memory. Memory devices are typically provided as internal semiconductor integrated circuit devices in computers or other electronic devices. There are many different types of memory, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0003] Flash memory has evolved into a popular source of non-volatile memory for a wide variety of electronic applications. Flash memory typically uses single-transistor memory cells that support high memory density, high reliability, and low power consumption. By programming the charge storage structure (e.g., floating gate or charge trap) or other physical phenomena (e.g., phase transition or polarization), changes in the threshold voltage (Vt) of the memory cell determine the data state (e.g., data value) of each memory cell. Common applications of flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and removable memory modules, and the applications of non-volatile memory continue to expand.

[0004] NAND flash memory is a common type of flash memory device, so named because of the logical arrangement of its basic memory cell configuration. Typically, the memory cell arrays used in NAND flash memory are arranged such that the control gates of each memory cell in a row of the array are connected together to form an access line, such as a word line. Columns in the array contain strings of memory cells (often called NAND strings) connected in series between a pair of select gates, such as between a source select transistor and a drain select transistor. Each source select transistor can be connected to the source, and each drain select transistor can be connected to a data line, such as a column bit line. Variations using more than one select gate between the memory cell string and the source and / or between the memory cell string and the data line are known.

[0005] Integrated circuit devices are typically powered by two or more externally supplied voltages (e.g., Vcc and Vss). In addition to these supply voltages, integrated circuit devices typically generate other voltages used in the operation of the device. For example, in memory, such internally generated voltages are typically used during access operations, such as sensing operations, programming operations (often referred to as write operations), or erasing operations. These internally generated voltages are typically higher (e.g., much higher) or lower than any of the supply voltages.

[0006] Charge pumps or other voltage generation circuits are typically used to perform the operation of generating additional voltage levels from the supply voltage. Charge pumps typically utilize alternately switched capacitors (e.g., capacitors) to generate higher or lower voltages from the supply voltage. Power efficiency is often an important consideration in the design and use of integrated circuit devices, as the generation and transmission of these internal voltages typically cause significant power losses. Attached Figure Description

[0007] Figure 1 This is a simplified block diagram of a memory that communicates with a processor as part of an electronic system, according to an embodiment.

[0008] Figure 2A-2B It can be used for reference. Figure 1 A schematic diagram of a portion of the memory cell array in the described type of memory.

[0009] Figure 3 is a schematic diagram of a conventional charge pump in the relevant technology.

[0010] Figure 4 is a schematic block diagram of the voltage generation system of the related technology.

[0011] Figure 5 This is a schematic block diagram of a voltage generation system according to an embodiment.

[0012] Figure 6 This is a schematic block diagram of a control signal generator according to an embodiment.

[0013] Figure 7 According to the embodiments Figure 6 A conceptual example of timing diagrams for each signal.

[0014] Figure 8 This is a flowchart of a method for generating an operating voltage system according to an embodiment.

[0015] Figure 9 This is a state diagram of voltage regulation in an integrated circuit device according to an embodiment. Detailed Implementation

[0016] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description and illustrate specific embodiments therein by means of illustration. Throughout the drawings, similar reference numerals describe substantially similar components. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be regarded in a limiting sense.

[0017] For example, as used herein, the term "semiconductor" can refer to a layer of material, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when referenced to a semiconductor in the following description, regions / junctions may have been formed in the substrate semiconductor structure using prior processing steps, and the term semiconductor may include an underlying layer containing such regions / junctions.

[0018] Unless otherwise apparent from the context, the term "conductive" as used herein, and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.), refer to electrical conductivity. Similarly, unless otherwise apparent from the context, the term "connecting" as used herein, and its various related forms (e.g., connect, connected, connection, etc.), refer to electrical connection.

[0019] This paper recognizes that even when values ​​are expected to be equal, the variability and precision of industrial processing and operation can still cause differences from their expected values. These variability and precision will generally depend on the technology used in the manufacture and operation of integrated circuit devices. Therefore, if values ​​are expected to be equal, then those values ​​are considered equal regardless of their resulting values.

[0020] Figure 1 This is a simplified block diagram illustrating communication between a first device in the form of a memory (e.g., a memory device) 100 and a second device in the form of a processor 130 as part of a third device in the form of an electronic system, according to one embodiment. Examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and the like. The processor 130 (e.g., a controller external to the memory device 100) may be a memory controller or other external host device.

[0021] Memory device 100 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (collectively referred to as a word line), while memory cells in logical columns are typically selectively connected to the same data line (collectively referred to as a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1 (Not shown in the text) can be programmed to be one of at least two target data states.

[0022] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 for managing inputs of commands, addresses, and data to memory device 100, as well as outputs of data and status information from memory device 100. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0023] A controller (e.g., control logic 116 within memory device 100) controls access to memory cell array 104 in response to commands and generates status information for external processor 130; that is, control logic 116 is configured to perform access operations (e.g., sensing operations [potentially including read and verification operations], programming operations, and / or erasing operations) on memory cell array 104. Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control them in response to addresses. Control logic 116 may include an instruction register 128, which may represent computer-available memory for storing computer-readable instructions. In some embodiments, instruction register 128 may represent firmware. Alternatively, instruction register 128 may represent a grouping of memory cells in memory cell array 104, such as a reserved block of memory cells.

[0024] Control logic 116 also communicates with cache register 118. Cache register 118 latches incoming or outgoing data, such as that guided by control logic 116, to temporarily store data while memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 120 to be transferred to memory cell array 104; then, new data can be latched from I / O control circuitry 112 into cache register 118. During read operations, data can be transferred from cache register 118 to I / O control circuitry 112 to be output to external processor 130; then, new data can be transferred from data register 120 to cache register 118. Cache register 118 and / or data register 120 may form a page buffer of memory device 100 (e.g., may form a portion thereof). The page buffer may additionally include sensing devices ( Figure 1 (Not shown in the diagram) to sense the data state of the memory cells, for example, by sensing the state of the data lines connected to the memory cells in the memory cell array 104. The status register 122 can communicate with the I / O control circuitry 112 and control logic 116 to latch status information for output to the processor 130.

[0025] The memory device 100 receives control signals from the processor 130 via control link 132 at control logic 116. These control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may be received via control link 132. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via multiplexed input / output (I / O) bus 134 and outputs data to the processor 130 via I / O bus 134.

[0026] For example, a command can be received at I / O control circuit 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to command register 124. An address can be received at I / O control circuit 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to address register 114. Data can be received at I / O control circuit 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 118. The data can then be written to data register 120 for programming memory cell array 104. In another embodiment, cache register 118 can be omitted, and data can be written directly to data register 120. Data can also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may contain any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connections to the memory device 100 via external devices (e.g., processor 130).

[0027] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 1 The memory device 100. It should be understood that, with reference to Figure 1 The functionality of the various block components described need not be separated from different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device can be adapted to perform... Figure 1 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0028] Furthermore, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0029] Figure 2A It can be, for example, part of memory cell array 104 in reference Figure 1 A schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array, used in the type of memory described. The memory array 200A includes, for example, word lines 2020 to 202. N Access lines and, for example, bit lines 2040 to 204 MThe data cable. Word line 202 can be connected in a many-to-one relationship to... Figure 2A Global access lines (e.g., global word lines) not shown. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have a conductivity type such as p-type conductivity to form a p-well, or have n-type conductivity to form an n-well, for example.

[0030] The memory array 200A can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cell 208 in each NAND string 206 may be connected in series with select gate 210 (e.g., a field-effect transistor) (e.g., select gates 2100 to 210). M One of them (e.g., it may be a source-select transistor, often referred to as a select-gate source) and select-gate 212 (e.g., a field-effect transistor) (e.g., select-gate 2120 to 212). M Between one of them (for example, it could be a drain-select transistor, often referred to as a select gate-drain transistor). Select transistors 2100 to 210 M They can be connected together to select line 214, such as the source select line (SGS), and select transistors 2120 to 212. M They can be connected together to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent multiple select gates connected in series, each selected gate configured in series to receive the same or independent control signals.

[0031] The source of each select gate 210 can be connected to the common source 216. The drain of each select gate 210 can be connected to the memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to the select line 214.

[0032] The drain of each select gate 212 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0033] Figure 2A The memory array in the array can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2A The memory array in the array may be a three-dimensional memory array, for example, in which the NAND string 206 may extend substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the bit line 204, which may be substantially parallel to the plane containing the common source 216.

[0034] like Figure 2A As shown, a typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or other structure configured to store charge) that determines the data state of the memory cell (e.g., by changing a threshold voltage), and a control gate 236. Data storage structure 234 may include both conductive and dielectric structures, while control gate 236 is typically formed of one or more conductive materials. In some cases, memory cell 208 may further have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The control gate 236 of memory cell 208 is connected to (and in some cases forms) a word line 202.

[0035] Columns of memory cells 208 may be NAND strings 206 or multiple NAND strings 206 selectively connected to a given positioning line 204. Rows of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. Rows of memory cells 208 may (but not necessarily) contain all memory cells 208 commonly connected to a given word line 202. Rows of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 typically contain every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202 NFurthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202 N And the memory cell 208 selectively connected to the odd-numbered bit lines 204 (e.g., bit lines 2041, 2043, 2045, etc.) can be another physical page of the memory cell 208 (e.g., the odd-numbered memory cell). Although Figure 2A Although bit lines 2043 and 2045 are not explicitly depicted in the figure, it is evident from the figure that bit line 204 of the memory cell array 200A can be connected from bit line 2040 to bit line 204. M Sequential numbering. Other groups of memory cells 208 commonly connected to a given word line 202 may also define physical pages of memory cells 208. For a particular memory device, all memory cells commonly connected to a given word line may be considered physical pages of the memory cell. A portion of a physical page of a memory cell (which in some embodiments may still be an entire row) that is read during a single read operation or programmed during a single programmable operation (e.g., the upper or lower page of the memory cell) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020-202. N All memory cells (e.g., all NAND strings 206 sharing common word line 202). Unless explicitly distinguished, a reference to a page of a memory cell herein refers to the memory cell of the logical page of the memory cell.

[0036] Although discussing in conjunction with NAND flash memory Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS or other data storage structures configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0037] Figure 2B It can be, for example, part of memory cell array 104 in reference Figure 1 Another schematic diagram of a portion of the memory cell array 200B used in the type of memory described. Figure 2B Elements with the same number in the text correspond to elements such as those mentioned above. Figure 2A The description provided. Figure 2BFurther details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may be incorporated into a vertical structure that may contain semiconductor pillars, a portion of which may serve as channel regions for the memory cells of NAND strings 206. Each of the NAND strings 206 may be selectively connected to bit lines 2040-204 via a select transistor 212 (e.g., a drain select transistor, often referred to as a select gate drain). M And a selection transistor 210 (e.g., a source selection transistor, often referred to as a select gate source) is selectively connected to a common source 216. Multiple NAND strings 206 can be selectively connected to the same bit line 204. A subset of NAND strings 206 can be connected via selection lines 2150-215. K A bias voltage is applied to its corresponding bit line 204 to selectively activate a specific selection transistor 212 located between the NAND string 206 and the bit line 204. A selection transistor 210 can be activated by applying a bias voltage to selection line 214. Each word line 202 can be connected to multiple rows of memory cells in the memory array 200B. Rows of memory cells commonly connected to each other via specific word lines 202 can be collectively referred to as a layer.

[0038] A three-dimensional NAND memory array 200B may be formed on a peripheral circuit system 226. The peripheral circuit system 226 may represent various circuit systems for accessing the memory array 200B. The peripheral circuit system 226 may include complementary circuit elements. For example, the peripheral circuit system 226 may include both n-channel transistors and p-channel transistors formed on the same semiconductor substrate, a process collectively referred to as CMOS or Complementary Metal-Oxide-Semiconductor. Although CMOS typically no longer utilizes a strictly metal-oxide-semiconductor construction due to advancements in integrated circuit manufacturing and design, the designation CMOS is retained for convenience. The peripheral circuit system 226 may include voltage generation systems and / or control signal generators in various embodiments.

[0039] Voltage generation circuits typically increase or decrease the input supply voltage to provide higher or lower output voltages, respectively, for operating circuit elements in an integrated circuit device. A charge pump is a type of voltage generation circuit commonly used in integrated circuit devices such as non-volatile memory systems. A charge pump typically comprises several stages, each containing a stage capacitor that is charged and discharged during the charge pump's clock cycle. Voltage isolation devices may be coupled between the stage capacitor and the stage input voltage to reduce losses in the output voltage generated by the stage.

[0040] One or more clock signals typically trigger the charging of a stage capacitor. A typical clock signal may have a clock frequency with a period shorter than the capacitor's discharge time. In one such design, two clock signals with opposite phases trigger the charging of alternating stages of a multi-stage charge pump.

[0041] Figure 3 schematically illustrates an example of a conventional charge pump 300 of the related art. The charge pump 300 may represent a positive charge pump, for example, generating an increasing voltage level at its output.

[0042] The charge pump 300 receives an input voltage Vin, which may be, for example, Vcc. A first clock signal CP1 may be received at one input (e.g., an electrode) of an alternating stage capacitor (e.g., stage capacitors 3160, 3162, 3164, etc.), while a second clock signal CP2 may be received at one input (e.g., an electrode) of an alternating stage capacitor (e.g., stage capacitors 3161, 3163, 3165, etc.). Although stage capacitors 3163, 3164, and 3165 are not directly shown in Figure 3, this is evident from the numbering of stage capacitors 316 from 0 to N. Clock signals CP1 and CP2 may typically have opposite phases, the same frequency, and similar (e.g., the same) amplitudes, which may correspond to the amplitude of the supply voltage.

[0043] The charge pump 300 may contain N+1 stages 312. Stages 3120 to 312 N Each stage may contain a stage capacitor 316. Stages 3120 to 312 N It may also include a voltage isolation device 314, such as a diode. The (N+1)th stage 312 of the charge pump 300 N A voltage isolation device 314 may include a capacitor 316 without a corresponding stage capacitor 316. N It may include a voltage isolation device 314 N This is to protect a load, such as a circuit system configured to receive an output voltage Vout. As an example, the load may be an access line 202 selectively connected to receive Vout. In this example, access line 202 may be configured to receive a voltage level associated with an access operation (e.g., a sensing operation or a programming operation). In the charge pump 300, voltage isolation device 314 typically reduces the charging or discharging of stage capacitor 316 between cycles of its respective clock signals CP1 or CP2. Therefore, the charge pump 300 can progressively store more charge on the capacitor components of each stage, and several such stages placed together in the charge pump 300 can generate an increasing voltage level.

[0044] Figure 4 is a schematic block diagram of a voltage generation system 400 of the related art. The voltage generation system 400 may respond to an analog control signal, such as Vref, received at a control signal node 440, which may be generated by a digital-to-analog converter (DAC) (not depicted in Figure 4). The control signal Vref may be provided to one input of comparator 442. The output 444 of comparator 442 may be provided to oscillator 446, for example, as an enable signal. Oscillator 446 may selectively provide an output (e.g., one or more clock signals) in response to the output of comparator 442. For example, referring to Figure 3, oscillator 446 may provide complementary clock signals CP1 and CP2. Alternatively, oscillator 446 may provide clock signal CP1, and an inverter may be used to generate clock signal CP2.

[0045] The output of oscillator 446 may be supplied to charge pump 448 having one or more pump stages. Charge pump 448 may represent any circuit capable of generating a voltage that has an amount greater than the supply voltage provided to charge pump 448 and / or a polarity different from the supply voltage. As an example, charge pump 448 may represent a charge pump of the type depicted in Figure 3. Oscillator 446 and charge pump 448 may be collectively referred to as voltage generation circuit 450. The output of charge pump 448 may represent a voltage level, such as Vout, generated at the output 452 of voltage generation circuit 450. Voltage generation circuit 450 may alternatively include any circuit configured to generate a voltage level in response to a logic level of an input control signal (e.g., the output 444 of comparator 442).

[0046] To adjust the voltage level of Vout and improve its stability, Vout can be provided with a feedback loop including resistive feedback (e.g., resistive voltage divider 454), capacitive feedback (e.g., capacitive voltage divider 472), and comparator 442. Resistive voltage divider 454 is conceptually depicted as having a node 456 between a top resistor 4580 and a bottom resistor 4581. Resistor 4581 can be additionally selectively connected to voltage node 4600 via an n-type field-effect transistor (nFET) 462. nFET 462 may have a control gate connected to control signal node 464 to receive control signal CS1. Voltage node 4600 can be configured to receive a bottom rail supply voltage, such as a reference potential, for example, a supply voltage Vss, which can be ground or 0V.

[0047] Node 456 can be selectively connected to node 466 via nFET 468. nFET 468 may have a control gate connected to control signal node 470 to receive control signal CS2. Although node 456 is connected to node 466 and voltage node 4600, depending on the resistance ratio of resistors 4580 and 4581, node 456 may be assumed to be at a voltage level between Vout and the voltage level of voltage node 4600, such as Vfeedback. Vfeedback may be provided as a second input to comparator 442, thereby generating an output signal of comparator 442 that has a first logic level, such as logic high, when the voltage level of Vout causes the voltage level of Vfeedback to be lower than the voltage level of Vref, and a second logic level, such as logic low, when the voltage level of Vout causes the voltage level of Vfeedback to be higher than the voltage level of Vref. In this way, the first logic level of comparator 442 can signal the voltage generation circuit 450 to enable oscillator 446 when Vout is lower than the target voltage level, thereby generating its output clock signal to operate charge pump 448, while the second logic level of comparator 442 can signal the voltage generation circuit 450 to disable oscillator 446 when Vout is higher than the target voltage level.

[0048] While resistive voltage dividers are commonly used in the control of voltage generation systems, this can cause significant current draw. For example, when resistors 4580 and 4581 are connected to voltage node 4600, current typically flows continuously from output 452 into voltage node 4600. To address this issue, a capacitive voltage divider is typically incorporated. As depicted, capacitive voltage divider 472 may include a top capacitor 4740 having a first electrode connected to output 452 and a second electrode connected to node 466, and may additionally include a bottom capacitor 4741 having a first electrode connected to node 466 and a second electrode connected to voltage node 4601. Voltage node 4601 may be configured to receive a bottom rail supply voltage, such as a reference potential, for example, a supply voltage Vss, which may be ground or 0V.

[0049] In operation, after charging node 466 to a voltage level representing the voltage divider level of Vout, the resistive voltage divider 454 can be isolated from node 466 and from voltage node 4600 by deactivating nFET 468 and nFET 462, respectively. The change in the voltage level of Vout will still be reflected in the voltage level at node 466, but the current draw through the resistive voltage divider 454 will be reduced.

[0050] Although the voltage level change of Vout can still be reflected in the voltage level at node 466 when resistive voltage divider 454 is isolated from node 466, current leakage may be unavoidable, causing errors in the resulting voltage level of Vout due to continuous operation in this manner. Furthermore, significant changes in the voltage level of Vout, such as those caused by attaching a load to output 452, may not be adequately reflected in the voltage level at node 466. Therefore, it is common in voltage generation systems of the type depicted in Figure 4 to periodically or selectively reconnect node 456 to node 466 and voltage node 4600. However, although resistors 4580 and 4581 are isolated from node 466 and voltage node 4600, the voltage level of node 456 may tend to balance with Vout. To address this issue, nFET 462 is typically activated before nFET 468 to allow node 456 to return to the voltage level of Vfeedback, which represents the voltage level of Vout, before reconnecting node 456 to node 466. The delay between activating nFET 462 and nFET 468 may depend on the expected time for the voltage level of node 456 to return to a steady state after it is connected to voltage node 4600.

[0051] While the use of capacitive voltage divider 472 in conjunction with resistive voltage divider 454 as described above offers advantages over using resistive voltage divider 454 alone, it may be important for the control logic to determine when to activate nFET 462 and nFET 468 and to determine the appropriate delay between activating nFET 462 and nFET 468 for different voltage levels of Vout. Various embodiments facilitate the autonomous control of a hybrid control system utilizing both resistive and capacitive feedback without regard to the voltage level of Vout.

[0052] Figure 5 This is a schematic block diagram of a voltage generation system 500 according to an embodiment. The voltage generation system 500 may respond to an analog control signal, such as Vref, received at a control signal node 540, which may be generated by a digital-to-analog converter (DAC). Figure 5 (Not depicted in the figure) is generated. A control signal Vref can be provided to one input of comparator 542. The output 544 of comparator 542 can be provided, for example, as an enable signal (e.g., a flag signal) to the first input of a logic gate (e.g., AND gate 547). The second input of AND gate 547 can be connected to the output 545 of oscillator 546. The output 545 of oscillator 546 can provide an oscillation signal, such as a clock signal clk_pmp, which may have a 50% duty cycle. Specifically, the clock signal clk_pmp may correspond to, for example, clock signals CP1 or CP2 in Figure 3, while a complement of clock signal clk_pmp may correspond to clock signals CP2 or CP1.

[0053] The output of AND gate 547 can be provided to charge pump 548 having one or more pump stages. Charge pump 548 can represent any circuit capable of generating a voltage that has an amount greater than the supply voltage provided to charge pump 548 and / or a polarity different from the supply voltage. As an example, charge pump 548 can represent a charge pump of the type depicted in Figure 3. Oscillator 546, AND gate 547, and charge pump 548 can be collectively referred to as voltage generation circuit 550. The output of charge pump 548 can represent a voltage level, such as Vout, generated at the output 552 of voltage generation circuit 550. Voltage generation circuit 550 can alternatively include any circuit configured to generate a voltage level in response to a logic level of an input control signal (e.g., the output 544 of comparator 542).

[0054] To adjust the voltage level of Vout and improve its stability, Vout may be provided with a feedback loop including selectively enabled resistive feedback (e.g., selectively enabled resistive voltage divider 554), capacitive feedback (e.g., capacitive voltage divider 572), and comparator 542. Resistive voltage divider 554 is conceptually depicted as having a top resistor 5580 with a first end connected to output 552 and a second end selectively connected to node (e.g., first feedback node) 556, and a bottom resistor 5581 with a first end connected to node 556. Resistor 5581 may additionally have a second end selectively connected to voltage node 5600 via an n-type field-effect transistor (nFET) 562. nFET 562 may have a control gate connected to control signal node 576 to receive control signal clk1, a first source / drain connected to the second end of resistor 5581, and a second source / drain connected to voltage node 5600. Voltage node 5600 may be configured to receive a voltage level different from (e.g., lower than) a target voltage level of Vout. Voltage node 5600 can be configured to receive a bottom rail supply voltage, such as a reference potential, such as the supply voltage Vss, which can be ground or 0V. As an example, the resistance value of resistor 5580 can be 10 to 20 times the resistance value of resistor 5581. Although depicted as static resistors, resistors 5580 and 5581 can alternatively represent adjustable resistors to allow changing the resistance ratio of 5580 / (5580+5581). Adjustable resistors in resistive voltage dividers are readily understood. See, for example, U.S. Patent No. 9,659,602 to Qiao et al.

[0055] Node 556 can be selectively connected to node (e.g., a second feedback node) 566 via transmission gate 578. Transmission gate 578 may include an nFET 580 having a control gate connected to control signal node 582 to receive control signal clk3, a first source / drain connected to node 556, and a second source / drain connected to node 566. Transmission gate 578 may additionally include a p-type field-effect transistor (pFET) 584 having a control gate connected to control signal node 586 to receive control signal / clk3, a first source / drain connected to node 556, and a second source / drain connected to node 566. Control signal / clk3 may be supplementary to control signal clk3. Alternatively, transmission gate 578 may be replaced with a single transistor, such as nFET 580.

[0056] Node 556 may be selectively connected to resistor 5580 and output 552 via nFET 588, which has a control gate connected to control signal node 576 to receive control signal clk1, a first source / drain connected to the second end of resistor 5580, and a second source / drain connected to node 556. Furthermore, node 556 may be selectively connected to voltage node 592 via nFET 594, which has a control gate connected to control signal node 596 to receive control signal / clk1, a first source / drain connected to node 556, and a second source / drain connected to voltage node 592. Control signal / clk1 may be a supplement to control signal clk1. Voltage node 592 may be configured to receive a voltage level between a target voltage level of Vout and the voltage level of voltage node 5600. Voltage node 592 may be further configured to receive voltage levels within the voltage domain of comparator 542, for example, comparator 542 may be configured to operate within the range of voltage levels targeted. In some embodiments, voltage node 592 may be configured to receive a voltage level near the control signal Vref. Voltage node 592 may be configured to receive a top rail supply voltage, such as the supply voltage Vcc.

[0057] Although node 556 is connected to node 566, voltage node 5600, and output 552 when isolated from voltage node 592, node 556 may be assumed to be at a voltage level between Vout and the voltage level of voltage node 5600, such as Vfeedback, depending on the resistance ratio of resistors 5580 and 5581. Vfeedback may be provided as a second input to comparator 542, thereby generating an output signal of comparator 542, which has a first logic level, such as logic high, when the voltage level of Vout causes the voltage level of Vfeedback to be lower than the voltage level of Vref, and a second logic level, such as logic low, when the voltage level of Vout causes the voltage level of Vfeedback to be higher than the voltage level of Vref. In this way, the first logic level of comparator 542 may signal voltage generation circuit 550 to enable charge pump 548, for example, by sending the output of oscillator 546 to charge pump 548 when Vout is lower than a target voltage level. In contrast, the second logic level of comparator 542 can signal voltage generation circuit 550 to disable charge pump 548 when Vout is higher than the target voltage level, for example, to isolate the output of oscillator 546 from charge pump 548. The ratio of resistor 5580 to resistor 5581 can be set to provide a feedback voltage Vfeedback equal to the control signal Vref when the output voltage Vout is equal to its target voltage level.

[0058] The voltage generation system 500 may additionally include a capacitive voltage divider 572. As depicted, the capacitive voltage divider 572 may include a top capacitor 5740 having a first electrode connected to output 552 and a second electrode connected to node 566, and may additionally include a bottom capacitor 5741 having a first electrode connected to node 566 and a second electrode connected to voltage node 5600. As an example, the capacitance value of capacitor 5740 may be approximately five times the capacitance value of capacitor 5741. A larger capacitance ratio can result in smoother voltage control, but typically requires a larger voltage range.

[0059] The voltage generation system 500 may additionally selectively connect node 566 to voltage node 5601, for example, via nFET 598, which has a control gate connected to control signal node 599, which is configured to receive control signal RegEn. Deactivating nFET 598 can be used to enable voltage regulation by allowing node 566 to have a voltage level representing a voltage divider level of Vout. Activating nFET 598 can be used to disable voltage regulation by pulling node 566 to the voltage level of voltage node 5601. Voltage node 5601 can be configured to receive a bottom rail supply voltage, such as a reference potential, such as supply voltage Vss, which may be ground or 0V. Alternatively, depending on the desired logic level of the output 544 of comparator 542 when voltage regulation is disabled, voltage node 5601 can be configured to receive a voltage level higher than control signal Vref. This may include a top rail supply voltage, such as supply voltage Vcc. In addition, oscillator 546 can be disabled when the control signal RegEn has the following logic level: the logic level is configured to connect node 566 to voltage node 5601 so that the logic level of the output 544 of comparator 542 can be uncorrelated.

[0060] In operation, after charging node 566 to a voltage level representing the voltage divider level of Vout, node 556 can be isolated from node 566 and from voltage node 5600 by deactivating transmission gate 578 and nFET 562, respectively. The voltage level change of Vout can still be reflected in the voltage level at node 566, but the current draw through resistive voltage divider 554 is reduced.

[0061] Although node 556 is isolated from node 566 and from voltage node 5600, node 556 can be further isolated from output 552 by deactivating nFET 588. In this case, voltage generation system 500 may not need to charge any parasitic capacitance that may exist below resistor 5580, compared to voltage generation system 400 of FIG. 4. This can further reduce power consumption compared to related technologies. Additionally, node 556 can be connected to voltage node 592 by activating nFET 594.

[0062] Although the voltage level change of Vout can still be reflected in the voltage level at node 566 when the resistive voltage divider 554 is isolated from node 566, current leakage may be unavoidable, causing errors in the resulting voltage level of Vout due to continuous operation in this manner. Furthermore, significant changes in the voltage level of Vout, such as those caused by attaching a load to output 552, may not be adequately reflected in the voltage level at node 566. Therefore, the voltage generation system 500 can be configured to periodically or selectively reconnect node 556 to node 566, output 552, and voltage node 5600. Compared to the voltage generation system of Figure 4, when resistive feedback is disabled, node 556 can be balanced towards a voltage level equal to the voltage level of voltage node 592 minus the threshold voltage (Vt) of nFET 594, the calculated voltage level being expected to be closer to the voltage level of Vfeedback representing the voltage level of Vout. Therefore, when resistive feedback is enabled (e.g., re-enabled), a smaller delay can be utilized between connecting node 556 to output 552 and voltage node 5600 and connecting node 556 to node 566. This delay is independent of the target voltage level of Vout, allowing the same delay to be used for a variety of different target voltage levels of Vout, which enables a less complex control scheme compared to related techniques. Furthermore, this delay approaches zero as the voltage level of voltage node 592 minus Vt of nFET 594 approaches Vref.

[0063] Figure 6 This is a schematic block diagram of a control signal generator 600 according to an embodiment. The control signal generator 600 may represent the functionality of a controller (e.g., control logic 116). The control signal generator 600 may include a plurality of series-connected flip-flops 661, such as D flip-flops. For example, a first flip-flop 6610 may have an input (e.g., a D input) connected to a signal node, such as the output 544 of a comparator 542, the signal node being configured to receive a signal indicating a willingness to enable the voltage generation circuitry. The input of the first flip-flop 6610 (e.g., a flag signal from the output 544 of the comparator 542) may be further connected to a corresponding input of an AND gate 663. The output of the first flip-flop 6610 (e.g., a Q output) may be connected to an input (e.g., a D input) of a second flip-flop 6611. The input of the second flip-flop 6611 may be further connected to a corresponding input of an AND gate 663. This series connection may be repeated for each of the flip-flops 661 such that for each value of Y from 0 to F-1, the flip-flop 661... Y The outputs (e.g., Q output) can all be connected to the flip-flop 661. Y+1 The input (e.g., D input). Each trigger is 6610-661. FThe inputs (e.g., D inputs) can be connected to the corresponding inputs of AND gate 663, and each flip-flop 6610-661 F The output (e.g., the Q output) can be connected to the corresponding input of the AND gate 663. In this way, as... Figure 6 As described, the AND gate 663 may contain one more input than the number of flip-flops 661, or in this instance, F+2 inputs.

[0064] Trigger 6610-661 F Each of the components may have a clock input CLK (e.g., the output 545 of oscillator 546) connected to a clock signal node configured to receive a first clock signal, such as clock signal clk_pmp. In this way, the output of AND gate 663 may have a logic low level when the output of any of the flip-flops 661 or the input of flip-flop 6610 is logic low, and may have a logic high level when all the outputs of flip-flops 661 and the input of flip-flop 6610 are logic high. Due to the nature of the clocked flip-flops 661, for the case where the number of consecutive clock cycles of clock signal clk_pmp is equal to (or greater than) F+1, the output of AND gate 663 may have a logic high level in response to the output 544 of comparator 542 having a logic high level.

[0065] The output of AND gate 663 can be connected to the first input of OR gate 665. The second input of OR gate 665 can be connected to clock signal node 667, which is configured to receive a second clock signal (e.g., an external clock signal clk_ext). Although not depicted, memory 100 may receive the external clock signal clk_ext, for example, via control link 132. Alternatively, the second clock signal may be generated internally within the integrated circuit device.

[0066] The period of the second clock signal may be greater than the period of the first clock signal. In some embodiments, the period of the second clock signal is at least an order of magnitude larger than the period of the first clock signal. In other embodiments, the period of the second clock signal is at least two orders of magnitude larger than the period of the first clock signal. As an example, the period of the first clock signal may be approximately tens of nanoseconds, while the period of the second clock signal may be on the order of microseconds. The smaller period of the first clock signal can help increase the response to sudden load changes in the voltage generating system. The larger period of the second clock signal can promote power saving by reducing the periodic activation of the resistive voltage divider. The second clock signal may also have a lower duty cycle than the first clock signal. For example, the second clock signal may have a 12.5% ​​duty cycle. The lower duty cycle of the second clock signal can achieve power saving, but the duty cycle of the second clock signal should be selected to help balance node 566 when the resistive voltage divider 554 is activated.

[0067] The output of OR gate 665 can be connected to the input (e.g., D input) of an optional flip-flop (e.g., a D flip-flop) 669. Flip-flop 669 may have a clock input CLK connected to a signal node configured to receive a first clock signal, such as the clock signal clk_pmp from the output 545 of oscillator 546. The output (e.g., Q output) of flip-flop 669 can be connected to a control signal node 576 to provide a control signal clk1. Flip-flop 669 can be provided to synchronize the transition of control signal clk1 to the first clock signal. However, similar functionality can be provided without flip-flop 669, making flip-flop 669 removable.

[0068] The output of flip-flop 669 can be further connected to the input of inverter 6730, the output of which can be connected to control signal node 596 to provide control signal / clk1. The output of flip-flop 669 (e.g., Q output) can be further connected to the input (e.g., D input) of optional flip-flop 671 (e.g., D flip-flop) and to the first input of AND gate 675. Flip-flop 671 may have a clock input CLK connected to a signal node configured to receive a first clock signal, such as the clock signal clk_pmp from the output 545 of oscillator 546. The output of flip-flop 671 can be connected to the second input of AND gate 675, the output of which can be connected to control signal node 582 to provide control signal clk3. Flip-flop 671 can implement a delay between the transitions of control signals clk1 and clk3, such as one clock cycle of the first clock signal. The output of AND gate 675 can be further connected to the input of inverter 6731, the output of which can be connected to control signal node 586 to provide the control signal / clk3. To provide additional delay, such as an additional clock cycle for the first clock signal, flip-flop 671 can represent the number of flip-flops connected in series between the output of flip-flop 669 and the second input of AND gate 675. Alternatively, if the voltage level of voltage node 592 is close to the voltage level of control signal Vref, such a delay may be meaningless and flip-flop 671, AND gate 675, and inverter 6731 can be eliminated. In this type of embodiment, control signal node 582 can be connected to control signal node 576, and control signal node 586 can be connected to control signal node 596.

[0069] refer to Figure 5 and 6It is evident that the selective activation of the resistive voltage divider 554 and the selective connection from the first feedback node 556 to the second feedback node 566 are in response to the logic level of the output of the OR gate 665. Although the logic level can be inverted, for example, by inserting a delay via flip-flops 669 and 671, or by inverting, for example, via inverters 6730 and 6731, each of the control signals clk1, / clk1, clk3, and / clk3 is a response to the logic level of the output of the OR gate 665.

[0070] Figure 7 According to the embodiments Figure 6 Here is a conceptual example of the timing diagram for each signal. Trace 781 can represent the second clock signal clk_ext from signal node 667. Trace 783 can represent the first clock signal clk_pmp from the output 545 of oscillator 546. Trace 785 can represent the flag signal from the output 544 of comparator 542. Trace 787 can represent the control signal clk1 leading to control signal node 576. Trace 789 can represent the control signal clk3 leading to control signal node 582.

[0071] Will use Figure 6 The instance structure and assume F equals 1 (e.g., two cascaded flip-flops 661) are used to make... Figure 7 The following description applies. At time t0, the second clock signal clk_ext may transition high. In response, the control signal clk1 may transition high at time t1, for example, one clock cycle after time t0, of the first clock signal clk_pmp. In response to the control signal clk1 transitioning high at time t1, the control signal clk3 may transition high at time t2, for example, one clock cycle after time t1, of the first clock signal clk_pmp. At time t3, the second clock signal clk_ext may transition low. In response, the control signals clk1 and clk3 may transition low at time t4, for example, one clock cycle after time t3, of the first clock signal clk_pmp.

[0072] At time t5, the flag signal may transition high, but then may subsequently transition low before a sufficient number of clock cycles (e.g., three clock cycles) of the first clock signal clk_pmp, causing the output of AND gate 663 to transition high and triggering a transition in control signal clk1. The flag signal may further make such high / low transitions at times t6, t7, t8, t9, and t10, each of which is insufficient to cause a transition in control signal clk1.

[0073] At time t11, the second clock signal clk_ext may transition high. In response, the control signal clk1 may transition high at time t12, for example, at one clock cycle of the first clock signal clk_pmp after time t11. In response to the control signal clk1 transitioning high at time t12, the control signal clk3 may transition high at time t13, for example, at one clock cycle of the first clock signal clk_pmp after time t12. At time t14, the second clock signal clk_ext may transition low. In response, the control signals clk1 and clk3 may transition low at time t15, for example, at one clock cycle of the first clock signal clk_pmp after time t14.

[0074] At time t16, the flag signal may transition high and subsequently remain high for a sufficient number of clock cycles (e.g., three clock cycles) of the first clock signal clk_pmp, causing the output of AND gate 663 to transition high and triggering a transition of control signal clk1. In response, control signal clk1 may transition high at time t17, for example, four clock cycles of the first clock signal clk_pmp after time t16 in this instance. In response to control signal clk1 transitioning high at time t17, control signal clk3 may transition high at time t18, for example, one clock cycle of the first clock signal clk_pmp after time t17. At time t19, the second clock signal clk_ext may transition high. At time t20, the second clock signal clk_ext may transition low. However, since the flag signal has already been high for a sufficient number of clock cycles of the first clock signal clk_pmp at time t19, the transition of the second clock signal may have no effect on control signals clk1 and clk3. At time t21, the flag signal may transition low. In response, control signals clk1 and clk3 may transition low at time t22, for example, one clock cycle after time t21, from the first clock signal clk_pmp.

[0075] Figure 8 This is a flowchart of a method for operating a device according to an embodiment. The method may represent actions associated with, for example, generating internal voltage levels of an integrated circuit device during access operations of a semiconductor memory. The method may be in the form of, for example, computer-readable instructions stored in instruction register 128. Such computer-readable instructions may be executed by a controller (e.g., control logic 116) to cause the device (e.g., related components of the device) to perform the method.

[0076] At point 801, voltage generation regulation of the voltage generation system can be enabled. For example, refer to... Figure 5In the voltage generation system, the control signal RegEn can be switched to a logic low level. Resistive feedback of the voltage generation system can be enabled at 803. For example, this can be achieved by switching control signals clk1 and clk3 to a logic high level (e.g., reference...). Figure 6 and 7 (as described) and switch control signals / clk1 and / clk3 (e.g., as complements to control signals clk1 and clk3, respectively) to logic low to enable resistive voltage divider 554.

[0077] At 805, it can be determined whether the output of the voltage generation system has reached its target voltage level. For example, it can be determined whether the feedback voltage Vfeedback has reached the voltage level of the control signal Vref. If the output has not yet reached its target voltage level, the method can return to 803 to enable resistive feedback (e.g., maintain enable). At 807, it can be determined whether the clock signal has a specific logic level. For example, it can be determined whether the second clock signal clk_ext has a logic high level. If the clock signal has a specific logic level, the method can return to 803 to enable resistive feedback (e.g., maintain enable). If the clock signal does not have a specific logic level at 807, and the output has indeed reached its target voltage level at 805, then resistive feedback can be disabled at 809. For example, this can be achieved by switching the control signals clk1 and clk3 to a logic low level (e.g., refer to...). Figure 6 and 7 (as described) and switch control signals / clk1 and / clk3 (e.g., as complements to control signals clk1 and clk3, respectively) to logic high to disable the resistive voltage divider 554.

[0078] At point 811, for example after disabling the resistive feedback of the voltage generation system, it can be determined whether the output of the voltage generation system remains below its target voltage level for a specific time period. For example, it can be determined whether the feedback voltage Vfeedback has remained below the control signal Vref voltage level for a predetermined number of clock cycles, such as a specific number of cycles (e.g., consecutive cycles) of the first clock signal clk_pmp. (See reference...) Figure 6A predetermined number of clock cycles for the first clock signal can be selected (e.g., defined) using the number of flip-flops 661 incorporated into the control signal generator 600. If the output does not remain below the target voltage level for a specific time period, the method can return to 809 to disable resistive feedback (e.g., maintain disabling). If the output has remained below the target voltage level for a specific time period, the method can return to 803 to enable resistive feedback. In some embodiments, the method can additionally return to 803 to enable resistive feedback if a specific logic level is determined for the clock signal (e.g., the second clock signal clk_ext).

[0079] Figure 9 This is a state diagram 900 for voltage regulation in an integrated circuit device according to an embodiment. For example, state diagram 900 may correspond to the regulation of the voltage generation system of the memory during access operations on memory cells of a memory cell array, such as sensing operations (which may include read or verify operations), programming operations, or erasing operations. State diagram 900 may represent the processing of a controller (e.g., control logic 116). The action of state diagram 900 may be defined as, for example, a computer-readable instruction stored in instruction register 128. Such computer-readable instructions may be executed by the controller (e.g., control logic 116) to cause the integrated circuit device (e.g., memory) to perform the action of state diagram 900. As an example, reference will be made to… Figure 5 The voltage generation system 500 and the control signal generator 600 are discussed in the state diagram 900.

[0080] State diagram 900 can be initialized at state 9200 where voltage regulation is disabled. For example, the control signal RegEn can be at a logic high level. Transition point 9220 can respond to the control signal RegEn transitioning to a logic low level, and the state can then advance to state 9201 where voltage regulation is enabled. The control signal RegEn can transition to a logic low level during the initialization of a memory access operation and can remain at a logic low level during the access operation.

[0081] Transition point 9221 may respond to a situation where, upon initial activation of voltage regulation, the voltage level of Vout is lower than the target voltage level of the voltage generation system 500, or the second clock signal clk_ext has a logic high level, and this state may subsequently advance to state 9202, which enables resistive feedback, for example, control signals clk1 and clk3 have logic high levels, and control signals / clk1 and / clk3 have logic low levels. In some embodiments, the control signal RegEn may transition to a logic low level synchronously with the transition of the second clock signal clk_ext to a logic high level. While generally less likely to occur from state 9201, transition point 9222 may respond to a situation where, upon initial activation of voltage regulation, the voltage level of Vout is higher than the target voltage level of the voltage generation system 500, and the second clock signal clk_ext has a logic low level, and this state may subsequently advance to state 9203, which disables resistive feedback, for example, control signals clk1 and clk3 have logic low levels, and control signals / clk1 and / clk3 have logic high levels.

[0082] From state 9202, transition point 9223 may respond to a voltage level of Vout being higher than the target voltage level of the voltage generation system 500, and a second clock signal clk_ext having a logic low level, and the state may then advance to state 9203 where resistive feedback is disabled. From state 9203, transition point 9224 may respond to a voltage level of Vout being lower than the target voltage level of the voltage generation system 500 for a specific time period, or a second clock signal clk_ext having a logic high level, and the state may then advance to state 9202 where resistive feedback is enabled. From states 9202 and 9203, respectively, transition points 9225 and 9226 may respond to a control signal RegEn having a logic high level, and the state may then advance to state 9200 where voltage regulation is disabled in either case.

[0083] in conclusion

[0084] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that any arrangement intended to achieve the same purpose may replace the specific embodiments shown. Many adaptations to the embodiments will be apparent to those skilled in the art. Therefore, this application is intended to cover any modifications or variations of the embodiments.

Claims

1. A voltage generation system for an integrated circuit device, comprising: A resistive voltage divider having a first resistor connected between the output of the voltage generation system and a first feedback node, and a second resistor connected between the first feedback node and a first voltage node, the first voltage node being configured to receive a first voltage level; A capacitive voltage divider having a first capacitor connected between the output of the voltage generation system and a second feedback node, and a second capacitor connected between the second feedback node and the first voltage node; A comparator having a first input connected to the second feedback node, a second input connected to the control signal node, and an output; and A voltage generating circuit is configured to generate a voltage level at the output of the voltage generating system in response to a logic level of the output of the comparator and in response to a clock signal. The first feedback node is selectively connected to the second feedback node; The first resistor is selectively connected to the first feedback node; The second resistor is selectively connected to the first voltage node; and The first feedback node is selectively connected to a second voltage node, which is configured to receive a second voltage level different from the first voltage level.

2. The voltage generating system according to claim 1, wherein the clock signal is a first clock signal, and wherein the voltage generating system further comprises: A control signal generator is configured to generate a plurality of control signals in response to the output of the comparator, in response to the first clock signal, and in response to the second clock signal, wherein the period of the second clock signal is greater than the period of the first clock signal. The control signal generator is configured to generate a first control signal and a second control signal among the plurality of control signals having a first logic level in response to the second clock signal having a first logic level of the second clock signal; The control signal generator is configured to generate the first control signal and the second control signal as having the first logic level of the comparator's output within a predetermined number of cycles of the first clock signal; and The control signal generator is configured to generate the first control signal and the second control signal as having a second logic level different from the first logic level of the plurality of control signals in response to the comparator's output having a second logic level different from the first logic level of the comparator's output and the second clock signal having a second logic level different from the first logic level of the second clock signal.

3. The voltage generation system according to claim 2, wherein the first logic level of the plurality of control signals is a logic high level, the first logic level of the second clock signal is the logic high level, and the first logic level of the output of the comparator is the logic high level.

4. The voltage generation system of claim 2, wherein the predetermined number of cycles of the first clock signal includes a first predetermined number of cycles of the first clock signal, wherein the control signal generator is configured to cause the logic level of the second control signal to change to the first logic level of the plurality of control signals for a second predetermined number of cycles of the first clock signal after the logic level of the first control signal changes to the first logic level of the plurality of control signals, and wherein the control signal generator is configured to cause the logic level of the second control signal to change to the second logic level of the plurality of control signals simultaneously with the logic level of the first control signal changing to the second logic level of the plurality of control signals.

5. The voltage generation system of claim 4, wherein the control signal generator is further configured to generate a third control signal among the plurality of control signals as a supplement to the first control signal, wherein the first feedback node is connected to the second feedback node in response to the second control signal having the first logic level of the plurality of control signals, wherein the first resistor is connected to the first feedback node in response to the first control signal having the first logic level of the plurality of control signals, wherein the second resistor is connected to the first voltage node in response to the first control signal having the first logic level of the plurality of control signals, and wherein the first feedback node is connected to the second voltage node in response to the third control signal having the first logic level of the plurality of control signals.

6. The voltage generation system of claim 5, wherein the control signal generator is further configured to generate a fourth control signal among the plurality of control signals as a supplement to the second control signal, and wherein the first feedback node is further connected to the second feedback node in response to the fourth control signal having the second logic level of the plurality of control signals.

7. The voltage generating system according to claim 2, further comprising: A plurality of series-connected flip-flops, wherein each of the plurality of series-connected flip-flops has an input, an output and a clock input, and wherein the clock input of each of the plurality of series-connected flip-flops is connected to a first clock signal node configured to receive the first clock signal; An AND gate having multiple inputs and outputs, wherein the input of each of the multiple series-connected flip-flops is connected to a corresponding input of the multiple inputs, and the output of each of the multiple series-connected flip-flops is connected to a corresponding input of the multiple inputs; and An OR gate having a first input, a second input, and an output, wherein the first input is connected to the output of the AND gate, and the second input is connected to a second clock signal node configured to receive the second clock signal.

8. The voltage generation system of claim 7, wherein the first feedback node is selectively connected to the second feedback node in response to the logic level of the output of the OR gate, wherein the first resistor is selectively connected to the first feedback node in response to the logic level of the output of the OR gate, wherein the second resistor is selectively connected to the first voltage node in response to the logic level of the output of the OR gate, and wherein the first feedback node is selectively connected to the second voltage node in response to the logic level of the output of the OR gate.

9. The voltage generation system of claim 7, wherein the AND gate is a first AND gate and wherein the plurality of series-connected flip-flops are a plurality of series-connected first flip-flops, the voltage generation system further comprising: The second flip-flop has an input connected to the output of the OR gate, an output, and a clock input connected to the first clock signal node; The third flip-flop has an input connected to the output of the second flip-flop, an output, and a clock input connected to the first clock signal node; and The second AND gate has a first input connected to the output of the second flip-flop, a second input connected to the output of the third flip-flop, and an output.

10. The voltage generation system of claim 9, wherein the first feedback node is selectively connected to the second feedback node in response to the logic level of the output of the second AND gate, wherein the first resistor is selectively connected to the first feedback node in response to the logic level of the output of the second flip-flop, wherein the second resistor is selectively connected to the first voltage node in response to the logic level of the output of the second flip-flop, and wherein the first feedback node is selectively connected to the second voltage node in response to the logic level of the output of the second flip-flop.

11. The voltage generating system of claim 1, wherein the first resistor is a variable resistor and the second resistor is a variable resistor.

12. The voltage generating system according to claim 1, wherein the ratio of the first resistor to the second resistor is greater than the ratio of the first capacitor to the second capacitor.

13. An integrated circuit device comprising: A voltage generation system having a feedback loop including a comparator, capacitive feedback, and selectively enabled resistive feedback; A load, which is selectively connected to the output of the voltage generating system; and Controller, wherein the controller is configured to cause the integrated circuit device to: Enable the resistive feedback; Determine whether the output voltage of the voltage generation system has reached the target voltage level; Determine whether the clock signal has a first logic level; The resistive feedback is disabled in response to the output voltage reaching the target voltage level and the clock signal having a second logic level different from the first logic level of the clock signal; Determine whether the output voltage remains below the target voltage level within a predetermined time period; and The resistive feedback is enabled in response to the output voltage remaining below the target voltage level for the predetermined time period.

14. The integrated circuit device of claim 13, wherein the controller is further configured to cause the integrated circuit device to enable the resistive feedback in response to the clock signal having the first logic level of the clock signal.

15. The integrated circuit device of claim 13, wherein the resistive feedback comprises: A first resistor is connected between the output of the voltage generation system and the first feedback node; and A second resistor is connected between the first feedback node and the first voltage node, the first voltage node being configured to receive a first voltage level; The first resistor is selectively connected to the first feedback node; The second resistor is selectively connected to the first voltage node; and The first feedback node is selectively connected to a second voltage node, which is configured to receive a second voltage level different from the first voltage level.

16. The integrated circuit device of claim 15, wherein the first voltage level is lower than the target voltage level of the output of the voltage generation system, and wherein the second voltage level is between the first voltage level and the target voltage level.

17. The integrated circuit device of claim 15, wherein the capacitive feedback comprises: A first capacitor is connected between the output of the voltage generation system and the second feedback node; and The second capacitor is connected between the second feedback node and the first voltage node; The second feedback node is selectively connected to the first feedback node.

18. The integrated circuit device of claim 17, wherein the controller is further configured to cause the integrated circuit device to: Connect the first feedback node to the first resistor, connect the second resistor to the first voltage node, and isolate the first feedback node from the second voltage node before connecting the second feedback node to the first feedback node; and The first feedback node is isolated from the first resistor, the second resistor is isolated from the first voltage node, and the first feedback node is connected to the second voltage node simultaneously with the second feedback node being connected to the first feedback node.

19. A memory comprising: Memory cell array; A voltage generation system having a feedback loop including a comparator, capacitive feedback, and selectively enabled resistive feedback; and A controller for accessing the memory cell array, wherein the controller is configured during access operations of the memory cell array to cause the memory to: The resistive feedback is enabled in response to the output voltage level of the voltage generation system being lower than the target voltage level for the access operation within a predetermined time period, or the clock signal having a first logic level of the clock signal. and The resistive feedback is disabled in response to the output voltage level being higher than the target voltage level and the clock signal having a second logic level of the clock signal that is different from the first logic level of the clock signal.

20. The memory of claim 19, wherein the resistive feedback comprises: A first resistor has a first terminal connected to receive the output voltage level of the voltage generating system and a second terminal; A first transistor having a first source / drain connected to the second end of the first resistor and a second source / drain connected to the first feedback node; The second resistor has a first end connected to the first feedback node and a second end; The second transistor has a first source / drain connected to the second end of the second resistor and a second source / drain connected to a first voltage node, the first voltage node being configured to receive a first voltage level; and A third transistor has a first source / drain connected to the first feedback node and a second source / drain connected to a second voltage node, the second voltage node being configured to receive a second voltage level different from the first voltage level.

21. The memory of claim 20, wherein the first transistor, the second transistor, and the third transistor are configured to be activated in response to the same logic level, wherein the first transistor and the second transistor have control gates connected to a first control signal node configured to receive a first control signal, and wherein the third transistor has a control gate connected to a second control signal node configured to receive a second control signal as a supplement to the first control signal.

22. The memory of claim 20, wherein the capacitive feedback comprises: A first capacitor has a first electrode connected to receive the output voltage level of the voltage generation system and a second electrode connected to a second feedback node; and The second capacitor has a first electrode connected to the second feedback node and a second electrode connected to the first voltage node.

23. The memory according to claim 22, further comprising: A fourth transistor having a first source / drain connected to the first feedback node and a second source / drain connected to the second feedback node.

24. The memory of claim 23, further comprising: The fifth transistor has a first source / drain connected to the first feedback node and a second source / drain connected to the second feedback node; The fourth transistor and the fifth transistor are configured to be activated in response to different logic levels, wherein the fourth transistor has a control gate connected to a third control signal node configured to receive a third control signal, and wherein the fifth transistor has a control gate connected to the fourth control signal node configured to receive a fourth control signal as a supplement to the third control signal.

25. The memory of claim 20, wherein the second voltage level is within the voltage domain of the comparator, and wherein the first voltage level is lower than the second voltage level.

26. The memory of claim 19, wherein the clock signal is a first clock signal, and wherein the controller is configured to cause the memory to enable the resistive feedback in response to the output voltage level of the voltage generation system being lower than the target voltage level for the access operation during the predetermined time period, comprising: The controller is configured to cause the memory to enable the resistive feedback in response to the output voltage level of the voltage generation system being lower than the target voltage level for the access operation within a predetermined number of clock cycles of a second clock signal, the second clock signal having a period shorter than the period of the first clock signal.

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