Multiplication type image sensor

Abstract

A multiplication type image sensor, comprising: a semiconductor layer having a first surface and a second surface; and a wiring layer provided on the second surface. The semiconductor layer includes a plurality of pixels arranged along the first surface. Each of the plurality of pixels includes: a first semiconductor region; a second semiconductor region formed on the second surface side relative to at least a portion of the first semiconductor region and divided for each of the plurality of pixels; and a well region formed in the second semiconductor region in a manner separated from the first semiconductor region and constituting a portion of a pixel circuit. At least a portion of the first semiconductor region and at least a portion of the second semiconductor region form an avalanche multiplication region.

Description

Technical Field

[0001] The present disclosure relates to a multiplication type image sensor. Background Art

[0002] As a multiplication type image sensor, a solid-state imaging element having a semiconductor layer having an avalanche multiplication region is described in Patent Document 1. In one example of the solid-state imaging element described in Patent Document 1, a plurality of pixels provided in the semiconductor layer each have a p-type semiconductor region, an n-type semiconductor region formed in the p-type semiconductor region and forming an avalanche multiplication region together with a part of the p-type semiconductor region, and a p-type well region formed in a p-type semiconductor region in the p-type semiconductor region and constituting a part of the pixel circuit, and the n-type semiconductor region is divided for each of the plurality of pixels.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2017 / 043068 Summary of the invention

[0006] Technical problem to be solved by the invention

[0007] However, in an example of a solid-state imaging element described in Patent Document 1, in order to ensure the voltage resistance of the pixel circuit when a voltage is applied to the p-type semiconductor region so as to apply a voltage higher than the breakdown voltage to the avalanche multiplication region, it is necessary to deplete the area between adjacent n-type semiconductor regions (inter-pixel separation area), which is estimated to be difficult to implement.

[0008] An object of the present disclosure is to provide a multiplication type image sensor capable of ensuring the voltage resistance of a pixel circuit.

[0009] Technical solutions to solve problems

[0010] An amplification type image sensor according to one aspect of the present disclosure includes: a semiconductor layer having a first surface and a second surface on an opposite side to the first surface, and including a plurality of pixels arranged along the first surface; and a wiring layer arranged on the second surface, wherein each of the plurality of pixels has: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type formed on the second surface side relative to at least a portion of the first semiconductor region and divided for each of the plurality of pixels; and a well region of the first conductivity type formed in the second semiconductor region in a manner separated from the first semiconductor region and constituting a portion of a pixel circuit, wherein at least a portion of the first semiconductor region and at least a portion of the second semiconductor region form an avalanche multiplication region.

[0011] In the multiplication type image sensor, in each of the plurality of pixels, an avalanche multiplication region is formed by at least a portion of a first semiconductor region of the first conductivity type and at least a portion of a second semiconductor region of the second conductivity type divided for each of the plurality of pixels, and a well region of the first conductivity type constituting a part of a pixel circuit is formed in the second semiconductor region of the second conductivity type in a manner separated from the first semiconductor region of the first conductivity type. Thus, when a voltage is applied to the first semiconductor region so as to apply a voltage higher than a breakdown voltage to the avalanche multiplication region, the pixel circuit is not easily affected by the voltage. Therefore, according to the multiplication type image sensor, the voltage resistance of the pixel circuit can be ensured.

[0012] In the multiplication type image sensor according to one aspect of the present disclosure, the second semiconductor region may be divided into sections for each of the plurality of pixels by excluding a portion of the first semiconductor region. This can suppress crosstalk between adjacent pixels.

[0013] In the multiplication type image sensor of one aspect of the present disclosure, the second semiconductor region may be divided for each of the plurality of pixels by a groove formed in the semiconductor layer so as to open on the second surface side. This can suppress crosstalk between adjacent pixels.

[0014] In the multiplication type image sensor according to one aspect of the present disclosure, the well region may be formed in the second semiconductor region so as to be separated from the trench. This can ensure the reliability of the voltage resistance of the pixel circuit.

[0015] In the multiplication type image sensor of one aspect of the present disclosure, the well region may be formed in the second semiconductor region so as to be in contact with the trench. This allows a high density arrangement of a plurality of pixels, that is, an improvement in the aperture ratio of the image sensor.

[0016] In the multiplication type image sensor of one aspect of the present disclosure, the second semiconductor region may be electrically connected to the wiring layer at the center of the second semiconductor region when viewed in a direction perpendicular to the first surface. This allows charges generated by each of the plurality of pixels to be sent to the wiring layer in a balanced manner.

[0017] In the multiplication type image sensor of one aspect of the present disclosure, each of the plurality of pixels may include a plurality of well regions divided from each other in the second semiconductor region as the well region. Thus, independent voltages of the plurality of well regions can be applied to the pixel circuit.

[0018] Effects of the Invention

[0019] According to the present disclosure, it is possible to provide a multiplication type image sensor capable of ensuring the voltage resistance of a pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a cross-sectional view of a portion of the multiplication type image sensor according to the first embodiment.

[0021] Figure 2 yes Figure 1 A bottom view of a portion of a semiconductor layer of a multiplication type image sensor is shown.

[0022] Figure 3 yes Figure 1 A top view of a portion of a multiplication type image sensor is shown.

[0023] Figure 4 This is a cross-sectional view of a portion of the multiplication type image sensor according to the second embodiment.

[0024] Figure 5 yes Figure 4 A bottom view of a portion of a semiconductor layer of a multiplication type image sensor is shown.

[0025] Figure 6 This is a cross-sectional view of a portion of the multiplication type image sensor according to the third embodiment.

[0026] Figure 7 yes Figure 6 A bottom view of a portion of a semiconductor layer of a multiplication type image sensor is shown.

[0027] Figure 8 This is a bottom view of a portion of the semiconductor layer of the multiplication type image sensor according to the first modification.

[0028] Fig. 9 It is a cross-sectional view of a part of the multiplication type image sensor according to the second modification.

[0029] Fig.10 yes Fig. 9 A bottom view of a portion of a semiconductor layer of a multiplication type image sensor is shown.

[0030] Fig.11 It is a cross-sectional view of a part of the multiplication type image sensor according to the third modification.

[0031] Fig.12 yes Fig.11 A bottom view of a portion of a semiconductor layer of a multiplication type image sensor is shown. DETAILED DESCRIPTION

[0032] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, the same reference numerals are given to the same or corresponding parts in each figure, and repeated descriptions are omitted.

[0033] [First embodiment]

[0034] like Figure 1 and Figure 2 As shown, the multiplication type image sensor 1A has a semiconductor layer 2. The semiconductor layer 2 has a first surface 2a and a second surface 2b opposite to the first surface 2a. The semiconductor layer 2 includes a plurality of pixels 20 arranged along the first surface 2a. The plurality of pixels 20 are arranged in a matrix, for example.

[0035] Each pixel 20 has a first semiconductor region 2A of a first conductivity type and a second semiconductor region 2B of a second conductivity type. The first semiconductor region 2A is composed of a p+ type semiconductor region 21, a p- type semiconductor region 22, and a p-type semiconductor region 23. The second semiconductor region 2B is composed of an n- type semiconductor region 24, an n-type semiconductor region 25, and an n-type semiconductor region 26.

[0036] The p+ type semiconductor region 21 is a layered region along the first surface 2a, and is formed over a plurality of pixels 20 (i.e., continuous in the semiconductor layer 2). As an example, the impurity concentration of the p+ type semiconductor region 21 is 1×10 18 cm -3 As described above, the thickness of the p + -type semiconductor region 21 is about 1.0 μm.

[0037] The p-type semiconductor region 22 is a region extending from the p+ type semiconductor region 21 to the second surface 2b and is formed over a plurality of pixels 20. As an example, the impurity concentration of the p-type semiconductor region 22 is 1×10 16 cm -3 Hereinafter, the thickness of the p-type semiconductor region 22 is about 10 μm.

[0038] The p-type semiconductor region 23 is a layered region extending substantially parallel to the first surface 2a in the p-type semiconductor region 22, and is formed over a plurality of pixels 20. As an example, the impurity concentration of the p-type semiconductor region 23 is 5×10 16 cm -3 Above and 1×10 18 cm -3 Hereinafter, the thickness of the p-type semiconductor region 23 is approximately 1.0 μm.

[0039] The n-type semiconductor region 24 is a region extending from the second surface 2b in the portion of the p-type semiconductor region 22 located closer to the second surface 2b than the p-type semiconductor region 23, and is divided for each pixel 20. The impurity concentration of the n-type semiconductor region 24 is 1×10 16 cm -3 Hereinafter, the thickness of the n-type semiconductor region 24 is about 1.0 μm.

[0040] The n-type semiconductor region 25 is a layered region along the end portion of the n-type semiconductor region 24 on the first surface 2a side, and is divided for each pixel 20. The impurity concentration of the n-type semiconductor region 25 is 5×10 16 cm -3 Above and 1×10 18 cm -3 Hereinafter, the thickness of the n-type semiconductor region 25 is approximately 1.0 μm.

[0041] The n-type semiconductor region 26 is a region along the second surface 2b in the center of the n-type semiconductor region 24 when viewed from a direction perpendicular to the first surface 2a. The impurity concentration of the n-type semiconductor region 26 is 1×10 16 cm -3 As described above, the thickness of the n-type semiconductor region 26 is about 0.5 μm.

[0042] In the semiconductor layer 2, the second semiconductor region 2B is formed on the second surface 2b side relative to a portion of the first semiconductor region 2A, and is divided for each pixel 20. The second semiconductor region 2B is divided for each pixel 20 by another portion of the first semiconductor region 2A. Specifically, in adjacent pixels 20, a portion of the p-type semiconductor region 22 (a portion of the p-type semiconductor region 22 excluding a portion overlapping with the n-type semiconductor region 25 when viewed from a direction perpendicular to the first surface 2a) is arranged between the second semiconductor region 2B of one pixel 20 and the second semiconductor region 2B of another pixel 20.

[0043] In each pixel 20, a photoelectric conversion region is formed by the p-type semiconductor region 22 and the portion of the p-type semiconductor region 23 that overlaps with the n-type semiconductor region 25 when viewed from a direction perpendicular to the first surface 2a, and the n-type semiconductor region 25. In addition, in each pixel 20, an avalanche multiplication region is formed by the portion of the p-type semiconductor region 23 that overlaps with the n-type semiconductor region 25 when viewed from a direction perpendicular to the first surface 2a, the n-type semiconductor region 25, and the portion between the p-type semiconductor region 22. That is, the avalanche multiplication region is formed by a portion of the first semiconductor region 2A and a portion of the second semiconductor region 2B. The avalanche multiplication region is a region that has the function of multiplying charge avalanche, and is a region that can generate 3×10 5 ~4×10 5 The area of ​​electric field strength is V / cm.

[0044] Each pixel 20 has a p-type well region 27 as a well region of the first conductivity type. The p-type well region 27 is a region in the n-type semiconductor region 24 that reaches the second surface 2b, and is covered by the n-type semiconductor region 24 except for the second surface 2b side. That is, the p-type well region 27 is formed in the second semiconductor region 2B in a manner separated from the first semiconductor region 2A (i.e., physically and electrically separated from the first semiconductor region 2A). In the present embodiment, the p-type well region 27 extends in a ring shape in a manner surrounding the n-type semiconductor region 26 when viewed from a direction perpendicular to the first surface 2a.

[0045] The p-type well region 27 constitutes a part of a plurality of pixel circuits 50. Each pixel circuit 50 is an n-type MOSFET (metal-oxide-semiconductor field-effect transistor) having a pair of channel regions (source region and drain region) 51 and a gate electrode 52 formed in the p-type well region 27. In addition to a transistor for reading a signal charge flowing into the n-type semiconductor region 24 via the n-type semiconductor region 26, each pixel circuit 50 also constitutes a transistor for amplification, a transistor for resetting, and the like.

[0046] As an example, the semiconductor layer 2 constructed as described above is manufactured as follows. First, a p-type semiconductor region 22 is formed on a substrate that becomes a p+ type semiconductor region 21 by epitaxial growth. Next, a p-type semiconductor region 23 is formed in the p-type semiconductor region 22 by ion implantation. Next, a plurality of n-type semiconductor regions 24 and a plurality of n-type semiconductor regions 25 are formed in the p-type semiconductor region 22 by pattern formation based on photolithography and ion implantation. Next, an n-type semiconductor region 26 and a p-type well region 27 are formed in each n-type semiconductor region 24 by pattern formation based on photolithography and ion implantation. Next, a plurality of channel regions 51 are formed in each p-type well region 27 by pattern formation based on photolithography and ion implantation. Finally, the substrate is thinned by grinding to form the p+ type semiconductor region 21. In addition, the p-type semiconductor region 22 and the p-type semiconductor region 23 can also be formed on the substrate that becomes the p+ type semiconductor region 21 by epitaxial growth.

[0047] The multiplication type image sensor 1A further includes a wiring layer 3. The wiring layer 3 is provided on the second surface 2b of the semiconductor layer 2. The wiring layer 3 includes an insulating layer 31, a plurality of wirings 32, and a plurality of contact plugs 33. The plurality of wirings 32 and the plurality of contact plugs 33 are formed in the insulating layer 31. The n-type semiconductor region 26 is electrically connected to the corresponding wirings 32 via the contact plugs 33. That is, the second semiconductor region 2B is electrically connected to the wiring layer 3 at the center of the second semiconductor region 2B when viewed from a direction perpendicular to the first surface 2a. Each part of the pixel circuit 50 is electrically connected to the corresponding wiring 32 via the contact plugs 33. Each wiring 32 is electrically connected to, for example, a CMOS reading circuit part of the multiplication type image sensor 1A.

[0048] The multiplication type image sensor 1A further includes an electrode layer 4. Figure 1 and Figure 3 As shown, the electrode layer 4 is provided on the first surface 2a of the semiconductor layer 2. The electrode layer 4 is electrically connected to the p+ type semiconductor region 21. The electrode layer 4 has a plurality of openings 4a. Each opening 4a overlaps with the n-type semiconductor region 25 of each pixel 20 when viewed from a direction perpendicular to the first surface 2a. The electrode layer 4 is made of, for example, metal, and extends in a grid-like manner to form a plurality of openings 4a. Each opening 4a functions as a light incident opening for each pixel 20.

[0049] The multiplication type image sensor 1A constructed as described above operates as follows. That is, when a voltage is applied to the p+ type semiconductor region 21 via the electrode layer 4 so as to apply a reverse bias voltage of a predetermined value to the pn junction formed in the avalanche multiplication region (i.e., to apply a voltage higher than the breakdown voltage to the avalanche multiplication region), a 3×10 5 ~4×10 5 In this state, if light is incident on the photoelectric conversion region of each pixel 20 through each opening 4a of the electrode layer 4, the charge generated by light absorption is avalanche multiplied in each pixel 20, and the multiplied signal charge flows into the n-type semiconductor region 24 and is read by the plurality of pixel circuits 50.

[0050] As described above, in the multiplication type image sensor 1A, in each pixel 20, an avalanche multiplication region is formed by a part of the p-type first semiconductor region 2A and a part of the n-type second semiconductor region 2B divided for each pixel 20, and the p-type well region 27 constituting a part of the plurality of pixel circuits 50 is formed in the n-type second semiconductor region 2B in a manner separated from the p-type first semiconductor region 2A. Thus, when a voltage is applied to the first semiconductor region 2A so as to apply a voltage higher than the breakdown voltage to the avalanche multiplication region, each pixel circuit 50 is not easily affected by the voltage. Therefore, according to the multiplication type image sensor 1A, the voltage resistance of each pixel circuit 50 can be ensured.

[0051] In addition, in the multiplication type image sensor 1A, the second semiconductor region 2B is divided by another portion of the first semiconductor region 2A for each pixel 20. This can suppress the occurrence of crosstalk between adjacent pixels 20.

[0052] In the multiplication type image sensor 1A, the center of the second semiconductor region 2B when viewed in a direction perpendicular to the first surface 2a is electrically connected to the wiring layer 3. Thus, charges generated in each pixel 20 can be sent to the wiring layer 3 in a balanced manner.

[0053] [Second embodiment]

[0054] like Figure 4 and Figure 5 As shown, the multiplication type image sensor 1B is different from the multiplication type image sensor 1A described above in that the second semiconductor region 2B is divided by the groove 60 for each pixel 20. In the multiplication type image sensor 1B, the groove 60 is formed in the semiconductor layer 2 in a manner opening on the second surface 2b side. The groove 60 extends in a manner passing through adjacent pixels 20, for example, in a lattice shape when viewed from a direction perpendicular to the first surface 2a. The groove 60 has an insulating film 61 formed along the inner surface and a metal component 62 arranged inside. In addition, an insulating component or the like may be arranged in the groove 60 instead of the metal component 62.

[0055] In the multiplication type image sensor 1B, the bottom surface of the groove 60 is located on the first surface 2a side relative to the p-type semiconductor region 23, so that the second semiconductor region 2B (specifically, the n-type semiconductor region 24 and the n-type semiconductor region 25) is divided for each pixel 20. The position of the bottom surface of the groove 60 only needs to be a position that at least divides the second semiconductor region 2B for each pixel 20, and for example, it does not need to reach the p-type semiconductor region 23. The p-type well region 27 is formed in the second semiconductor region 2B (specifically, in the n-type semiconductor region 24) in a manner away from the groove 60. The p-type well region 27 is covered by the n-type semiconductor region 24 except for the second surface 2b side.

[0056] In the multiplication type image sensor 1B, similarly to the multiplication type image sensor 1A described above, in each pixel 20, an avalanche multiplication region is formed by a portion of the p-type first semiconductor region 2A and a portion of the n-type second semiconductor region 2B divided for each pixel 20, and a p-type well region 27 constituting a portion of a plurality of pixel circuits 50 is formed in the n-type second semiconductor region 2B in a manner separated from the p-type first semiconductor region 2A. Thus, when a voltage is applied to the first semiconductor region 2A so as to apply a voltage higher than a breakdown voltage to the avalanche multiplication region, each pixel circuit 50 is not easily affected by the voltage. Therefore, according to the multiplication type image sensor 1B, the voltage resistance of each pixel circuit 50 can be ensured.

[0057] In the multiplication type image sensor 1B, the second semiconductor region 2B is divided for each pixel 20 by the grooves 60 formed in the semiconductor layer 2 so as to open on the second surface 2b side. This can suppress the occurrence of crosstalk between adjacent pixels 20.

[0058] In addition, in the multiplication type image sensor 1B, the p-type well region 27 is formed in the second semiconductor region 2B so as to be separated from the trench 60. Thus, it is possible to achieve reliability in ensuring the withstand voltage of the plurality of pixel circuits 50.

[0059] [Third Embodiment]

[0060] like Figure 6 and Figure 7 As shown in FIG. 1 , the multiplication type image sensor 1C is different from the multiplication type image sensor 1B described above in that the p-type well region 27 is formed in the second semiconductor region 2B in such a manner as to be in contact with the trench 60. In the multiplication type image sensor 1C, the p-type well region 27 is formed in the n-type semiconductor region 24 in such a manner as to be in contact with the trench 60. The p-type well region 27 is covered by the n-type semiconductor region 24 and the trench 60 except on the second surface 2b side.

[0061] In the multiplication type image sensor 1C, similarly to the multiplication type image sensor 1A described above, in each pixel 20, an avalanche multiplication region is formed by a portion of the p-type first semiconductor region 2A and a portion of the n-type second semiconductor region 2B divided for each pixel 20, and a p-type well region 27 constituting a portion of a plurality of pixel circuits 50 is formed in the n-type second semiconductor region 2B in a manner separated from the p-type first semiconductor region 2A. Thus, when a voltage is applied to the first semiconductor region 2A so as to apply a voltage higher than a breakdown voltage to the avalanche multiplication region, each pixel circuit 50 is not easily affected by the voltage. Therefore, according to the multiplication type image sensor 1C, the voltage resistance of each pixel circuit 50 can be ensured.

[0062] In the multiplication type image sensor 1C, similarly to the multiplication type image sensor 1B, the second semiconductor region 2B is divided for each pixel 20 by the grooves 60 formed in the semiconductor layer 2 so as to open on the second surface 2b side. This can suppress crosstalk between adjacent pixels 20.

[0063] In the multiplication type image sensor 1C, the p-type well region 27 is formed in the second semiconductor region 2B so as to be in contact with the trench 60. This allows the plurality of pixels 20 to be arranged at a higher density, that is, the aperture ratio of the image sensor to be improved.

[0064] [Modifications]

[0065] The present disclosure is not limited to the first to third embodiments described above. Figure 8 As shown in FIG. 1 , each pixel 20 may include a plurality of p-type well regions 27 that are separated from each other in the second semiconductor region 2B. Figure 8 In the example shown, a plurality of p-type well regions 27 are formed in the n-type semiconductor region 24, and each p-type well region 27 constitutes a pixel circuit 50. Thus, an independent voltage in each p-type well region 27 can be applied to the pixel circuit 50.

[0066] In addition, if Fig. 9 and Fig.10 As shown, by forming the n-type well region 28 in the p-type well region 27, the p-type well region 27 can also constitute a part of the pixel circuit 50. Fig. 9 and Fig.10 In the example shown, one pixel circuit 50 is an n-type MOSFET having a pair of channel regions (source region and drain region) 51 and a gate electrode 52 formed in a p-type well region 27, and the other pixel circuit 50 is a p-type MOSFET having a pair of channel regions (source region and drain region) 53 and a gate electrode 52 formed in an n-type well region 28.

[0067] In addition, if Fig.11 and Fig.12 As shown, in each pixel 20, the second semiconductor region 2B may be electrically connected to the wiring layer 3 at the end of the second semiconductor region 2B when viewed in a direction perpendicular to the first surface 2a. Fig.11 and Fig.12 In the illustrated example, the p-type well region 27 formed in the n-type semiconductor region 24 has no hole when viewed from a direction perpendicular to the first surface 2 a , and the n-type semiconductor region 26 is located at the end of the n-type semiconductor region 24 .

[0068] In addition, the electrode layer 4 may be formed in a frame shape on the p+ type semiconductor region 21 in a manner of surrounding the plurality of pixels 20. In addition, the electrode layer 4 may be formed in a layer shape on the p+ type semiconductor region 21 by a material having conductivity and light transmittance (e.g., ITO, etc.). In addition, instead of the electrode layer 4, a voltage may be applied to the first semiconductor region 2A via a through electrode extending from the metal component 62 in the groove 60 or the second surface 2b of the semiconductor layer 2 to the first surface 2a side.

[0069] In addition, the n-type semiconductor region 25 is not formed on the semiconductor layer 2, and in each pixel 20, the avalanche multiplication region can also be formed by the portion of the p-type semiconductor region 23 that overlaps with the n-type semiconductor region 24 when viewed from a direction perpendicular to the first surface 2a, the end of the n-type semiconductor region 24 on the side of the first surface 2a, and the portion between them in the p-type semiconductor region 22. In addition, the pixel circuit 50 is not limited to MOSFET, and can also be a JFET (junction field-effect transistor), a bipolar transistor, etc. In addition, the conductivity types of the p-type and n-type can also be opposite to the above. That is, the first conductivity type can also be n-type and the second conductivity type can be p-type. In addition, multiple pixels 20 can also be arranged one-dimensionally along the first surface 2a of the semiconductor layer 2.

[0070] Description of Reference Numerals

[0071] 1A, 1B, 1C…Multiplication type image sensor

[0072] 2…Semiconductor layer

[0073] 2a…1st surface

[0074] 2b…2nd surface

[0075] 2A…1st semiconductor region

[0076] 2B…Second semiconductor region

[0077] 3…Wiring layer

[0078] 20... pixels

[0079] 27…p-type well region (well region)

[0080] 50...Pixel circuit

[0081] 60…trench.

Claims

1. A multiplication type image sensor, characterized in that: include: a semiconductor layer having a first surface and a second surface on the opposite side of the first surface, and including a plurality of pixels arranged along the first surface; and a wiring layer provided on the second surface, Each of the plurality of pixels has: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type formed on one side of the second surface with respect to at least a portion of the first semiconductor region and divided for each of the plurality of pixels; and a first conductivity type well region constituting a part of the pixel circuit is formed in the second semiconductor region so as to be separated from the first semiconductor region, At least a portion of the first semiconductor region and at least a portion of the second semiconductor region form an avalanche multiplication region. A portion of the second semiconductor region where the well region is formed is continuous with a portion of the second semiconductor region where the avalanche multiplication region is formed.

2. The multiplication type image sensor according to claim 1, wherein: The second semiconductor region is divided into sections for each of the plurality of pixels by a portion of the first semiconductor region other than the at least one portion.

3. The multiplication type image sensor according to claim 1, wherein: The second semiconductor region is divided into sections for each of the plurality of pixels by a trench formed in the semiconductor layer so as to open on one side of the second surface.

4. The multiplication type image sensor according to claim 3, wherein: The well region is formed in the second semiconductor region so as to be separated from the trench.

5. The multiplication type image sensor according to claim 3, wherein: The well region is formed in the second semiconductor region so as to be in contact with the trench.

6. The multiplication type image sensor according to any one of claims 1 to 5, characterized in that: The second semiconductor region is electrically connected to the wiring layer at a center portion of the second semiconductor region when viewed in a direction perpendicular to the first surface.

7. The multiplication type image sensor according to any one of claims 1 to 5, characterized in that: Each of the plurality of pixels includes, as the well region, a plurality of well regions partitioned from one another in the second semiconductor region.

8. The multiplication type image sensor according to claim 6, wherein: Each of the plurality of pixels includes, as the well region, a plurality of well regions partitioned from one another in the second semiconductor region.

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