Semiconductor integrated circuits and their design methodologies, design support systems and programs

Abstract

This invention relates to a semiconductor integrated circuit and its design method, design support system, and program. The semiconductor integrated circuit of an embodiment includes multiple memories and a first control circuit for controlling the multiple memories. The first control circuit includes: a first state transition circuit that performs at least one of write control and read control when the multiple memories are in operation; and a second state transition circuit connected to the first state transition circuit, enabling the first state transition circuit to sequentially perform tests on the multiple memories.

Description

[0001] [Citation of relevant applications]

[0002] This application asserts priority based on the prior rights of Japanese Patent Application No. 2021-015745, filed on February 3, 2021, and Japanese Patent Application No. 2021-110627, filed on July 2, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of the present invention relate to a semiconductor integrated circuit and its design method, design support system and program. Background Technology

[0004] In semiconductor integrated circuits, the grouping of test objects for memory via Build-In Self-Test (BIST) is shifting towards configuration-based partitioning. This is to mitigate the wiring clutter that arises in partitioning based on memory type or test cycle information. Furthermore, in the currently mainstream configuration-based memory grouping, multiple memories are controlled by a single BIST control circuit. Grouping is performed regardless of the memory's configuration. Additionally, grouping is independent of the test cycle during testing. Summary of the Invention

[0005] In one embodiment of the present invention, a semiconductor integrated circuit and its design method, design support system and program are provided for reducing the retrial of memory groups and preventing the increase in peak power caused by simultaneous switching during memory testing.

[0006] The semiconductor integrated circuit of the embodiment includes multiple memories and a first control circuit for controlling the multiple memories. The first control circuit includes: a first state transition circuit that performs at least one of write control and read control when the multiple memories are in operation; and a second state transition circuit connected to the first state transition circuit that enables the first state transition circuit to sequentially perform tests on the multiple memories.

[0007] Based on the aforementioned configuration, a semiconductor integrated circuit and its design method, design support system, and program can be provided to reduce the retry of memory groups and prevent the increase in peak power caused by simultaneous switching during memory testing. Attached Figure Description

[0008] Figure 1A This is a schematic diagram illustrating the partitioning state of the memory of the semiconductor integrated circuit according to the first embodiment.

[0009] Figure 1BThis is a schematic diagram illustrating the partitioning state of the memory of the semiconductor integrated circuit according to the first embodiment.

[0010] Figure 1C This is a schematic diagram illustrating the partitioning state of the memory of the semiconductor integrated circuit according to the first embodiment.

[0011] Figure 1D This is a block diagram of the semiconductor integrated circuit according to the first embodiment.

[0012] Figure 1E This is an explanatory diagram of the BIST control circuit of the first embodiment.

[0013] Figure 1F This is an operational diagram illustrating the use of a serial control FSM.

[0014] Figure 2A This is the timing diagram of the operation of the semiconductor integrated circuit in the first example of the first embodiment.

[0015] Figure 2B This is the timing diagram of the operation of the semiconductor integrated circuit in the second example of the first embodiment.

[0016] Figure 3 This is a block diagram of the semiconductor integrated circuit according to the second embodiment.

[0017] Figure 4 This is a block diagram of the clock phase control circuit.

[0018] Figure 5 This is a timing diagram of the operation of the semiconductor integrated circuit in the second embodiment.

[0019] Figure 6 This is a schematic diagram illustrating the partitioning state of the memory of the semiconductor integrated circuit according to the third embodiment.

[0020] Figure 7 This is a block diagram of the semiconductor integrated circuit according to the third embodiment.

[0021] Figure 8 This is a block diagram of the counter control circuit.

[0022] Figure 9 This is the timing diagram of the operation of the semiconductor integrated circuit in the third embodiment.

[0023] Figure 10 This is a schematic diagram illustrating the structure of the design support system for implementing the method.

[0024] Figure 11 This is a detailed functional block diagram of the server and storage media of the implementation method design support system.

[0025] Figure 12This is a flowchart of memory partitioning applicable to the design support system of the implementation method. Detailed Implementation

[0026] Next, embodiments will be described with reference to the accompanying drawings. In the following description or accompanying drawings, the same reference numerals are used to denote the same constituent elements, and descriptions are omitted. The drawings are schematic diagrams. Furthermore, the embodiments shown below illustrate apparatus or methods used to embody the technical concept. Various modifications can be made to the embodiments within the scope of the claims.

[0027] (Semiconductor integrated circuit of the first embodiment)

[0028] like Figure 1A As shown, a plurality of memory modules MEMA1~MEMAN, MEMB1~MEMBN, MEMC1~MEMCN, and MEMC1~MEMCN are divided in the semiconductor substrate 100. Memory modules MEMA1~MEMAN are configured in block A, memory modules MEMB1~MEMBN are configured in block B, memory modules MEMC1~MEMCN are configured in block C, and memory modules MEMD1~MEMDN are configured in block D.

[0029] Each block can also be designated as a functional block. A functional block refers to a semiconductor integrated circuit (IC) structure with a specific function. For example, integrated circuits such as Static Random Access Memory (SRAM), Read Only Memory (ROM), Dynamic Random Access Memory (DRAM), and Central Processing Unit (CPU) are functional blocks. Alternatively, functional blocks can also be obtained by dividing closely spaced memories into blocks.

[0030] Regarding memory types, there are various types, including single-port memory and dual-port memory. Grouping memory types of different kinds together complicates the test control circuitry. Therefore, it's also possible to divide memory of the same type into blocks. In other words, when multiple memory units are grouped into multiple blocks, memory units of the same type can be grouped together.

[0031] When the clock signals connected to the memory have different frequencies, the test control circuitry becomes more complex. That is, when multiple memories are grouped into multiple blocks, memories connected to the same clock signal can be grouped together. Alternatively, they can be combined and divided into blocks. This partitioning can also be viewed as configuration-based partitioning.

[0032] In the following explanation, it is assumed that blocks A, B, C, and D all operate at the same clock frequency, and the memory within the blocks is of the same type in the classification of single-port memory and dual-port memory, etc.

[0033] Figure 1B An example of a grouping of memory contained in block A.

[0034] like Figure 1B As shown, let's say block A contains, for example, 3 memories. The loop values ​​represent the test loop values ​​required for each memory.

[0035] The memory contained in block A is divided into sub-blocks A1 and A2 based on the number of memory tests performed during memory testing, i.e., the number of test loops. This type of segmentation based on test loops... Figure 1A The blocks shown are partitioned based on configuration. Memory groups are divided according to the number of test cycles derived as an indicator based on the word count and / or bit width of each memory, and test algorithm information. The memory with the largest number of test cycles is set as a threshold, and the remaining memories are partitioned within a range controlled to the threshold. In this way, in the first embodiment, the three memories are divided into two groups, A1 and A2, using the number of test cycles as an indicator. Group A1 contains MEMA1 with 10,000 test cycles. Group A2 contains MEMA2 with 6,000 cycles and MEMA3 with 4,000 cycles. The 10,000 cycles of MEMA1 is set as the threshold, and the sum of the test cycle numbers of MEMA2 and MEMA3 does not exceed the threshold. Furthermore, BIST control circuits A1 and A2 for controlling memory testing are configured for groups A1 and A2, respectively. The partitioning of memory groups within blocks using these test cycle numbers as indicators can also be considered as partitioning of nearby memories. Here, nearby memories refer to memories that are likely to be tested using the same BIST control circuit.

[0036] When dividing multiple memories contained in a block into multiple sub-blocks, one of the memories that requires the largest number of test cycles during memory testing can be set as a sub-block, and the remaining memories can be set as another sub-block in such a way that the total number of test cycles for the memory is less than the largest number of test cycles.

[0037] Furthermore, BIST refers to Built-in Self Test, which, for example, refers to tester actions performed within the chip, including "generating test patterns" or "checking test results against expected values." The BIST control circuitry includes the on-chip circuitry that controls these tester actions.

[0038] Although not illustrated, blocks B, C, and D are similarly divided. Furthermore, regarding memory, the required number of test cycles increases proportionally to the number of words and bits, and the area of ​​the BIST control circuit also increases. When memories with smaller test cycle counts are grouped together with those with larger test cycle counts, the overall number of test cycles is dominated by the memory with the larger test cycle count. Therefore, grouping memories with similar test cycle counts together reduces the impact on the overall number of test cycles or the area of ​​the BIST control circuit.

[0039] Figure 1C This represents the state after partitioning blocks A, B, C, and D using the first embodiment. The number of memory test cycles for the same block is determined by the largest memory test cycle number. Therefore, the largest memory test cycle number is set as the upper limit for the number of test cycles and is set as a threshold. When grouping, groups are formed such that the sum of the memory test cycle numbers does not exceed this threshold.

[0040] Blocks A1 and A2 have BIST control circuits A1 and A2, respectively.

[0041] Blocks B1 and B2 have BIST control circuits B1 and B2 respectively.

[0042] Blocks C1 and C2 respectively have BIST control circuits C1 and C2.

[0043] Blocks D1 and D2 have BIST control circuits D1 and D2 respectively.

[0044] use Figure 1D The semiconductor integrated circuit 1 consisting of blocks A1 and A2, as well as blocks B1 and B2, is described in detail.

[0045] The semiconductor integrated circuit 1 includes a clock generating circuit 53, blocks A1, A2, B1, and B2 connected to the clock generating circuit 53, an access control circuit 54, a BIST access circuit 56 connected to the access control circuit 54, and BIST control circuits A1, A2, B1, and B2 connected to the BIST access circuit 56.

[0046] The clock generation circuit 53 is a circuit that generates a clock signal CLK1 of a certain frequency from the reference clock signal RCLK and supplies it to the internal circuit. For example, it includes a phase synchronization circuit (PLL: Phase Locked Loop). Here, the internal circuit consists of the circuits in blocks A1, A2, B1, B2, etc.

[0047] BIST control circuits A1, A2, B1, and B2 control the BIST test of the memory. BIST control circuits A1, A2, B1, and B2 are synchronized with the memory I / F and the clock signal CLK1 supplied from the clock generation circuit 53. BIST access circuit 56 manages the BIST control circuits A1, A2, B1, and B2.

[0048] Access control circuit 54 controls BIST access circuit 56. Access control circuit 54 may use, for example, a Joint Test Action Group (JTAG) controller (TAPC, Test AccessPort Controller) as defined by the IEEE 1149.1 standard. Alternatively, BIST access circuit 56 may be controlled directly from external terminals.

[0049] The memory I / F is a circuit that performs selection and comparison of expected values ​​between the clock signal CLK1 and the test signals generated from the BIST control circuits A1, A2, B1, and B2. For example, there is one memory I / F for each group in memory MEMA2 and memory MEMA3.

[0050] MEMA2 and MEMA3 are the memory devices that will be tested. Examples of memory devices that can be tested include SRAM, ROM, and DRAM.

[0051] also, Figure 1D Although blocks C1, C2, D1, and D2 are not shown in the diagram, they are constructed in the same manner. In blocks C1, C2, D1, and D2, the BIST access circuit 56 and the signal line for transmitting the clock signal CLK1 are connected in the same way as in blocks A1, A2, B1, and B2.

[0052] The semiconductor integrated circuit of the first embodiment is as follows: Figure 1E As shown, the system includes multiple memories MEMA2 and MEMA3, and a BIST control circuit A2 that controls the multiple memories MEMA2 and MEMA3. The BIST control circuit A2 includes: a first state transition circuit (BIST control FSM) 64, which performs at least one of write control and read control during the operation of the multiple memories; and a second state transition circuit (serial control FSM) 74, connected to the first state transition circuit 64, which enables the first state transition circuit 64 to sequentially perform tests on the multiple memories. Here, the operation of the multiple memories refers, for example, to the testing of the multiple memories.

[0053] like Figure 1EAs shown, block A2 contains BIST control circuit A2, memory interface (I / F), and memory MEMA2 and memory MEMA3.

[0054] BIST control circuit A2 is connected to multiple memory interfaces (I / F).

[0055] The BIST control circuit A2 is connected to memory MEMA2 and memory MEMA3 via memory interface (I / F).

[0056] The BIST control circuit A2 includes a first state transition circuit 64, a data generator 66, an address generator 68, a control signal generator 70, and a result comparison control circuit 72. The first state transition circuit 64 includes a BIST control state machine (FSM: Finite State Machine). The first state transition circuit 64 controls the data generator 66, the address generator 68, the control signal generator 70, and the result comparison control circuit 72.

[0057] The first state transition circuit 64 is a state machine that performs a series of controls, such as read control and / or write control, during memory testing. The data generator 66 is a circuit that generates at least one of the read and write values ​​of the memory. The address generator 68 is a circuit that generates the address value of the memory. The control signal generator 70 is a circuit that generates control signals for at least one of the read and write controls of the memory. The result comparison control circuit is a circuit that generates flags, etc., by comparing the expected value generated by the BIST control circuit 58 with the actual memory data value.

[0058] Data generator 66, address generator 68, control signal generator 70 and result comparison control circuit 72 are connected to memory interface (I / F).

[0059] The BIST control circuit A2 is supplied with a clock signal CLK, a reset signal RS, and an enable signal EN from an external source. The reset signal RS initializes the settings of the BIST control circuit A2, and the enable signal EN controls the on / off operation of the BIST control circuit A2. The clock signal CLK is supplied from the clock generation circuit 53.

[0060] Additionally, a data output signal DO is output from the BIST control circuit A2. The data output signal DO is used to output the value of the internal registers, etc. Blocks A1, B1, B2, C1, C2, D1, and D2 are constructed in the same manner as block A2.

[0061] In the semiconductor integrated circuit 1 of the first embodiment, by incorporating the serial control FSM (state machine) 74, the testing of the memories MEMA2 and MEMA3 contained in block A2 is initiated sequentially. Figure 1F The text indicates that the BIST of the FSM74, which is equipped with serial control, can control the operation of the FSM64. Memory tests can be started sequentially for MEMA2 and MEMA3 contained in group A2.

[0062] Similarly, the BIST control circuit B2 can control the start time of memory tests for MEMB2 and MEMB3, and can start the tests for MEMB3 sequentially after MEMB2.

[0063] Similarly, the BIST control circuit C2 can control the start time of memory tests for MEMC2 and MEMC3, and can start the tests for MEMC3 sequentially after MEMC2.

[0064] Similarly, the BIST control circuit D2 can control the start time of the memory tests of MEMD2 and MEMD3, and can start the tests of MEMD3 sequentially after MEMD2.

[0065] The BIST control circuits A1, B1, C1, and D1 can control the start point of memory testing for MEMA1, MEMB1, MEMC1, and MEMD1, respectively.

[0066] (Example of memory testing operation for a semiconductor integrated circuit in the first example of the first embodiment)

[0067] (Action sequence diagram)

[0068] Figure 2A This is the first example of the timing diagram for the operation of the semiconductor integrated circuit according to the first embodiment. Figure 2A The diagram shows two blocks, A1 and A2, that operate using the clock signal CLK. Memory modules MEMA2 and MEMA3 are sequentially driven according to the state machine as the enable signal EN1 is activated; memory module MEMA1 is activated simultaneously with the enable signal EN2. During the period when the enable signal EN1 is activated, write and / or read operations and wait operations are performed on memory modules MEMA2 and MEMA3. Similarly, during the period when the enable signal EN1 is activated, write and / or read operations are performed on memory modules MEMA2 and MEMA3. During the period when the enable signal EN2 is activated, write and / or read operations are performed on memory module MEMA1.

[0069] During the period t1-t11 when enable signals EN1 and EN2 are simultaneously turned on, memory MEMA1 and MEMA2 are accessed; during the period t11-t12, memory MEMA3 and MEMA1 are accessed.

[0070] exist Figure 2A In the process, the write and / or read operations of memory MEMA2 are repeatedly executed 6000 times during the period t1-t11. The write and / or read operations of memory MEMA3 are repeatedly executed 4000 times during the period t11-t12. The write and / or read operations of memory MEMA1 are repeatedly executed 10000 times during the period t1-t12.

[0071] (Effects in the first example of the first embodiment)

[0072] In the first example of this embodiment, memory access can be decentralized. Therefore, the concentration of peak power can be avoided.

[0073] Furthermore, to avoid peak power concentration, driving MEMA1, MEMA2, and MEMA3 sequentially requires a total of 20,000 write and / or read cycles. In the first example, by distributing the drive memory during testing, peak power concentration can be reduced and test time shortened.

[0074] (Example of memory testing operation for semiconductor integrated circuit in the second example of the first embodiment)

[0075] Figure 2B This is the first example of the timing diagram of the operation of the semiconductor integrated circuit in the first embodiment. Figure 2B In this approach, a distributed drive for memory access, similar to the first example, is applied to each block. Figure 2B As shown, by adjusting the start time of memory testing between functional blocks A, B, C, and D, and further adjusting the start time of memory testing within each block, simultaneous switching that occurs during memory access can be suppressed. For example, the number of memories that switch simultaneously before reaching 10,000 cycles must be reduced to six or fewer. Here, a functional block refers to an integrated circuit structure with a specific function. For example, integrated circuits such as SRAM, ROM, DRAM, and Central Processing Unit (CPU) are functional blocks. For instance, in functional blocks such as SRAM, the memory that might be tested using the 1BIST control circuit is a memory located near the 1BIST control circuit.

[0076] (Effects in the second example of the first embodiment)

[0077] In the second example of this embodiment, memory access can also be decentralized. Therefore, the concentration of peak power can be avoided.

[0078] In addition, compared to driving in sequence according to block A, block B, block C, and block D to avoid peak power concentration, the test time can be shortened.

[0079] (Semiconductor integrated circuit of the second embodiment)

[0080] The semiconductor integrated circuit of the second embodiment is as follows: Figure 3 As shown, the system includes multiple memories MEMA2 and MEMA3, and a first control circuit (BIST control circuit A2) for controlling the multiple memories MEMA2 and MEMA3. The BIST control circuit A2 includes: a first state transition circuit (BIST control FSM) 64, which performs at least one of write control and read control when the multiple memories MEMA2 and MEMA3 are in operation; and a second state transition circuit (serial control FSM) 74, connected to the first state transition circuit (BIST control FSM) 64, which enables the first state transition circuit 64 to sequentially perform tests on the multiple memories MEMA2 and MEMA3. The operation of the multiple memories MEMA2 and MEMA3 refers to the testing of the multiple memories MEMA2 and MEMA3.

[0081] The semiconductor integrated circuit of the second embodiment further includes a second control circuit, which is capable of controlling at least one memory that is different from the memory controlled by the first control circuit (BIST control circuit A2). The first control circuit (BIST control circuit A2) includes a clock phase control circuit 76, which controls the phase of the clock signal of the first control circuit (BIST control circuit A2) relative to the phase of the clock signal of the second control circuit.

[0082] like Figure 3 As shown, in the semiconductor integrated circuit of the second embodiment, a clock phase control circuit 76 is also included in the BIST control circuit A2. When the clock system is the same, for example, when multiple memories such as BIST are operating, the operation of the clock phase control circuit 76 can shift the clock phase relative to the original clock signal CLK, thereby reducing simultaneous switching caused by memory access. The configurations of the BIST control circuits A1, B1, C1, C2, D1, and D2 are also the same as those of the BIST control circuit A2.

[0083] (A specific example of a clock phase control circuit)

[0084] Figure 4 This is a block diagram of the clock phase control circuit 76.

[0085] The clock phase control circuit 76 includes a delay logic element 78, a phase setting register 80, and a selector 82.

[0086] The delay logic element 78 is a logic circuit used to shift the phase of the clock signal CLKO of the first control circuit (BIST control circuit A2) relative to the original clock signal CLK.

[0087] Phase setting register 80 sets the phase difference between the clock signal of the first control circuit (BIST control circuit A2) and the original clock signal CLK. In other words, phase setting register 80 is used to determine the phase of the output clock signal CLKO relative to the original clock signal CLK. The data link DCH, a data register chain defined by the IEEE 1149.1 standard, is supplied to and output from phase setting register 80.

[0088] Selector 82 selects either the original clock signal CLK or a clock signal with a set phase difference.

[0089] Figure 4 In the middle, the clock signal CLK and the clock signal CLK1 input to the BIST control circuit A2 ( Figure 1D The output clock signal CLKO is the same as the original clock signal CLK, or its phase is offset relative to the original clock signal CLK.

[0090] The select signal SEL is the signal that selects the clock signal CLK.

[0091] The length of the phase setting register 80 changes according to the phase difference between the output clock signal CLKO and the original clock signal CLK. When the phase difference is, for example, 45°, 90°, or 135°, the register requires a length of 2 bits.

[0092] (Action sequence diagram)

[0093] Figure 5 This is a timing diagram of the operation of the semiconductor integrated circuit according to the second embodiment. As an example, only the operation of block A is shown.

[0094] (a) First, before the memory test begins, the phase setting register 80 is accessed from the data link DCH to set the desired phase difference value. The period for register setting is the access period during which the phase setting register 80 is configured.

[0095] (b) Next, after the memory test begins, at time t1, the enable signal EN and the select signal SEL are turned on simultaneously.

[0096] (c) When the enable signal EN and the selection signal SEL change to a high level H, based on the set phase difference value, the output clock signal CLKO, whose phase is offset relative to the original clock signal CLK, is transmitted to the memories MEMA1, MEMA2, and MEMA3, and the test begins at time t2. Here, as shown by arrow A, the phase of the output clock signal CLKO is offset relative to the original clock signal CLK.

[0097] (d) During the period from t2 to t5, write and / or read operations are performed on the memory. MEMA1 operates synchronously with CLK0, and MEMA2 and MEMA3 operate synchronously with CLK1.

[0098] (e) At time t41, the memory write and / or read operations are completed, and when the enable signal EN and the select signal SEL return to low level, the clock phase is restored to normal. Here, as shown by arrow B, the phase difference between the output clock signal CLKO and the clock signal CLK returns to zero, eliminating the phase difference.

[0099] Furthermore, the same driving method can be applied to blocks B, C, and D. Additionally, this operation can also be applied to the first embodiment.

[0100] (Effects of the second implementation)

[0101] This can further suppress simultaneous switching that occurs during memory access.

[0102] (Semiconductor integrated circuit of the third embodiment)

[0103] exist Figure 6 The value in the figure represents the memory partitioning state of the semiconductor integrated circuit in the third embodiment. The value in the figure represents the maximum number of test cycles for the memory contained in each functional block A, B, C, and D.

[0104] The semiconductor integrated circuit of the third embodiment is as follows: Figure 7 As shown, it includes: multiple functional blocks (A to D), multiple memories including at least a first memory, a second memory and a third memory, and control circuits (BIST control circuits A to D) capable of independently controlling the first memory, the second memory and the third memory; and BIST access circuit 56 connected to the control circuits (BIST control circuits A to D) and capable of accessing the control circuits (BIST control circuits A to D).

[0105] BIST access circuit 56 can transmit an enable signal EN to the control circuit (BIST control circuits A to D). The enable signal EN is used to start the control operation of the third memory after the control operation of the first and second memories is completed, or to start the control operation of the first and second memories after the control operation of the third memory is completed.

[0106] BIST access circuit 56 includes a counter control circuit 84 that enables the control circuit (BIST control circuits A to D) via the enable signal EN.

[0107] like Figure 7 As shown, a counter control circuit 84 is incorporated into the BIST access circuit 56 in the third embodiment. Furthermore, the counter control circuit 84 may also be configured independently of the BIST access circuit 56. Additionally, it is described that there are two memories in block A, one memory in block B, two memories in block C, and one memory in block D, but this is not a limitation. As explained in the first and second embodiments, further partitioning based on nearby memories may or may not be performed within each block.

[0108] BIST access circuit 56 is a control circuit that uniformly manages all BIST control circuits A, B, C, and D. At the start of the test, enable signals are output from BIST access circuit 56 to activate BIST control circuits A, B, C, and D. These enable signals are supplied to the BIST control circuits A, B, C, and D of each functional block. The operation of counter control circuit 84 is controlled by transmitting the enable signals to each functional block at different times.

[0109] (A specific example of a counter control circuit)

[0110] Figure 8 This is a block diagram of the counter control circuit 84. It is a circuit structure that enables the BIST control circuits A, B, C, and D to start at any point in time.

[0111] The counter control circuit 84 includes a counter circuit 86, a counter setting register 88, and an AND gate 90.

[0112] When one of the multiple functional blocks A, B, C, and D is activated, the counter circuit 86 counts the number of pulses of the clock signal CLK supplied after the start of the operation, and then starts the operation of the next functional block. The counter circuit 86 counts the clock signal CLK, and outputs a high-level signal H when the set count value is reached.

[0113] The counter setting register 88 is a register circuit used to set the count value. In other words, the counter setting register 88 is a register circuit that counts the number of pulses of the clock signal CLK. The data link DCH, as defined by the IEEE 1149.1 standard, is supplied to and output from the counter setting register 88.

[0114] AND gate 90 is a logic AND gate circuit that outputs the enable signal ENO by the enable signal EN and the clock signal CLK that has passed through the counter circuit 86.

[0115] (Action sequence diagram)

[0116] exist Figure 9 In the above, the memory write and / or read operations of function block B are repeatedly executed 2000 times during the period tE1-t1. The memory write and / or read operations of function block C are repeatedly executed 1200 times during the period tE2-t2. The memory write and / or read operations of function block D are repeatedly executed 5000 times during the period tE3-t4. The memory write and / or read operations of function block A are repeatedly executed 9500 times during the period tE1-t4.

[0117] Figure 9 This is the timing diagram of the operation of the semiconductor integrated circuit in the third embodiment. Figure 9 This is a diagram illustrating a specific example of a timing diagram for counter control. In Figure 9 In this diagram, the memories belonging to functional blocks A, B, C, and D are represented by MEMA, MEMB, MEMC, and MEMD, respectively. The following describes the operations.

[0118] (a) First, before the memory test begins, at time t01, the counter setting register 88 is accessed from the data link DCH to set the required count values ​​for blocks C and D. The period for register setting is the access period during which the counter setting register 88 is set.

[0119] (b) Next, after the memory test begins, for blocks A and B without a set counter value, enable signals EN1 and EN4 are simultaneously turned on at time tE1 to perform the memory test. The period tE1–t1 is the test period for functional block B. The period tE1–t4 is the test period for functional block A.

[0120] (c) Next, after the count value set in function block C is reached, at time tE2, as shown by arrow C, the enable signal EN2 of block C is turned on, and the test of function block C begins. The period from tE2 to t2 is the test period of function block C.

[0121] (d) Next, after reaching the count value set in function block D, at time tE3, as shown by arrow D, the enable signal EN3 of function block D is turned on, and the test of function block D begins. The period from tE3 to t4 is the test period of function block D.

[0122] (Effects of the third embodiment)

[0123] The semiconductor integrated circuit of the third embodiment can provide a BIST control circuit that suppresses simultaneous switching caused by memory access in a test cycle-based partitioning (block level).

[0124] The semiconductor integrated circuit of the third embodiment can individually control the enable signal that starts the BIST control circuit using a counter control circuit. As a result, the BIST control circuit can be started in any cycle and in units of functional blocks, thereby improving the simultaneous switching that occurs during memory access.

[0125] In test-cycle-based partitioning (block level), the test cycle (power consumption) of each BIST control circuit can be used as a parameter to activate the block-level BIST control circuit, thereby improving the simultaneous switching that occurs during memory access.

[0126] (Other implementation methods)

[0127] (a) In the third embodiment, the clocks of multiple memories within a functional block can also be staggered, as in the second embodiment. In this case, Figure 9 In this case, the clock of block A is different from the clocks of blocks B, C, and D. In addition to the effects of the third embodiment, the simultaneous switching that occurs during memory access can also be improved.

[0128] (b) In the embodiment described above, functional blocks A, B, C, and D are all connected to the lines of CLK1. Figure 1D , Figure 7 However, it is also possible to connect to lines with different clocks. For example, function blocks A and B can be connected to CLK1, and function blocks C and D can be connected to CLK2. In this case, the described implementation method can also be applied.

[0129] (c) in the embodiment ( Figure 7 In this example, the number of functional blocks after division is 4, but it is not limited to this. There can be more or fewer.

[0130] (d) in the embodiment ( Figure 1D In a function block, the number of partitions based on the nearest memory is at most 2 (e.g., dividing block A into blocks A1 and A2), but it is not limited to this and can be divided into more than 2.

[0131] (e) in the embodiment ( Figure 1D In a function block, which is divided based on the nearest memory, there can be a maximum of two memory units (for example, function block A2 contains MEMA2 and MEMA3), but it is not limited to this and can contain more than two.

[0132] (Design Methods for Semiconductor Integrated Circuits)

[0133] The following describes the design method of the semiconductor integrated circuit according to the implementation method.

[0134] (a) First, for the multiple memories mounted on the semiconductor integrated circuit, based on the configuration and functional information of the memories, the multiple memories are divided into multiple blocks (A, B, C, D) (for example, refer to...). Figure 1A and Figure 6 ).

[0135] (b) Next, in at least one of the blocks (A), based on the number of memory tests performed during memory testing, i.e., the number of test cycles, the at least one block is divided into multiple sub-blocks (A1, A2) (for example, see reference). Figure 1B ).

[0136] (c) Next, after dividing into multiple sub-blocks, calculate the power consumption information of each block during memory testing, and based on the power consumption information of the multiple blocks, group the multiple blocks into multiple upper-level blocks U1(A) and upper-level blocks U2(B, C, D) (for example, refer to...). Figure 6 and Figure 9 ).

[0137] In the semiconductor integrated circuit design method of the implementation method, when multiple memories are divided into multiple blocks, memories of the same type can also be grouped together.

[0138] In addition, when multiple memories are divided into multiple blocks, memories connected to the same clock signal can also be grouped together.

[0139] Alternatively, when dividing multiple memories contained in a block into multiple sub-blocks, one of the memories that requires the largest number of test cycles during memory testing can be set as a sub-block, and the remaining memories can be set as another sub-block in such a way that the total number of test cycles for the memory is below the largest number of test cycles.

[0140] In addition, in the semiconductor integrated circuit design method of the implementation method, when multiple blocks are divided into multiple upper blocks, the block (A) that requires the maximum power consumption during memory testing can be set as an upper block U1, and the remaining blocks (B, C, D) can be set as another upper block U2 in such a way that the total power consumption of the blocks is less than or equal to the maximum power consumption.

[0141] (Design Support System)

[0142] The semiconductor integrated circuit and its design method described in this embodiment can be applied to design techniques and verification devices used in memory testing that consider low power consumption. The design support system of this embodiment will be described below.

[0143] Figure 10 This is a schematic diagram illustrating the configuration of the design support system 2 in the implementation method. The design support system 2 includes a computer device 10, a CPU server 20, a network 30, and a storage medium 40.

[0144] Design support system 2 includes: a computer device 10, operated by a user via a network 30; a CPU server 20, storing computer programs for design support system 2; and a storage medium 40. The storage medium 40 stores input information data and verification result messages used to execute the computer programs for design support system 2.

[0145] Computer device 10 may be, for example, a personal computer (PC), a thin client terminal, a mobile terminal, or a PDA (Personal Digital Assistant). CPU server 20 may be, for example, an engineering workstation, a mainframe, or a supercomputer. Network 30 may be, for example, the Internet, an intranet, a LAN (Local Area Network), a telephone communication network, or a dedicated line. Storage medium 40 may be, for example, an external storage device such as a hard disk, a semiconductor storage device such as a memory, or a storage medium (media). However, the actual implementation is not limited to these examples.

[0146] Figure 11 This is a detailed functional block diagram of the CPU server 20 and storage medium 40 of the design support system 2 in this implementation method. The design support system 2 includes a CPU server 20 and a storage medium 40 for storing data from the CPU server 20.

[0147] CPU server 20 includes: a memory partitioning processing unit 22, which performs partitioning processing on multiple blocks and multiple memories when multiple blocks contain multiple memories; and a memory BIST circuit generation unit 24, which can perform testing on multiple memories.

[0148] Furthermore, the memory partitioning processing unit 22 may also be a processing device of a CPU or microprocessor or a semiconductor integrated circuit (IC) with the same function. However, it is not limited to these examples in practice.

[0149] The memory partitioning processing unit 22 includes a test cycle calculation unit 221, a test cycle threshold setting unit 222, a first memory partitioning unit 223, a power consumption calculation unit 224, a power consumption threshold setting unit 225, and a second memory partitioning unit 226.

[0150] The test loop calculation unit 221 is capable of calculating the test loop number for each of the multiple memories.

[0151] The test cycle threshold setting unit 222 can set at least one of the test cycle numbers as the test cycle threshold.

[0152] The first memory partitioning unit 223 can partition multiple memories contained in a block into multiple sub-blocks based on the number of test cycles.

[0153] The second memory partitioning unit 226 divides the multiple blocks into multiple upper-level blocks based on the power consumption information of the multiple blocks. Therefore, the second memory partitioning unit 226 can also be called a memory grouping unit.

[0154] The storage medium 40 includes a memory information storage unit 42, a test algorithm information storage unit 44, a test cycle value storage unit 46, a power consumption value storage unit 48, a threshold storage unit 50, and a memory segmentation information storage unit 52.

[0155] The memory information storage unit 42 stores memory definition data 42D. Here, memory definition data refers to data that defines the type of memory (e.g., SRAM, DRAM, clock count, word line and / or data line information, etc.). The test algorithm information storage unit 44 stores test algorithm definition data 44D. Test algorithm definition data, for example, refers to data that defines the test pattern of BIST, the number of test repetitions, etc. The test cycle value storage unit 46 stores test cycle value data 46D for each memory. The power consumption value storage unit 48 stores power consumption value data 48D for each function block. The threshold storage unit 50 stores threshold data 50T for the test cycle and threshold data 50P for power consumption. The memory partitioning information storage unit 52 stores partitioning information data 52P for nearby memories and partitioning information data 52F for function blocks.

[0156] The test loop calculation unit 221 calculates the test loop number of each of the multiple memories based on the memory definition data 42D and the test algorithm definition data 44D, and stores it in the test loop value storage unit 46 as the test loop value data 46D of the multiple memories.

[0157] The test cycle threshold setting unit 222 sets the threshold for the number of test cycles and stores the setting result as threshold data 50T for the number of test cycles in the threshold storage unit 50.

[0158] The first memory partitioning unit 223 performs partitioning processing based on the nearby memory based on the test cycle value data 46D, the threshold data 50T of the number of test cycles, and the threshold data 50P of power consumption for each memory, and stores the partitioned data as partitioning information data 52P of the nearby memory of the sub-block in the memory partitioning information storage unit 52.

[0159] The power consumption calculation unit 224 calculates the power consumption based on the test cycle value data 46D of multiple memories, and stores the calculation result as the power consumption value data 48D of each functional block in the power consumption value storage unit 48.

[0160] The power consumption threshold setting unit 225 sets a power consumption threshold based on the power consumption value data 48D of each function block, and stores the setting result as power consumption threshold data 50P in the threshold storage unit 50.

[0161] The second memory partitioning unit (memory grouping unit) 226 performs function block-level grouping based on the power consumption value data 48D of each function block, the threshold data 50T of the number of test cycles, and the threshold data 50P of power consumption, and stores the grouped data as the function block partitioning information data 52F of the upper-level block in the memory partitioning information storage unit 52.

[0162] The memory BIST circuit generation unit 24 generates a memory BIST circuit for the design support system 2 of the implementation method based on the partition information data 52P of the nearby memory of the sub-block stored in the memory partition information storage unit 52 and the partition information data 52F of the functional block of the upper block.

[0163] (Flowchart of memory partitioning)

[0164] Figure 12 This is a flowchart of memory partitioning for the design support system 2 applicable to the implementation method. (Refer to...) Figure 12 The operation of the design support system for the implementation method is explained.

[0165] (A) First, in step S11, in the memory group, the number of test cycles of the memory is calculated based on the number of words and / or bit width of the memory and the test algorithm.

[0166] (B) Next, in step S12, the memory with the longest test cycle count is determined, divided into independent groups, and the test cycle count is set as a threshold.

[0167] (C) Next, in step S13, the other memories are grouped in a manner that does not exceed the threshold.

[0168] (D) Next, in step S14, it is determined whether the group partitioning has been completed in the nearby memory. If the determination result is no, then return to step S13. If the determination result is yes, then proceed to step S15.

[0169] (E) Next, in step S15, the power consumption generated by the simultaneous switching rate of each functional block is calculated based on the longest test cycle number of the memory group contained in each functional block.

[0170] (F) Next, in step S16, based on the calculated power consumption, the functional block with the maximum value is divided into independent groups, and its power consumption is set as a threshold.

[0171] (G) Next, in step S17, other functional blocks are grouped in a manner that does not exceed a threshold.

[0172] (H) Next, in step S17, it is determined whether group partitioning has been completed in the function block. If the determination result is no, then return to step S17. If the determination result is yes, then end the memory partitioning process.

[0173] In the design support system for the implementation method, memory groups based on configuration information are combined with memory groups based on test cycle counts, and memory grouping is performed according to the aforementioned action flowchart. This minimizes the impact of test cycle counts and suppresses simultaneous switching that accompanies memory access, thereby preventing an increase in peak power during testing.

[0174] (Computer programs used for designing support systems)

[0175] The computer program used to design the support system has the following commands that cause the computer to execute: (1) For multiple memories, the multiple memories are divided into multiple blocks based on the configuration information and functional information of the memories; (2) The number of test cycles required for testing the multiple memories is calculated according to the word count and / or bit width of each memory and the test algorithm; (3) The maximum number of test cycles of the multiple memories contained in at least one of the multiple blocks is set as a first threshold; (4) The memory with the largest number of test cycles is allocated to a sub-block, and the remaining memories contained in at least one block are allocated to another sub-block within the range controlled within the first threshold; (5) The power consumption generated by the simultaneous switching rate of each block is calculated according to the number of test cycles of the multiple blocks; (6) According to the power consumption, one of the multiple blocks with the largest power consumption is allocated to the upper block, and the maximum power consumption is set as a second threshold; (7) The other blocks of the multiple blocks are allocated to the upper block in a manner not exceeding the second threshold.

[0176] The embodiments are illustrative, and the scope of the invention is not limited to these.

Claims

1. A semiconductor integrated circuit, comprising: Multiple memory; The first control circuit controls the plurality of memories; The second control circuit is capable of controlling at least one memory that is different from the memory controlled by the first control circuit; and The first control circuit includes: The first state transition circuit performs at least one of write control and read control when the plurality of memories are in operation; A second state transition circuit, connected to the first state transition circuit, enables the first state transition circuit to sequentially perform tests on the plurality of memories; and A clock phase control circuit controls the phase of the clock signal of the first control circuit relative to the phase of the clock signal of the second control circuit.

2. The semiconductor integrated circuit according to claim 1, wherein the operation of the plurality of memories refers to the testing of the plurality of memories.

3. A semiconductor integrated circuit, comprising: Multiple memories; and The first control circuit controls the plurality of memories; and The first control circuit includes: The first state transition circuit performs at least one of write control and read control when the plurality of memories are in operation; The second state transition circuit is connected to the first state transition circuit and enables the first state transition circuit to perform tests on the plurality of memories sequentially. and Clock phase control circuit; and The clock phase control circuit includes: a delay logic element that causes the phase of the clock signal of the first control circuit to be offset relative to the original clock signal; and a phase setting register that sets the phase difference between the clock signal of the first control circuit and the original clock signal. and a selector, to select either the original clock signal or a clock signal with the phase difference set.

4. The semiconductor integrated circuit according to claim 3, wherein the operation of the plurality of memories refers to the testing of the plurality of memories.

5. A semiconductor integrated circuit comprising: a plurality of functional blocks; a plurality of memories including at least a first memory, a second memory, and a third memory; and a control circuit capable of independently controlling the first memory, the second memory, and the third memory; and An access circuit, connected to the control circuit, is capable of accessing the control circuit; and The access circuit can transmit an enable signal to the control circuit. The enable signal is used to start the control operation of the third memory after the control operation of the first and second memories is completed, or to start the control operation of the first and second memories after the control operation of the third memory is completed. The access circuit includes a counter control circuit that enables the control circuit to start via the enable signal; The counter control circuit includes a counter circuit. When one of the multiple functional blocks is activated, the counter circuit counts the number of pulses of the clock signal supplied after the activation starts, and then activates the next functional block.

6. The semiconductor integrated circuit according to claim 5, wherein the counter control circuit includes a counter setting register for counting the number of pulses of the clock signal.

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