Chip preparation method and chip

Abstract

The present invention relates to the technical field of chip manufacturing, and provides a chip preparation method and chip. The chip preparation method comprises first electroplating an initial wafer to obtain a processed wafer; the initial wafer comprises an initial chip and an alignment chip; and coating a barrier layer on the processed wafer, and patterning the barrier layer to form through-holes for solder joints or alignment points that are subsequently required to be electroplated. Because the area on the alignment chip that performs package alignment is the alignment point, and the cross-sectional area of ​​the alignment point is similar to the cross-sectional area of ​​the solder joint, the height difference between the two structures after electroplating reflow is small, thereby improving the uniformity of the plane where the two structures are located, and thereby facilitating improved uniformity in subsequent wafer grinding.

Description

Technical Field

[0001] The present invention relates to the technical field of chip manufacturing, and in particular to a chip preparation method and the chip. Background Art

[0002] During the chip manufacturing process, chips are continuously processed on wafers of uniform specifications to form chips of different specifications and sizes. On the one hand, in order to reduce the size of the chip so that the chip can be suitable for highly integrated circuits; on the other hand, in order to improve the flatness of the chip, the chip needs to be polished. In addition to equipment requirements, the uniformity of chip grinding also has high requirements for the flatness of the chip itself.

[0003] In the existing technology, wafer-level chips are generally ground and then sliced ​​into single chips after the grinding process. Although this method improves the processing efficiency of the chip, it makes more stringent requirements on the flatness of the wafer-level chip. However, the wafer in the existing technology not only contains effective chips, but also includes alignment mark chips. The existing processing technology makes the height difference between the two large, which makes the overall height uniformity of the wafer-level chip low, resulting in uneven force during grinding, leading to cracking or yield loss. Summary of the Invention

[0004] The present invention aims to solve the technical problem that the existing chip preparation method has low wafer-level chip height uniformity.

[0005] To solve the above technical problems, the present application discloses a method for preparing a chip, which comprises:

[0006] Providing an initial wafer; the initial wafer includes a plurality of initial chips and an alignment chip; each of the plurality of initial chips is provided with an electrode array;

[0007] Performing electroplating pretreatment on the first surface of the initial wafer to obtain a processed wafer; the electrode array is provided on the first surface;

[0008] A barrier layer is coated on the first surface of the processed wafer and patterned; the patterned barrier layer includes a plurality of first through-hole arrays and a second through-hole array; the plurality of first through-hole arrays correspond to the plurality of electrode arrays; the second through-hole array is located on the alignment chip; and a difference between a cross-sectional area of ​​the second through-holes of the second through-hole array and a cross-sectional area of ​​the first through-holes of the first through-hole array is less than or equal to a first threshold;

[0009] Using an electroplating process, solder joints are prepared in the first through holes of the plurality of first through hole arrays, and alignment points are prepared in the second through holes of the second through hole arrays;

[0010] The barrier layer is removed to obtain a target wafer-level chip having a plurality of solder joint arrays and alignment point arrays on the surface.

[0011] Optionally, the height of the second through holes of the second through hole array is equal to the height of the first through holes of the first through hole array;

[0012] The difference between the array pitch of the second through hole array and the array pitch of the first through hole array is less than or equal to a second threshold.

[0013] Optionally, during the packaging process, the packaging device can identify the position of the alignment point array, and then determine the position of the chip to be packaged that has a corresponding positional relationship with the alignment point array based on the position of the alignment point array.

[0014] Optionally, performing electroplating pretreatment on the first surface of the initial wafer to obtain a processed wafer includes:

[0015] A dielectric layer is prepared on the first surface of the initial wafer; the dielectric layer includes a plurality of third through-hole arrays, each of the plurality of third through-hole arrays being used to expose a corresponding electrode array;

[0016] An electroplating seed layer is prepared on the dielectric layer; the electroplating seed layer includes a plurality of groove arrays, and each groove array in the plurality of groove arrays corresponds to an electrode array.

[0017] Optionally, the step of preparing solder joints in the first through-holes of the plurality of first through-hole arrays and preparing alignment points in the second through-holes of the second through-hole arrays by using an electroplating process; and removing the barrier layer to obtain a target wafer-level chip having a plurality of solder joint arrays and an alignment point array on its surface comprises:

[0018] Using an electroplating process, a first solder column is formed in the first through-holes of the plurality of first through-hole arrays, and a second solder column is formed in the second through-holes of the second through-hole arrays;

[0019] removing the electroplating seed layer outside the first solder column and the second solder column, and the barrier layer;

[0020] The first solder column and the second solder column are subjected to a reflow process to obtain a target wafer-level chip having a plurality of solder point arrays and alignment point arrays on the surface.

[0021] Optionally, after reflowing the first solder pillar and the second solder pillar to obtain a target wafer-level chip having a plurality of solder joint arrays and alignment point arrays on the surface, the method further includes:

[0022] A protective film is covered on the first surface of the target wafer-level chip to obtain a wafer to be ground; the protective film is capable of filling the array gaps within the solder joint array and the alignment point array, as well as the gap between the solder joint array and the alignment point array; the thickness of the protective film is greater than the height of the solder joint array and the alignment point array;

[0023] A second surface opposite to the first surface is ground to obtain a ground wafer.

[0024] Optionally, after grinding the second surface opposite to the first surface to obtain a ground wafer, the method further includes:

[0025] The ground wafer is sliced ​​to obtain target chips.

[0026] Optionally, the thickness of the dielectric layer ranges from 3 to 10 microns.

[0027] Optionally, the material of the dielectric layer includes a low-temperature curing polymer material or a high-temperature curing polymer material.

[0028] The present application also discloses a chip, which is manufactured based on any of the above chip manufacturing methods.

[0029] By adopting the above technical solution, the chip preparation method provided in this application has the following beneficial effects:

[0030] The chip preparation method provided in the present application is to obtain a processed wafer by first electroplating the initial wafer; the initial wafer includes an initial chip and an alignment chip; and a barrier layer is coated on the processed wafer, and the barrier layer is patterned to form solder joints or through holes of alignment points that need to be subsequently formed by electroplating; since the area on the alignment chip that plays a role in package alignment is the alignment point, and the cross-sectional area of ​​the alignment point is similar to the cross-sectional area of ​​the solder point, the height difference between the two structures after electroplating reflow is small, which improves the uniformity of the plane where the two structures are located, and is conducive to improving the uniformity of subsequent wafer grinding. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0032] Figure 1 A flow chart of an optional chip preparation method for this application;

[0033] Figure 2 This is a schematic cross-sectional view of an optional initial wafer for this application;

[0034] Figure 3 This is a schematic diagram of the structure of an optional processed wafer in this application;

[0035] Figure 4 This is a schematic structural diagram of an optional initial wafer with a dielectric layer in this application;

[0036] Figure 5 A top view of a processed wafer after an optional patterned barrier layer is shown in the present application;

[0037] Figure 6 This is a cross-sectional view of an optional wafer after electroplating in this application;

[0038] Figure 7 A cross-sectional view of an optional target wafer-level chip for this application;

[0039] Figure 8 This is a schematic diagram of the structure of an optional wafer after grinding in this application;

[0040] Figure 9 This is a schematic structural diagram of an optional wafer after grinding with the protective film removed according to the present application;

[0041] Figure 10 This is an optional top view of an alignment chip in the prior art.

[0042] The following is a supplementary description of the accompanying drawings:

[0043] 1-electrode; 2-passivation layer; 3-dielectric layer; 4-electroplating seed layer; 5-groove; 6-third through hole; 7-barrier layer; 8-initial chip; 801-first through hole array; 9-alignment chip; 901-second through hole array; 10-first through hole; 11-second through hole; 12-first metal layer; 13-second metal layer. DETAILED DESCRIPTION

[0044] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work are within the scope of protection of this application.

[0045] References to "one embodiment" or "embodiment" herein refer to specific features, structures, or characteristics that may be included in at least one implementation of the present application. Throughout the description of this application, it should be understood that the terms "upper," "lower," "top," and "bottom," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely for ease of description and simplification. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Thus, a feature designated "first" or "second" may explicitly or implicitly include one or more of such features. Furthermore, the terms "first," "second," etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential sequence. It should be understood that such terms are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0046] For the purpose of the following detailed description, it should be understood that the present invention may adopt various alternative variations and step sequences, unless expressly provided otherwise. In addition, except in any operating examples, or when otherwise indicated, all numerals representing the amount of the components used in the specification and claims should be understood to be modified by the term "about" in all cases. Therefore, unless otherwise indicated, the numerical parameters set forth in the following specification and the appended claims are approximate values ​​that vary according to the desired performance to be obtained by the present invention. At least, it is not intended to limit the application of the doctrine of equivalents to the scope of the claims, and each numerical parameter should at least be interpreted according to the number of reported significant figures and by applying ordinary rounding techniques.

[0047] Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values ​​set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements.

[0048] When a numerical range is disclosed herein, the above range is considered to be continuous and includes the minimum and maximum values ​​of the range, as well as every value between such minimum and maximum values. Further, when a range refers to an integer, every integer between the minimum and maximum values ​​of the range is included. In addition, when multiple ranges are provided to describe a feature or characteristic, the ranges can be merged. In other words, unless otherwise indicated, all ranges disclosed herein should be understood to include any and all subranges included therein. For example, a specified range from "1 to 10" should be considered to include any and all subranges between a minimum of 1 and a maximum of 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0049] The chip manufacturing process requires high precision, especially during the packaging process, which necessitates precise positioning of each die to be packaged. However, wafer-level packaging, due to the full-surface packaging of wafer-level chips, can also produce defective products. Inspection marks are placed on the atlas to distinguish good from defective products. Maps for electrical performance or appearance are generated, and these process maps need to be superimposed and ultimately aligned one-to-one with the chips on the wafer. To quickly and accurately overlay these maps, and in the WL-CSP packaging field, alignment mark chips are required during the lithography process. These mark patterns are precisely aligned with the wafer surface pattern, allowing the mask pattern to be copied onto the wafer and minimizing deviations. The alignment mark chips serve as reference points for the entire wafer and are crucial for the use of the atlas generated during the packaging process. The clear distinction between the alignment mark chip and the appearance of the valid chip allows for rapid alignment of the atlas markers with the wafer markers, facilitating proper use of the atlas and improving packaging efficiency. Therefore, in wafer-level chips, the presence of an alignment chip as the wafer reference point is essential.

[0050] In the existing technology, the alignment chip and the effective chip run through the entire process of chip manufacturing. In particular, in the electroplating process, the solder joints of the effective chip and the alignment patterns of the alignment chip are prepared at the same time. In fact, since the solder joint area of ​​the effective chip is smaller than the area of ​​the alignment pattern, the electroplating process easily results in a small amount of tin applied to the small solder joint area, and thus the height of the final solder joint is smaller than the height of the alignment pattern. Due to the poor uniformity of the solder joint and the alignment pattern plane, stress concentration is easily generated during the grinding process of the wafer-level chip, resulting in poor grinding uniformity or even cracking.

[0051] For this purpose, see Figure 1 , Figure 1 This is a flow chart of an optional chip preparation process for this application. This application provides a chip preparation method comprising the following steps:

[0052] S101: providing an initial wafer; the initial wafer comprises a plurality of initial chips 8 and an alignment chip 9; each of the plurality of initial chips 8 is provided with an electrode array.

[0053] See Figure 2 , Figure 2 This is a schematic cross-sectional view of an optional initial wafer of the present application. A passivation layer 2 is also provided on the surface of the initial wafer; the passivation layer 2 is provided with openings for exposing the electrodes 1 of the electrode array, and the passivation layer 2 is used to protect the chip circuit.

[0054] Optionally, the passivation layer 2 may be Figure 2 The structure shown has a local passivation, but it can also be a full-surface passivation, that is, a passivation layer 2 is provided on the entire surface of the wafer.

[0055] It should be noted that the initial wafer can be ready-made or can be formed and processed using a general chip processing technology as needed.

[0056] S102: Perform electroplating pretreatment on the first surface of the initial wafer to obtain a processed wafer, such as Figure 3 The structure shown; the electrode array is provided on the first surface.

[0057] In a feasible embodiment, step S102 can be specifically described as: preparing a dielectric layer 3 on the first surface of the initial wafer; the dielectric layer 3 includes a plurality of third through-hole arrays, each of the plurality of third through-hole arrays is used to expose a corresponding electrode array; preparing an electroplating seed layer 4 on the dielectric layer 3; the electroplating seed layer 4 includes a plurality of groove arrays, each of the plurality of groove arrays corresponds to an electrode array.

[0058] It should be noted that one groove array corresponds to one electrode array, each groove array includes a plurality of grooves 5, and each groove 5 corresponds to one electrode 1; Figure 3 It can be seen that a groove 5 is provided on one electrode 1 of the electrode array.

[0059] See Figure 4 , Figure 4 This is a schematic diagram of the structure of an optional initial wafer with a dielectric layer for this application. Each initial chip 8 is provided with an electrode array. The openings in the passivation layer 2 and the third through-holes 6 in the dielectric layer 3 are intended to expose a corresponding electrode 1, allowing subsequent electroplating of the electrode 1 and connection of the plated solder joints to external circuitry.

[0060] The dielectric layer 3 can serve as a buffer protection layer for the wafer. Its protective and stress buffering functions greatly improve the reliability of the product structure, protect the chip surface from stress damage, and make the chip surface flatter, which is conducive to improving the uniformity and bonding strength of subsequent electroplating processes.

[0061] In a feasible embodiment, the thickness of the dielectric layer 3 ranges from 3 to 10 microns.

[0062] In a feasible embodiment, the material of the dielectric layer 3 includes a low-temperature curing polymer material or a high-temperature curing polymer material.

[0063] Optionally, the electroplating seed layer 4 can be prepared by sputtering, and the entire surface of the first surface can be sputtered; the material of the electroplating seed layer 4 includes but is not limited to Ti / Cu, that is, it can also be other conductive metals.

[0064] S103: Coating a barrier layer 7 on the first surface of the processed wafer and patterning the barrier layer 7; the patterned barrier layer 7 includes a plurality of first through-hole arrays 801 and a second through-hole array 901; the plurality of first through-hole arrays 801 correspond to a plurality of the electrode arrays; the second through-hole array 901 is located on the alignment chip 9; and the difference between the cross-sectional area of ​​the second through-hole 11 of the second through-hole array 901 and the cross-sectional area of ​​the first through-hole 10 of the first through-hole array 801 is less than or equal to a first threshold value.

[0065] In a feasible embodiment, the height of the second through hole 11 of the second through hole array 901 is equal to the height of the first through hole 10 of the first through hole array 801; and the difference between the array spacing of the second through hole array 901 and the array spacing of the first through hole array 801 is less than or equal to the second threshold.

[0066] See Figure 5 , Figure 5 This is a top view of a processed wafer after an optional patterned barrier layer is formed in this application. The second through hole array 901 is used to form an alignment point array after subsequent electroplating; the alignment point array can be arranged as needed. Figure 5 The cross shape shown can also be other shapes, such as an L-shape or a square, as long as it can be clearly distinguished from the rectangle formed by the first through-hole array 801.

[0067] Optionally, the first threshold value ranges from 0 to 5 square microns. Since the difference between the cross-sectional area of ​​the second through hole 11 and the cross-sectional area of ​​the first through hole 10 is small, the amount of tin applied during the subsequent electroplating process is relatively close or equal, so that the height difference between the solder joint on the initial chip 8 and the height difference between the alignment point on the alignment chip 9 is small, thereby improving the grinding uniformity and preventing chipping.

[0068] Optionally, a specific method for patterning the blocking layer 7 includes: placing a mask on the blocking layer 7 with a preset distance between the mask and the blocking layer 7, and performing an exposure process; and developing the exposed wafer to achieve patterning the blocking layer 7.

[0069] Optionally, the position of the alignment chip 9 on the wafer and the number of alignment chips 9 can be designed as needed. For example, when the number of alignment chips 9 is three, one can be set on each opposite side of the wafer, and one can be set between the two alignment chips 9.

[0070] During the process of aligning and exposing the mask, the alignment chip 9 can be used as an alignment reference point to enable the mask and the wafer to be accurately aligned, thereby reducing the offset between the mask and the wafer.

[0071] S104 : preparing solder joints in the first through holes 10 of the plurality of first through hole arrays 801 and preparing alignment points in the second through holes 11 of the second through hole array 901 by using an electroplating process.

[0072] Optional, see Figure 6 , Figure 6 This is a cross-sectional view of an optional electroplated wafer in this application. The solder joints and alignment points obtained after electroplating have the same structure, namely, both comprise a stacked first metal layer 12 and a second metal layer 13. The first metal layer 12 is made of materials including, but not limited to, copper, gold, and silver. The second metal layer 13 is made of tin, facilitating flip-chip soldering to external circuits.

[0073] S105: removing the barrier layer 7 to obtain a target wafer-level chip having a plurality of solder joint arrays and alignment point arrays on its surface.

[0074] In a feasible embodiment, steps S104-S105 can be specifically described as follows: using an electroplating process to prepare a first solder column in the first through hole 10 of the plurality of first through hole arrays 801, and preparing a second solder column in the second through hole 11 of the second through hole array 901; removing the electroplating seed layer 4 and the barrier layer 7 on the outside of the first solder column and the second solder column; reflowing the first solder column and the second solder column to obtain a target wafer-level chip having a plurality of solder point arrays and an alignment point array on the surface, that is, Figure 7 The structure shown.

[0075] Optionally, the first solder column includes a stacked first metal layer 12 and a second metal layer 13 ; the second solder column includes a stacked first metal layer 12 and a second metal layer 13 .

[0076] Since metallic tin has a low melting point, it becomes spherical after reflow. The higher the amount of tin, the higher the height after reflow. Since the cross-sectional area of ​​each alignment point in the present application is similar to the cross-sectional area of ​​the solder joint, the amount of electroplated tin is also similar. After reflow treatment, the height of the second metal layer 13 in the first solder column and the second metal layer 13 in the second solder column are also similar.

[0077] In addition to serving as an alignment reference in the photolithography process, the alignment chip 9 can also be used as a positioning reference during the packaging process by identifying the position of the alignment point array, and then determining the position of the chip to be packaged that has a corresponding positional relationship with the alignment point array based on the position of the alignment point array. Therefore, in the actual packaging process, there may be defective products. In the actual packaging process, only the chips that have passed the previous process can be packaged and used as the chips to be packaged. By determining the position of the alignment point array, the position of the alignment chip 9 can be determined, and then the position of the chip to be packaged can be determined. Of course, as mentioned earlier, since the corresponding map will be formed after the chip is packaged, the alignment chip 9 also facilitates the rapid alignment and stacking of multiple maps, and the defective products can be quickly eliminated after subsequent slicing.

[0078] In a possible embodiment, see Figure 8-9 , Figure 8 This is a schematic diagram of the structure of an optional wafer after grinding in this application; Figure 9 This is a schematic diagram of the structure of a polished wafer with the protective film removed, which is optional in this application. After the reflow process, the preparation method further includes: covering the first surface of the target wafer-level chip with a protective film to obtain a polished wafer; the protective film is capable of filling the array gaps within the solder joint array and the alignment point array, as well as the gaps between the solder joint array and the alignment point array; the thickness of the protective film is greater than the height of the solder joint array and the alignment point array; and polishing the second surface opposite the first surface to obtain a polished wafer.

[0079] Optionally, the protective film can be a BG film, which is used to protect the first surface of the wafer. The height of the protective film is mainly based on the height of the solder joints and the alignment points. The protective film needs to completely cover the solder joints and the alignment points, but the height cannot be too high, which will make the protective film softer and unable to provide sufficient supporting force. It will collapse during grinding and affect the uniformity of the silicon layer.

[0080] Optionally, the above-mentioned process of covering with a protective film and grinding specifically includes: first applying a protective film, measuring the thickness of the protective film, grinding the wafer, and determining the thickness of the wafer after grinding. If the thickness of the wafer after grinding meets the preset conditions (that is, the thickness of the wafer after grinding meets the preset thickness), then peeling off the protective film to obtain the ground wafer.

[0081] In a feasible embodiment, after preparing the ground wafer, the preparation method further includes: slicing the ground wafer to obtain target chips.

[0082] This application is to use the existing technology Figure 10 The large area alignment pattern shown ( Figure 10 The cross alignment pattern in the figure is made into a dot matrix pattern, and the cross-sectional area of ​​the solder joint on the initial chip 8 (i.e., the effective chip) is made close to the cross-sectional area of ​​the alignment point, so that the height difference between the two formed by electroplating reflow is small, thereby improving the grinding uniformity.

[0083] The present application also discloses a chip, which is manufactured based on any of the above chip manufacturing methods.

[0084] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for preparing a chip, characterized in that: include: Providing an initial wafer; The initial wafer comprises a plurality of initial chips (8) and an alignment chip (9); each of the plurality of initial chips (8) is provided with an electrode array; performing electroplating pretreatment on the first surface of the initial wafer to obtain a processed wafer; The electrode array is provided on the first surface; A barrier layer (7) is coated on the first surface of the processed wafer, and the barrier layer (7) is patterned; the patterned barrier layer (7) includes a plurality of first through-hole arrays (801) and a second through-hole array (901); the plurality of first through-hole arrays (801) correspond to the plurality of electrode arrays; the second through-hole array (901) is located on the alignment chip (9); and the difference between the cross-sectional area of ​​the second through-hole (11) of the second through-hole array (901) and the cross-sectional area of ​​the first through-hole (10) of the first through-hole array (801) is less than or equal to a first threshold value; the range of the first threshold value includes 0 to 5 square micrometers; Using an electroplating process, solder joints are prepared in the first through holes (10) of the plurality of first through hole arrays (801), and alignment points are prepared in the second through holes (11) of the second through hole array (901); The barrier layer (7) is removed to obtain a target wafer-level chip having a plurality of solder point arrays and alignment point arrays on its surface.

2. The preparation method according to claim 1, characterized in that The height of the second through-holes (11) of the second through-hole array (901) is equal to the height of the first through-holes (10) of the first through-hole array (801); The difference between the array spacing of the second through hole array (901) and the array spacing of the first through hole array (801) is less than or equal to a second threshold.

3. The preparation method according to claim 1, characterized in that During the packaging process, the packaging equipment can identify the position of the alignment point array and then determine the position of the chip to be packaged that has a corresponding positional relationship with the alignment point array based on the position of the alignment point array.

4. The preparation method according to claim 1, characterized in that The step of performing electroplating pretreatment on the first surface of the initial wafer to obtain a processed wafer comprises: A dielectric layer (3) is prepared on the first surface of the initial wafer; the dielectric layer (3) comprises a plurality of third through-hole arrays, each of the plurality of third through-hole arrays being used to expose a corresponding electrode array; An electroplating seed layer (4) is prepared on the dielectric layer (3); the electroplating seed layer (4) comprises a plurality of groove arrays, and each groove array in the plurality of groove arrays corresponds to an electrode array.

5. The preparation method according to claim 4, characterized in that The electroplating process is used to prepare solder joints in the first through holes (10) of the plurality of first through hole arrays (801), and to prepare alignment points in the second through holes (11) of the second through hole array (901); The barrier layer (7) is removed to obtain a target wafer-level chip having a plurality of solder joint arrays and alignment point arrays on the surface, comprising: Using an electroplating process, a first solder column is prepared in the first through hole (10) of the plurality of first through hole arrays (801), and a second solder column is prepared in the second through hole (11) of the second through hole array (901); removing the electroplating seed layer (4) and the barrier layer (7) outside the first solder column and the second solder column; The first solder pillars and the second solder pillars are subjected to a reflow process to obtain a target wafer-level chip having a plurality of solder joint arrays and alignment point arrays on the surface.

6. The preparation method according to claim 5, characterized in that After the first solder pillars and the second solder pillars are subjected to a reflow process to obtain a target wafer-level chip having a plurality of solder joint arrays and an alignment point array on the surface, the method further includes: A protective film is covered on the first surface of the target wafer-level chip to obtain a wafer to be ground; the protective film is capable of filling the array gaps within the solder joint array and the alignment point array, as well as the gap between the solder joint array and the alignment point array; the thickness of the protective film is greater than the height of the solder joint array and the alignment point array; A second surface opposite to the first surface is ground to obtain a ground wafer.

7. The preparation method according to claim 6, characterized in that After grinding the second surface opposite to the first surface to obtain a ground wafer, the method further includes: The ground wafer is sliced ​​to obtain target chips.

8. The preparation method according to claim 4, characterized in that The thickness of the dielectric layer (3) ranges from 3 to 10 microns.

9. The preparation method according to claim 4, characterized in that The material of the dielectric layer (3) includes a low-temperature curing polymer material or a high-temperature curing polymer material.

10. A chip, characterized in that: The chip is made based on the chip preparation method according to any one of claims 1 to 9.

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