Method for forming a self-aligned isolation structure and image sensor

Abstract

The present application provides a method for forming a self-aligned isolation structure and an image sensor. The image sensor comprises: a semiconductor substrate; a plurality of first isolation structures located within the semiconductor substrate, wherein two adjacent first isolation structures define the position of a self-aligned isolation structure as described above; and a self-aligned isolation structure located within the semiconductor substrate between the two adjacent first isolation structures, wherein the depth of the self-aligned isolation structure is greater than the depth of the first isolation structure. The method for forming a self-aligned isolation structure and the image sensor described herein use the first isolation structures as hard masks to etch second trenches to form the self-aligned isolation structures, thereby improving the alignment accuracy of deep trench isolation structures between adjacent pixel units in the image sensor.

Description

Technical Field

[0001] The present application relates to the technical field of image sensors, and in particular to a method for forming a self-aligned isolation structure and an image sensor. Background Art

[0002] In the field of image sensors, electrical and optical isolation between adjacent pixel units is achieved through deep trench isolation (DTI), which is divided into front-end deep trench isolation (F-DTI) and back-end deep trench isolation (B-DTI).

[0003] Due to its advantages such as improving etching sidewalls through high-temperature processes, the front-end deep trench process has gradually become the preferred solution for high-performance image sensors.

[0004] DTI etching often requires a hard mask layer of a certain thickness. Especially when the DTI etching depth exceeds 8μm, the thickness of the hard mask layer determines that DTI lithography can only use a photoresist thicker than 1μm. This poses a challenge to the resolution and overlay accuracy of the DTI pattern.

[0005] Therefore, it is necessary to provide a more reliable and effective technical solution to improve the resolution and alignment accuracy of the front-end deep trench process. Summary of the Invention

[0006] The present application provides a method for forming a self-aligned isolation structure and an image sensor, which can improve the alignment accuracy of a deep trench isolation structure between adjacent pixel units of the image sensor.

[0007] One aspect of the present application provides a method for forming a self-aligned isolation structure for isolating different pixel areas of an image sensor, comprising: providing a semiconductor substrate, forming a plurality of first isolation structures in the semiconductor substrate, wherein two adjacent first isolation structures define the position of the self-aligned isolation structure; etching the semiconductor substrate between the two adjacent first isolation structures to a specific depth to form a second trench; and forming the self-aligned isolation structure in the second trench, wherein the depth of the self-aligned isolation structure is greater than the depth of the first isolation structure.

[0008] In some embodiments of the present application, the first isolation structure is formed simultaneously with a shallow trench isolation structure in an active region of a semiconductor substrate.

[0009] In some embodiments of the present application, the self-aligned isolation structure is a deep trench isolation structure, and a depth ratio of the self-aligned isolation structure to the first isolation structure is (2-30):1.

[0010] In some embodiments of the present application, the depth of the first isolation structure is 90 nanometers to 400 nanometers, and the depth of the self-aligned isolation structure is 1 micrometer to 30 micrometers.

[0011] In some embodiments of the present application, the method for forming the self-aligned isolation structure further includes: after forming the plurality of first isolation structures and before forming the second trenches, performing ion implantation in the semiconductor substrate to form a well region.

[0012] In some embodiments of the present application, the method for forming the second trench includes: forming a second photoresist layer on the surface of the semiconductor substrate, the second photoresist layer including a first opening, the first opening exposing the semiconductor substrate between the two adjacent first isolation structures and a portion of the two adjacent first isolation structures; etching the semiconductor substrate and the first isolation structure along the first opening to form a second trench; and removing the second photoresist layer.

[0013] In some embodiments of the present application, the area of ​​the portion of the first isolation structure exposed by the first opening accounts for one third to two thirds of the area of ​​the first isolation structure.

[0014] In some embodiments of the present application, a width of the self-aligned isolation structure is 0.2 micrometers to 1 micrometer.

[0015] Another aspect of the present application provides an image sensor, comprising: a semiconductor substrate; a plurality of first isolation structures located in the semiconductor substrate, wherein two adjacent first isolation structures define the position of the self-aligned isolation structure described above; the self-aligned isolation structure described above, located in the semiconductor substrate between the two adjacent first isolation structures, the depth of the self-aligned isolation structure being greater than the depth of the first isolation structure.

[0016] In some embodiments of the present application, the first isolation structure is a shallow trench isolation structure, the self-aligned isolation structure is a deep trench isolation structure, and the depth ratio of the self-aligned isolation structure to the first isolation structure is (2-30):1.

[0017] In some embodiments of the present application, the depth of the first isolation structure is 90 nanometers to 400 nanometers, and the depth of the self-aligned isolation structure is 1 micrometer to 30 micrometers.

[0018] In some embodiments of the present application, the image sensor further includes a well region located in the semiconductor substrate between adjacent self-aligned isolation structures.

[0019] In some embodiments of the present application, a width of the self-aligned isolation structure is 0.2 micrometers to 1 micrometer.

[0020] The method for forming a self-aligned isolation structure and the image sensor described in the present application use the first isolation structure as a hard mask to etch the second trench to form a self-aligned isolation structure, which can improve the alignment accuracy of the deep trench isolation structure between adjacent pixel units of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The following figures describe in detail exemplary embodiments disclosed in this application. Identical reference numerals denote similar structures in several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the same inventive intent as described in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0022] Figures 1 to 5 Schematic diagram of the structure of each step in a method for forming an image sensor;

[0023] Figures 6 to 13 Schematic diagram of the structure of each step in the method for forming a self-aligned isolation structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0025] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.

[0026] Figures 1 to 5 The figure is a structural schematic diagram of each step in a method for forming an image sensor.

[0027] refer to Figure 1 , providing a semiconductor substrate 100.

[0028] refer to Figure 2 A patterned hard mask layer 110 is formed on the surface of the semiconductor substrate 100. The patterned hard mask layer 110 defines the location of the deep trench isolation structure. The patterned hard mask layer 110 can be formed by, for example: forming a hard mask layer on the surface of the semiconductor substrate 100; forming a patterned photoresist layer on the surface of the hard mask layer; and etching the hard mask layer using the patterned photoresist layer as a mask to form the patterned hard mask layer 110.

[0029] refer to Figure 3 , the semiconductor substrate 100 is etched using the patterned hard mask layer 110 as a mask to form a deep trench 120. Figure 4 , Figure 4 is a plan view of the semiconductor substrate 100 , in which the deep trenches 120 are distributed in an array.

[0030] refer to Figure 5 , removing the patterned hard mask layer 110 , and filling the deep trench 120 with an isolation material to form a deep trench isolation structure 130 .

[0031] refer to Figure 4 For the sake of brevity, Figure 4 The deep trench 120 shown in FIG is a regular rectangular pattern. However, in the actual process, since the DTI etching process is a distributed etching process, the etching depth increases with the increase of the pattern size. Figure 4 The etching depth at the intersection of the deep trenches 120 in the image sensor will increase significantly, affecting the performance of the image sensor. Currently, only OPC (optical proximity effect) can be used to make some corrections, but OPC correction of thick photoresist layers is extremely challenging. Due to the deep depth of the deep trenches 120, the thickness of the patterned hard mask layer required is thicker, and the thickness of the photoresist layer used to etch the hard mask layer is also thicker, which places high demands on OPC correction. In addition, when forming the patterned hard mask layer, the requirements for overlay accuracy are also very high, which can only continuously place higher demands on the photolithography machine.

[0032] In response to the above problems, the present application provides a method for forming a self-aligned isolation structure and an image sensor, which uses the first isolation structure as a hard mask to etch the second trench to form a self-aligned isolation structure, thereby improving the alignment accuracy of the deep trench isolation structure between adjacent pixel units of the image sensor.

[0033] An embodiment of the present application provides a method for forming a self-aligned isolation structure for isolating different pixel areas of an image sensor, comprising: providing a semiconductor substrate, forming a plurality of first isolation structures in the semiconductor substrate, wherein two adjacent first isolation structures define the position of the self-aligned isolation structure; etching the semiconductor substrate between the two adjacent first isolation structures to a specific depth to form a second trench; and forming the self-aligned isolation structure in the second trench, wherein the depth of the self-aligned isolation structure is greater than the depth of the first isolation structure.

[0034] Figures 6 to 13The following is a structural diagram of each step in the method for forming a self-aligned isolation structure according to an embodiment of the present application. The method for forming a self-aligned isolation structure and the image sensor according to an embodiment of the present application are described in detail with reference to the accompanying drawings.

[0035] refer to Figure 6 As shown, a semiconductor substrate 200 is provided, and a plurality of first isolation structures 210 are formed in the semiconductor substrate 200 , wherein two adjacent first isolation structures 210 define the position of the self-aligned isolation structure.

[0036] In some embodiments of the present application, the first isolation structure 210 is formed simultaneously with a shallow trench isolation structure in the active region of the semiconductor substrate 200. The steps for forming the first isolation structure 210 can be synchronized with the steps for forming a conventional shallow trench isolation structure. The method for forming the self-aligned isolation structure described in the embodiments of the present application is compatible with conventional image sensor deep trench isolation processes, without introducing new steps or complicating the process.

[0037] In some embodiments of the present application, the material of the semiconductor substrate 200 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination thereof. In addition, the semiconductor substrate 200 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 200 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0038] In some embodiments of the present application, the semiconductor substrate 200 is divided into different pixel regions, such as a red pixel region, a green pixel region, and a blue pixel region, as needed. The self-aligned isolation structure is used to isolate adjacent pixel regions.

[0039] In some embodiments of the present application, the method of forming the first isolation structure 210 may include: forming a patterned photoresist on the surface of the semiconductor substrate, the patterned photoresist defining the position of the first isolation structure 210; etching the semiconductor using the patterned photoresist as a mask to form a shallow trench; and forming the first isolation structure 210 in the shallow trench.

[0040] In some embodiments of the present application, when forming the first isolation structure 210, OPC (optical proximity effect) can be used to modify the patterned photoresist. Because the patterned photoresist is relatively thin, OPC modification is also relatively easy. This modification improves the pattern of the semiconductor substrate at the intersections between adjacent first isolation structures 210. This improves the pattern of the second trenches subsequently formed in the semiconductor substrate between adjacent first isolation structures 210, thereby resolving the issue of significantly increased etching depth at the intersections of the second trenches.

[0041] In some embodiments of the present application, the material of the first isolation structure 210 is an insulating material commonly used in semiconductor processes, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0042] In some embodiments of the present application, the depth of the first isolation structure 210 is 90 nm to 400 nm, for example, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, or 350 nm.

[0043] In some embodiments of the present application, the width of the first isolation structure 210 is 0.1 micrometer to 0.2 micrometer. The width may be the width of the top surface of the first isolation structure 210 or the average width of the first isolation structure 210.

[0044] It should be noted that although Figure 6 The first isolation structure 210 shown in FIG is a regular rectangle, but those skilled in the art will appreciate that in actual processes, due to limitations of the etching process, the first isolation structure 210 may not be a regular shape, but rather an inverted trapezoid. The same is true for the self-aligned isolation structure formed in subsequent processes.

[0045] refer to Figures 7 to 9 In some embodiments of the present application, the method for forming the self-aligned isolation structure further includes: after forming a plurality of first isolation structures 210 and before forming the second trench, performing ion implantation in the semiconductor substrate to form a well region 220 .

[0046] refer to Figure 7 As shown, a first photoresist layer 221 is formed on the surface of the semiconductor substrate 200 . The first photoresist layer 221 includes a second opening 222 . The second opening 222 exposes the semiconductor substrate for forming a well region and two first isolation structures 210 on both sides of the well region.

[0047] refer to Figure 8 As shown, an ion implantation process is performed on the exposed semiconductor substrate along the second opening 222 to form a well region 220. As required, the well region 220 can be of N-type or P-type.

[0048] In some embodiments of the present application, the exposed semiconductor substrate may be subjected to multiple ion implantations at different concentrations and depths to form heavily doped regions, lightly doped regions, etc. distributed in layers.

[0049] refer to Figure 9 As shown, the second photoresist layer 221 is removed.

[0050] refer to Figures 10 to 13 The semiconductor substrate 200 between the two adjacent first isolation structures 210 is etched to a specific depth to form a second trench 230. The specific depth can be set according to the actual required depth of the self-aligned isolation structure.

[0051] refer to Figure 10 As shown, a second photoresist layer 231 is formed on the surface of the semiconductor substrate 200. The second photoresist layer 231 includes a first opening 232. The first opening 232 exposes the semiconductor substrate 200 between the two adjacent first isolation structures 210 and a portion of the two adjacent first isolation structures 210. Because the first isolation structures 210 can also serve as an etching block, the precision requirements for the second photoresist layer 231 do not need to be too high. In other words, the first opening 232 does not need to completely expose the semiconductor substrate for forming the second trench, but can also partially expose the first isolation structure 210. As a result, the positional accuracy of the formed second trench can be higher.

[0052] In some embodiments of the present application, the area of ​​the portion of the first isolation structure 210 exposed by the first opening 232 accounts for one-third to two-thirds, for example, one-half, of the area of ​​the first isolation structure 210. To improve etching accuracy, the boundary of the first opening 232 can be located as close as possible to the center of the first isolation structure 210.

[0053] refer to Figure 11 As shown, the semiconductor substrate and the first isolation structure are etched along the first opening 232 to form a second trench 230. The etching may include wet etching or dry etching.

[0054] refer to Figure 12 As shown, the second photoresist layer 231 is removed.

[0055] refer to Figure 13 As shown, the self-aligned isolation structure 240 is formed in the second trench 230 , and the depth of the self-aligned isolation structure 240 is greater than the depth of the first isolation structure 210 .

[0056] In some embodiments of the present application, a method for forming the self-aligned isolation structure 240 may include a chemical vapor deposition process or a physical vapor deposition process and a chemical mechanical polishing process.

[0057] In some embodiments of the present application, the material of the self-aligned isolation structure 240 is an insulating material commonly used in semiconductor processes, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0058] In some embodiments of the present application, the self-aligned isolation structure 240 is a deep trench isolation structure, and the depth ratio of the self-aligned isolation structure 240 to the first isolation structure 210 is (2-30) : 1. In order to better isolate adjacent pixel regions, the depth of the self-aligned isolation structure 240 needs to be sufficiently deep.

[0059] In some embodiments of the present application, the depth of the first isolation structure 210 is 90 nanometers to 400 nanometers, and the depth of the self-aligned isolation structure 240 is 1 micrometer to 30 micrometers, for example, 2 micrometers, 5 micrometers, 10 micrometers, or 20 micrometers.

[0060] In some embodiments of the present application, the width of the self-aligned isolation structure 240 is 0.2 micrometers to 1 micrometer, for example, 0.5 micrometers or 0.8 micrometers, etc. The width can be the width of the top surface of the self-aligned isolation structure 240 or the average width of the self-aligned isolation structure 240 .

[0061] In the method for forming a self-aligned isolation structure described in an embodiment of the present application, first, the self-aligned isolation structure 240 is formed using the first isolation structure 210 as an alignment tool, rather than simply using a photolithography process, so the requirements for the photolithography process can be reduced, and the position accuracy of the self-aligned isolation structure 240 can be improved; secondly, the well region 220 is also formed using the first isolation structure 210 as an alignment tool, so the alignment accuracy between the well region 220 and the pixel area defined by the self-aligned isolation structure 240 is also improved; in addition, when forming the first isolation structure 210, OPC (optical proximity effect) can be used to make some corrections, thereby reducing the difficulty of pattern optimization at the intersection position of the second groove 230.

[0062] The embodiment of the present application also provides an image sensor, referring to Figure 13 As shown, it includes: a semiconductor substrate; a plurality of first isolation structures located in the semiconductor substrate, wherein two adjacent first isolation structures define the position of the self-aligned isolation structure as described above; the self-aligned isolation structure as described above is located in the semiconductor substrate between the two adjacent first isolation structures, and the depth of the self-aligned isolation structure is greater than the depth of the first isolation structure.

[0063] refer to Figure 13 As shown, in some embodiments of the present application, the material of the semiconductor substrate 200 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination of the above. In addition, the semiconductor substrate 200 can be doped (for example, a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 200 can be doped with a P-type dopant (for example, boron, indium, aluminum, or gallium) or an N-type dopant (for example, phosphorus or arsenic).

[0064] In some embodiments of the present application, the semiconductor substrate 200 is divided into different pixel regions, such as a red pixel region, a green pixel region, and a blue pixel region, as needed. The self-aligned isolation structure 240 is used to isolate adjacent pixel regions.

[0065] In some embodiments of the present application, the material of the first isolation structure 210 is an insulating material commonly used in semiconductor processes, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0066] In some embodiments of the present application, the first isolation structure 210 is a shallow trench isolation structure, and the depth of the first isolation structure 210 is 90 nanometers to 400 nanometers, for example, 100 nanometers, 150 nanometers, 200 nanometers, 250 nanometers, 300 nanometers or 350 nanometers.

[0067] In some embodiments of the present application, the width of the first isolation structure 210 is 0.1 micrometer to 0.2 micrometer. The width may be the width of the top surface of the first isolation structure 210 or the average width of the first isolation structure 210.

[0068] It should be noted that although Figure 13 The first isolation structure 210 shown in FIG is a regular rectangle, but those skilled in the art will appreciate that in actual processes, due to limitations of the etching process, the first isolation structure 210 may not be a regular shape, but rather an inverted trapezoid. The same is true for the self-aligned isolation structure formed in subsequent processes.

[0069] Continue to refer Figure 13 As shown, in some embodiments of the present application, the image sensor further includes a well region 220 located in the semiconductor substrate between adjacent self-aligned isolation structures 240. As needed, the well region 220 can be N-type or P-type.

[0070] In some embodiments of the present application, the well region 220 may include heavily doped regions, lightly doped regions, etc. with different doping concentrations and depths distributed in layers.

[0071] Continue to refer Figure 13 As shown, the depth of the self-aligned isolation structure 240 is greater than the depth of the first isolation structure 210 .

[0072] In some embodiments of the present application, the self-aligned isolation structure 240 is a deep trench isolation structure, and the depth ratio of the self-aligned isolation structure 240 to the first isolation structure 210 is (2-30) : 1. In order to better isolate adjacent pixel regions, the depth of the self-aligned isolation structure 240 needs to be sufficiently deep.

[0073] In some embodiments of the present application, the depth of the first isolation structure 210 is 90 nanometers to 400 nanometers, and the depth of the self-aligned isolation structure 240 is 1 micrometer to 30 micrometers, for example, 2 micrometers, 5 micrometers, 10 micrometers, or 20 micrometers.

[0074] In some embodiments of the present application, the width of the self-aligned isolation structure 240 is 0.2 micrometers to 1 micrometer, for example, 0.5 micrometers or 0.8 micrometers, etc. The width can be the width of the top surface of the self-aligned isolation structure 240 or the average width of the self-aligned isolation structure 240 .

[0075] In the self-aligned isolation structure described in the embodiment of the present application, on the one hand, the self-aligned isolation structure 240 is formed using the first isolation structure 210 as an alignment tool, and the positional accuracy of the self-aligned isolation structure 240 can be improved; on the other hand, since the positional accuracy of the self-aligned isolation structure 240 is improved, the alignment accuracy between the well region 220 and the pixel region defined by the self-aligned isolation structure 240 is also improved.

[0076] The method for forming a self-aligned isolation structure and the image sensor described in the present application use the first isolation structure as a hard mask to etch the second trench to form a self-aligned isolation structure, which can improve the alignment accuracy of the deep trench isolation structure between adjacent pixel units of the image sensor.

[0077] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0078] It should be understood that the term "and / or" used in this embodiment includes any and all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present.

[0079] Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means there are no intervening elements.

[0080] It should also be understood that the terms “comprise,” “comprising,” “include,” or “including,” when used in this application document, indicate the presence of the recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0081] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0082] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a self-aligned isolation structure for isolating different pixel areas of an image sensor, characterized in that: include: Providing a semiconductor substrate, forming a plurality of first isolation structures in the semiconductor substrate, wherein two adjacent first isolation structures define the position of the self-aligned isolation structure; Etching the semiconductor substrate between the two adjacent first isolation structures to a specific depth to form a second trench, wherein the method for forming the second trench comprises: forming a second photoresist layer on the surface of the semiconductor substrate, wherein the second photoresist layer comprises a first opening, wherein the first opening exposes the semiconductor substrate between the two adjacent first isolation structures and a portion of the two adjacent first isolation structures; etching the semiconductor substrate along the first opening to form a second trench; and removing the second photoresist layer; The self-aligned isolation structure is formed in the second trench, and the depth of the self-aligned isolation structure is greater than the depth of the first isolation structure.

2. The method for forming a self-aligned isolation structure according to claim 1, wherein: The first isolation structure is formed simultaneously with a shallow trench isolation structure in an active region of a semiconductor substrate.

3. The method for forming a self-aligned isolation structure according to claim 2, wherein: The self-aligned isolation structure is a deep trench isolation structure, and a depth ratio of the self-aligned isolation structure to the first isolation structure is (2-30):

1.

4. The method for forming a self-aligned isolation structure according to claim 3, wherein: The depth of the first isolation structure is 90 nanometers to 400 nanometers, and the depth of the self-aligned isolation structure is 1 micrometer to 30 micrometers.

5. The method for forming a self-aligned isolation structure according to claim 1, wherein: Also includes: After forming a plurality of first isolation structures and before forming the second trenches, ion implantation is performed in the semiconductor substrate to form a well region.

6. The method for forming a self-aligned isolation structure according to claim 1, wherein: An area of ​​the portion of the first isolation structure exposed by the first opening accounts for one third to two thirds of an area of ​​the first isolation structure.

7. The method for forming a self-aligned isolation structure according to claim 1, wherein: The width of the self-aligned isolation structure is 0.2 micrometers to 1 micrometer.

8. An image sensor, characterized in that: include: semiconductor substrates; a plurality of first isolation structures located in the semiconductor substrate, wherein two adjacent first isolation structures define positions of the self-aligned isolation structures formed by the method for forming a self-aligned isolation structure according to any one of claims 1 to 7; The self-aligned isolation structure is located in the semiconductor substrate between the two adjacent first isolation structures, and the depth of the self-aligned isolation structure is greater than the depth of the first isolation structure.

9. The image sensor according to claim 8, wherein The first isolation structure is a shallow trench isolation structure, the self-aligned isolation structure is a deep trench isolation structure, and a depth ratio of the self-aligned isolation structure to the first isolation structure is (2-30):

1.

10. The image sensor according to claim 9, wherein The depth of the first isolation structure is 90 nanometers to 400 nanometers, and the depth of the self-aligned isolation structure is 1 micrometer to 30 micrometers.

11. The image sensor according to claim 8, wherein The invention also includes a well region located in the semiconductor substrate between adjacent self-aligned isolation structures.

12. The image sensor according to claim 8, wherein The width of the self-aligned isolation structure is 0.2 micrometers to 1 micrometer.

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