A p-type gallium nitride-based heterojunction PIN diode and a manufacturing method thereof

Abstract

The application relates to a P-type gallium nitride-based heterojunction PIN diode and a manufacturing method thereof, which comprises an N-type Ga2O3 substrate, an N-type Ga2O3 epitaxial layer, a P-type GaN layer, a plurality of P-type GaN regions, an N-region ohmic contact region and a P-region ohmic contact region, wherein the N-region ohmic contact region, the N-type Ga2O3 substrate, the N-type Ga2O3 epitaxial layer and the P-type GaN layer are stacked in sequence; the plurality of P-type GaN regions are distributed on the P-type GaN layer, and the doping concentration of the plurality of P-type GaN regions is greater than that of the P-type GaN layer; and the P-region ohmic contact region covers the P-type GaN layer and the surfaces of the plurality of P-type GaN regions. The PIN diode is provided with a plurality of P-type GaN regions with relatively high doping concentration on the P-type GaN layer, the P-type GaN regions with high doping concentration increase the contact area between the P-region ohmic contact region and the P-type GaN, the on-resistance of the PIN diode can be reduced, the power consumption of the device is reduced, the performance of the device is improved, and the difficulty in preparing P-type Ga2O3 is avoided.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of microelectronics, and particularly relates to a P-type gallium nitride based heterojunction PIN diode and a manufacturing method thereof. BACKGROUND

[0002] Beta-Ga2O3 is a group III semiconductor oxide with a band gap of 4.9 eV. Because of its stability, beta-Ga2O3 is widely used in high-power electronics, ultraviolet optoelectronic devices, and solar-blind ultraviolet detectors, so in the past decade beta-Ga2O3 has become increasingly attractive. In high-power electronic devices, vertical PIN diodes exhibit small reverse leakage current, high breakdown voltage, excellent power characteristics, and are widely used in military and civilian electronic equipment, and are indispensable key devices.

[0003] However, the vertical PIN diode has a high on-resistance, resulting in high power consumption and reduced performance. At the same time, for the preparation of vertical Ga2O3 PIN diodes, the difficulty in preparing P-type Ga2O3 is a common problem faced by all researchers. SUMMARY

[0004] In order to solve the above problems existing in the prior art, the present application provides a P-type gallium nitride based heterojunction PIN diode and a manufacturing method thereof. The technical problem to be solved by the present application is solved by the following technical scheme:

[0005] The embodiment of the present application provides a P-type gallium nitride based heterojunction PIN diode, comprising: an N-type Ga2O3 substrate, an N-type Ga2O3 epitaxial layer, a P-type GaN layer, a plurality of P-type GaN regions, an N-region ohmic contact region and a P-region ohmic contact region, wherein,

[0006] The N-region ohmic contact region, the N-type Ga2O3 substrate, the N-type Ga2O3 epitaxial layer and the P-type GaN layer are stacked in sequence;

[0007] The plurality of P-type GaN regions are distributed on the P-type GaN layer, and the doping concentration of the plurality of P-type GaN regions is greater than the doping concentration of the P-type GaN layer;

[0008] The P-region ohmic contact region covers the surface of the P-type GaN layer and the plurality of P-type GaN regions.

[0009] In an embodiment of the present application, the doping ions of the N-type Ga2O3 substrate include Si ions or Sn ions, the doping concentration is 1x10 19 cm -3 ~ 1x10 20 cm -3 , and the thickness is 300-650 mu m.

[0010] In one embodiment of the present invention, the doping ions of the N-type Ga2O3 epitaxial layer include Si ions or Sn ions, and the doping concentration is 1×10⁻⁶. 16 cm -3 ~1×10 17 cm -3 The thickness is 4μm to 10μm.

[0011] In one embodiment of the present invention, the dopant ions of the p-type GaN layer include Mg ions, and the doping concentration is 3 × 10⁻⁶. 18 cm -3 ~3×10 19 cm -3 The thickness ranges from 300nm to 1000nm.

[0012] In one embodiment of the present invention, the dopant ions in the p-type GaN region include Mg ions, and the doping concentration is 3 × 10⁻⁶. 19 cm -3 ~3×10 20 cm -3 The thickness is 40–300 nm.

[0013] In one embodiment of the invention, the shape of each of the P-type GaN regions includes a regular hexagon.

[0014] In one embodiment of the present invention, the plurality of P-type GaN regions are uniformly distributed in an array, and adjacent rows of the plurality of P-type GaN regions are staggered.

[0015] In one embodiment of the present invention, the side length of the regular hexagonal prism is 0.3 to 3 μm, and the distance between adjacent regular hexagonal prisms is 0.5 to 3 μm.

[0016] Another embodiment of the present invention provides a method for fabricating a heterojunction PIN diode based on p-type gallium nitride, comprising the steps of:

[0017] S1. An N-type Ga2O3 epitaxial layer is grown on one side of an N-type Ga2O3 substrate.

[0018] S2. A P-type GaN layer is grown on the N-type Ga2O3 epitaxial layer;

[0019] S3. A plurality of P-type GaN regions are prepared on the P-type GaN layer, such that the plurality of P-type GaN regions are distributed on the P-type GaN layer, and the doping concentration of the plurality of P-type GaN regions is greater than the doping concentration of the P-type GaN layer.

[0020] S4. Prepare an N-region ohmic contact region on the other surface of the N-type Ga2O3 substrate;

[0021] S5. Prepare P-region ohmic contact regions on the P-type GaN layer and on the surface of the plurality of P-type GaN regions.

[0022] In one embodiment of the present invention, step S3 includes:

[0023] S31. Prepare a P-type GaN intermediate layer on the P-type GaN layer;

[0024] S32. Etch the P-type GaN intermediate layer to form the plurality of P-type GaN regions.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] 1. The PIN diode of the present invention has a plurality of P-type GaN regions distributed on a P-type GaN layer, and the doping concentration of the plurality of P-type GaN regions is greater than that of the P-type GaN layer. By setting heavily doped P-type regions on a lightly doped P-type layer, the heavily doped P-type GaN regions can reduce the on-resistance of the PIN diode, thereby reducing the power consumption of the device and improving the performance of the device.

[0027] 2. The PIN diode of the present invention, by setting multiple P-type GaN regions, with the P-type ohmic contact region covering the surface of the multiple P-type GaN regions and the surface of the P-type GaN layer, increases the contact area between the P-type region and the P-type ohmic contact region, thereby further reducing the on-resistance of the PIN diode, reducing the power consumption of the device, and improving the performance of the device.

[0028] 3. In the PIN diode of the present invention, the P-type region is made of P-type GaN material. The P-type doping concentration of P-type GaN can be specifically characterized and precisely controlled, avoiding the difficulty of preparing P-type Ga2O3, thereby achieving a high-quality P-type region. At the same time, the thermal conductivity of GaN is about five times that of Ga2O3. Using P-type GaN material as the P-type region can promote the heat dissipation of the PIN diode and improve the device performance. Attached Figure Description

[0029] Figure 1 A schematic diagram of a heterojunction PIN diode based on p-type gallium nitride provided in an embodiment of the present invention;

[0030] Figure 2 A schematic diagram of the distribution of multiple P-type GaN regions provided in an embodiment of the present invention;

[0031] Figure 3 A schematic flowchart illustrating a method for fabricating a heterojunction PIN diode based on p-type gallium nitride, provided in an embodiment of the present invention.

[0032] Figures 4a-4eThis is a schematic diagram illustrating the process of fabricating a heterojunction PIN diode based on P-type gallium nitride, as provided in an embodiment of the present invention. Detailed Implementation

[0033] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0034] Example 1

[0035] Please see Figure 1 , Figure 1 This is a schematic diagram of a heterojunction PIN diode based on p-type gallium nitride, provided as an embodiment of the present invention.

[0036] The heterojunction PIN diode based on P-type gallium nitride includes an N-type Ga2O3 substrate 1, an N-type Ga2O3 epitaxial layer 2, a P-type GaN layer 3, several P-type GaN regions 4, an N-region ohmic contact region 5, and a P-region ohmic contact region 6.

[0037] The structure consists of an N-type ohmic contact region 5, an N-type Ga2O3 substrate 1, an N-type Ga2O3 epitaxial layer 2, and a P-type GaN layer 3, stacked sequentially. Several P-type GaN regions 4 are distributed on the P-type GaN layer 3, and the doping concentration of these P-type GaN regions 4 is greater than that of the P-type GaN layer 3. A P-type ohmic contact region 6 covers the surface of the P-type GaN layer 3 and the surfaces of the P-type GaN regions 4.

[0038] Specifically, multiple P-type GaN regions 4 can be uniformly distributed on the P-type GaN layer 3 or non-uniformly distributed on the P-type GaN layer 3; that is, the distance between two adjacent P-type GaN regions 4 can be equal or unequal, and this embodiment does not impose further restrictions.

[0039] Specifically, the doping ions in the N-type Ga2O3 substrate 1 include Si ions or Sn ions, with a doping concentration of 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The thickness ranges from 300 μm to 650 μm. The doping ions in the N-type Ga₂O₃ epitaxial layer 2 include Si or Sn ions, with a doping concentration of 1 × 10⁻⁶. 16 cm -3 ~1×10 17 cm -3 The thickness ranges from 4 μm to 10 μm. The doping ions in the p-type GaN layer 3 include Mg ions, with a doping concentration of 3 × 10⁻⁶. 18 cm -3 ~3×10 19 cm -3The thickness ranges from 300 nm to 1000 nm. The doping ions in region 4 of the p-type GaN include Mg ions, with a doping concentration of 3 × 10⁻⁶. 19 cm -3 ~3×10 20 cm -3 The thickness is 40–300 nm. Therefore, in this embodiment, the material of the N-type Ga2O3 substrate 1 is N... + -Ga2O3, the material of the N-type Ga2O3 epitaxial layer 2 is N - -Ga2O3, the material of the P-type GaN layer 3 is P + -GaN, the material of the P-type GaN region is P ++ -GaN.

[0040] Specifically, the material of the N-region ohmic contact region 5 includes a Ti / Au combination or a Ti / Al / Ni / Au combination. When the N-region ohmic contact region 5 is a Ti / Au combination, the thickness of the first Ti layer is 20–100 nm, and the thickness of the second Au layer is 40–200 nm. When the N-region ohmic contact region 5 is a Ti / Al / Ni / Au combination, the growth thickness of the first Ti layer is 20–100 nm, the growth thickness of the second Al layer is 50–200 nm, the growth thickness of the third Ni layer is 30–100 nm, and the growth thickness of the fourth Au layer is 30–200 nm.

[0041] The material of the P-region ohmic contact region 6 includes a Ni / Au combination. When the P-region ohmic contact region 6 is a Ni / Au combination, the thickness of the first layer of metal Ni is 15–40 nm, and the thickness of the second layer of metal Au is 40–100 nm.

[0042] In one specific embodiment, from a top view, the shape of the P-type GaN region 4 can be a polygon; preferably, the shape of the P-type GaN region 4 is a regular polygon; more preferably, the shape of the P-type GaN region 4 includes a regular hexagon, in which case the P-type GaN region 4 is a regular hexagonal prism.

[0043] Please see Figure 2 , Figure 2This is a schematic diagram illustrating the distribution of multiple P-type GaN regions according to an embodiment of the present invention. When the P-type GaN region 4 is a regular hexagonal prism, the multiple P-type GaN regions 4 are evenly distributed in an array, with adjacent rows of P-type GaN regions 4 staggered. It can be understood that the multiple P-type GaN regions 4 are arranged in several rows, with equal distances between the P-type GaN regions 4 in each row. Between adjacent rows of P-type GaN regions 4, one row's P-type GaN regions 4 are interspersed between two adjacent P-type GaN regions 4 in the other row. Preferably, one row's P-type GaN regions 4 are interspersed in the middle of two adjacent P-type GaN regions 4, thus ensuring equal distances between the P-type GaN regions 4 in each column. That is, the edges of one P-type GaN region 4 are opposite to the edges of another P-type GaN region 4, and the distances between adjacent P-type GaN regions 4 are equal.

[0044] Specifically, the side length l of the regular hexagonal prism is 0.3 to 3 μm, and the distance d between adjacent regular hexagonal prisms is 0.5 to 3 μm; that is, the side length of the P-type GaN region 4 is 0.3 to 3 μm, and the side length of the opposite side of the P-type GaN region 4 is 0.5 to 3 μm.

[0045] In this embodiment, the P-type GaN region adopts a regular hexagonal prism, and several P-type GaN regions are evenly distributed in a 4-fold array. On the one hand, due to the high symmetry, the electric field distribution of the PIN diode is uniform, resulting in high device performance. On the other hand, the structure of several P-type GaN regions evenly distributed in a 4-fold array results in high device area utilization and good device performance.

[0046] In this embodiment, the PIN diode has several P-type GaN regions distributed on the P-type GaN layer, and the doping concentration of the several P-type GaN regions is greater than the doping concentration of the P-type GaN layer. By setting heavily doped P-type regions on the lightly doped P-type layer, the heavily doped P-type GaN regions can reduce the on-resistance of the PIN diode, thereby reducing the power consumption of the device and improving the performance of the device.

[0047] In this embodiment, the PIN diode has multiple P-type GaN regions. The P-type ohmic contact region covers the surface of the multiple P-type GaN regions and the surface of the P-type GaN layer, which increases the contact area between the P-type region and the P-type ohmic contact region. This further reduces the on-resistance of the PIN diode, lowers the power consumption of the device, and improves the performance of the device.

[0048] In this embodiment of the PIN diode, the P-type region uses P-type GaN material. The P-type doping concentration of P-type GaN can be specifically characterized and precisely controlled, avoiding the difficulties in preparing P-type Ga2O3, thereby achieving a high-quality P-type region. At the same time, the thermal conductivity of GaN is about five times that of Ga2O3. Using P-type GaN material as the P-type region can promote the heat dissipation of the PIN diode and improve the device performance.

[0049] Example 2

[0050] Based on Example 1, please refer to Figure 3 and Figures 4a-4e , Figure 3 This is a schematic flowchart illustrating a method for fabricating a heterojunction PIN diode based on p-type gallium nitride, as provided in an embodiment of the present invention. Figures 4a-4e This is a schematic diagram illustrating the process of fabricating a heterojunction PIN diode based on P-type gallium nitride, as provided in an embodiment of the present invention.

[0051] The fabrication method of the heterojunction PIN diode based on p-type gallium nitride includes the following steps:

[0052] S1. An N-type Ga2O3 epitaxial layer 2 is grown on one side of the N-type Ga2O3 substrate 1. Please refer to [link / reference]. Figure 4a .

[0053] First, the N-type Ga₂O₃ substrate 1 was subjected to standard cleaning. Then, the cleaned N-type Ga₂O₃ substrate 1 was placed in a metal-organic chemical vapor deposition (MOCVD) system with a trimethylgallium™Ga flow rate of 5.0 × 10⁻⁶. -6 ~9.0×10 -6 mol / min, O2 flow rate 2×10 -2 ~4×10 -2 mol / min, temperature 60–100℃, pressure 500 Pa, doped ions are Si or Sn ions, doping concentration is 1×10 16 cm -3 ~1×10 17 cm -3 Under these conditions, low-doped N₂ atoms with a thickness of 4 μm to 10 μm are epitaxially grown. - - A Ga2O3 thin film was formed to create an N-type Ga2O3 epitaxial layer 2. Subsequently, the epitaxial material was cleaned: the substrate with the N-type Ga2O3 epitaxial layer 2 was sequentially cleaned with organic solvent and deionized water, then immersed in a mixed solution with a volume ratio of HF:H2O = 1:1 for 60 seconds, cleaned with flowing deionized water, and dried with high-purity nitrogen gas.

[0054] S2. Grow a P-type GaN layer 3 on the N-type Ga2O3 epitaxial layer 2. (See below) Figure 4b .

[0055] Specifically, P was prepared on a lightly doped N-type Ga2O3 epitaxial layer 2 using the MPCVD method. + -GaN layer, forming a P-type GaN layer 3.

[0056] S3. Prepare several P-type GaN regions 4 on the P-type GaN layer 3, such that the P-type GaN regions 4 are distributed on the P-type GaN layer 3, and the doping concentration of the P-type GaN regions 4 is greater than the doping concentration of the P-type GaN layer 3.

[0057] S31. Prepare a P-type GaN intermediate layer 41 on the P-type GaN layer 3. (See below) Figure 4b .

[0058] Specifically, P-type GaN layers were prepared on P-type GaN layer 3 using the MPCVD method. ++ -GaN layer, forming a P-type GaN intermediate layer 41.

[0059] S32, Etch the P-type GaN intermediate layer 41 to form several P-type GaN regions 4. Please refer to [link / reference]. Figure 4c and Figure 2 .

[0060] First, photoresist is spin-coated to photolithographically shape the P-type GaN intermediate layer region to be etched away. Then, using an ICP (Inductively Coupled Plasma) device, the excess P-type gallium nitride is etched under the following conditions: upper electrode power 250–300 W, lower electrode power 40–80 W, chamber pressure 9–12 mTorr, gas flow rate BCl3 / Cl2 30–60 / 30–60 sccm, and chuck temperature 15–20 °C, forming several P-type GaN regions 4. The structure of the formed P-type GaN regions 4 can be found in [reference needed]. Figure 2 Similar to Example 1, it will not be repeated here. Finally, the photoresist on the device surface is removed.

[0061] In a preferred embodiment, the prepared P-type GaN regions 4 are all regular hexagonal prism structures.

[0062] S4. Prepare an N-region ohmic contact region 5 on the other surface of the N-type Ga2O3 substrate 1. (See below) Figure 4d .

[0063] Specifically, using an electron beam evaporation stage, Ti / Au combination or Ti / Al / Ni / Au combination is sequentially evaporated on the back side of N-type Ga2O3 substrate 1; after the electrode metal is evaporated, it is rapidly thermally annealed for 60s in an N2 environment at 400-600℃ to form N-region ohmic contact region 5.

[0064] Specifically, when the N-region ohmic contact region 5 is a Ti / Au combination, the thickness of the first Ti layer is 20–100 nm, and the thickness of the second Au layer is 40–200 nm. When the N-region ohmic contact region 5 is a Ti / Al / Ni / Au combination, the growth thickness of the first Ti layer is 20–100 nm, the growth thickness of the second Al layer is 50–200 nm, the growth thickness of the third Ni layer is 30–100 nm, and the growth thickness of the fourth Au layer is 30–200 nm.

[0065] S5. Prepare P-type ohmic contact regions 6 on the surface of the P-type GaN layer 3 and several P-type GaN regions 4. (See below) Figure 4e .

[0066] Specifically, Ni / Au composites are sequentially evaporated onto the surface of the P-type GaN layer 3 and several P-type GaN regions 4 to serve as the P-region ohmic contact region metal; wherein the Ni growth thickness is 15–40 nm and the Au growth thickness is 40–100 nm. After the electrode metal evaporates, it is annealed in an O2 environment at 500–700 °C for 2–5 min to form the P-region ohmic contact region 6, thus completing the fabrication of the PIN diode.

[0067] In this embodiment, the P-type GaN region adopts a regular hexagonal prism, and several P-type GaN regions are evenly distributed in a 4-fold array. On the one hand, due to the high symmetry, the electric field distribution of the PIN diode is uniform, resulting in high device performance. On the other hand, the structure of several P-type GaN regions evenly distributed in a 4-fold array results in high device area utilization and good device performance.

[0068] In this embodiment, the PIN diode has several P-type GaN regions distributed on the P-type GaN layer, and the doping concentration of the several P-type GaN regions is greater than the doping concentration of the P-type GaN layer. By setting heavily doped P-type regions on the lightly doped P-type layer, the heavily doped P-type GaN regions can reduce the on-resistance of the PIN diode, thereby reducing the power consumption of the device and improving the performance of the device.

[0069] In this embodiment, the PIN diode has multiple P-type GaN regions. The P-type ohmic contact region covers the surface of the multiple P-type GaN regions and the surface of the P-type GaN layer, which increases the contact area between the P-type region and the P-type ohmic contact region. This further reduces the on-resistance of the PIN diode, lowers the power consumption of the device, and improves the performance of the device.

[0070] In this embodiment of the PIN diode, the P-type region uses P-type GaN material. The P-type doping concentration of P-type GaN can be specifically characterized and precisely controlled, avoiding the difficulties in preparing P-type Ga2O3, thereby achieving a high-quality P-type region. At the same time, the thermal conductivity of GaN is about five times that of Ga2O3. Using P-type GaN material as the P-type region can promote the heat dissipation of the PIN diode and improve the device performance.

[0071] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A heterojunction PIN diode based on p-type gallium nitride, characterized in that, include: The structure comprises an N-type Ga2O3 substrate (1), an N-type Ga2O3 epitaxial layer (2), a P-type GaN layer (3), several P-type GaN regions (4), an N-type ohmic contact region (5), and a P-type ohmic contact region (6), wherein... The N-region ohmic contact region (5), the N-type Ga2O3 substrate (1), the N-type Ga2O3 epitaxial layer (2), and the P-type GaN layer (3) are stacked sequentially; The plurality of P-type GaN regions (4) are distributed on the P-type GaN layer (3), and the doping concentration of the plurality of P-type GaN regions (4) is greater than the doping concentration of the P-type GaN layer (3); each of the P-type GaN regions (4) is a regular hexagonal prism; the plurality of P-type GaN regions (4) are uniformly distributed in an array, and adjacent rows of the plurality of P-type GaN regions (4) are staggered. The P-region ohmic contact region (6) covers the surface of the P-type GaN layer (3) and the surface of the plurality of P-type GaN regions (4).

2. The heterojunction PIN diode based on p-type gallium nitride according to claim 1, characterized in that, The N-type Ga2O3 substrate (1) is doped with either Si or Sn ions, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The thickness is 300μm to 650μm.

3. The heterojunction PIN diode based on p-type gallium nitride according to claim 1, characterized in that, The doped ions of the N-type Ga2O3 epitaxial layer (2) include Si ions or Sn ions, with a doping concentration of 1×10⁻⁶. 16 cm -3 ~1×10 17 cm -3 The thickness is 4μm to 10μm.

4. The heterojunction PIN diode based on p-type gallium nitride according to claim 1, characterized in that, The doped ions of the p-type GaN layer (3) include Mg ions, with a doping concentration of 3 × 10⁻⁶. 18 cm -3 ~3×10 19 cm -3 The thickness ranges from 300nm to 1000nm.

5. The heterojunction PIN diode based on p-type gallium nitride according to claim 1, characterized in that, The doped ions in the p-type GaN region (4) include Mg ions, with a doping concentration of 3 × 10⁻⁶. 19 cm -3 ~3×10 20 cm -3 The thickness is 40–300 nm.

6. The heterojunction PIN diode based on p-type gallium nitride according to claim 1, characterized in that, The side length of the regular hexagonal prism is 0.3 to 3 μm, and the distance between adjacent regular hexagonal prisms is 0.5 to 3 μm.

7. A method for fabricating a heterojunction PIN diode based on p-type gallium nitride, characterized in that, Including the following steps: S1. An N-type Ga2O3 epitaxial layer (2) is grown on one side of the N-type Ga2O3 substrate (1); S2. A P-type GaN layer (3) is grown on the N-type Ga2O3 epitaxial layer (2); S3. A plurality of P-type GaN regions (4) are prepared on the P-type GaN layer (3), such that the plurality of P-type GaN regions (4) are distributed on the P-type GaN layer (3), and the doping concentration of the plurality of P-type GaN regions (4) is greater than the doping concentration of the P-type GaN layer (3); each of the P-type GaN regions (4) is a regular hexagonal prism; the plurality of P-type GaN regions (4) are uniformly distributed in an array, and adjacent rows of the plurality of P-type GaN regions (4) are staggered. S4. An N-region ohmic contact region (5) is prepared on the other surface of the N-type Ga2O3 substrate (1); S5. Prepare P-region ohmic contact regions (6) on the surface of the P-type GaN layer (3) and the plurality of P-type GaN regions (4).

8. The method for fabricating a heterojunction PIN diode based on p-type gallium nitride according to claim 7, characterized in that, Step S3 includes: S31. A P-type GaN intermediate layer (41) is prepared on the P-type GaN layer (3); S32. Etch the P-type GaN intermediate layer (41) to form the plurality of P-type GaN regions (4).

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