Integrated assembly having void along gate region and method of forming conductive structure

Abstract

Some embodiments include an integrated assembly having a semiconductor material structure with a first source / drain region, a second source / drain region, and a channel region between the first and second source / drain regions. The semiconductor material structure has a first side and an opposing second side. A first conductive structure is adjacent to the first side and is operatively proximate to the channel region to gate control coupling of the first and second source / drain regions through the channel region. A second conductive structure is adjacent to the second side and is spaced apart from the second side by an intervening region that includes a void. Some embodiments include methods of forming an integrated assembly.

Description

[0001] Related patent data

[0002] This application claims priority to and the benefit of U.S. Patent Application No. 16 / 727,153, filed December 26, 2019, the disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] Integrated assemblies (e.g., integrated memory). Integrated assemblies having voids along gate regions. Methods of forming integrated assemblies. BACKGROUND

[0004] Memory is a type of integrated circuitry and is used in computer systems to store data. An example memory is DRAM (dynamic random access memory). DRAM cells (memory cells) can each include a transistor in combination with a capacitor. The DRAM cells can be arranged in an array; where word lines (gate lines) extend along rows of the array and digit lines (bit lines) extend along columns of the array. The word lines can be coupled with the transistors of the memory cells. Each memory cell can be uniquely addressed by a combination of one of the word lines and one of the digit lines.

[0005] A problem that can be encountered in conventional memory architectures is crosstalk (interference) between memory cells, resulting in loss of data. As memory architectures expand to increased levels of integration, the crosstalk problem becomes increasingly severe. It is desirable to mitigate or prevent such unwanted crosstalk. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figures 1 to 1B is a diagrammatic view of a region of an example construction at an example processing stage of an example method for forming an example integrated assembly. Figure 1 is a top view. Figure 1A and 1B are cross-sectional side views along lines A-A and B-B, respectively, of Figure 1

[0007] Figures 2 to 2B is a diagrammatic view of a region of Figures 1 to 1B at an example processing stage after the example processing stage of Figures 1 to 1B Figure 2 is a top view. Figure 2A and 2B are cross-sectional side views along lines A-A and B-B, respectively, of Figure 2

[0008] Figures 3 to 3B is a diagrammatic view of a region of Figures 2 to 2B at an example processing stage after the example processing stage of Figures 1 to 1B Figure 3 is a top view.​​​​Figure 3A and 3B are cross-sectional side views along lines A-A and B-B, respectively, of Figure 3 .

[0009] Figures 4 to 4B are diagrammatic views of a region of Figures 3 to 3B at an example processing stage after the example processing stage of Figures 1 to 1B . Figure 4 is a top view. Figure 4A and 4B are cross-sectional side views along lines A-A and B-B, respectively, of Figure 4 .

[0010] Figures 5 to 5B are diagrammatic views of a region of Figures 4 to 4B at an example processing stage after the example processing stage of Figures 1 to 1B . Figure 5 is a top view. Figure 5A and 5B are cross-sectional side views along lines A-A and B-B, respectively, of Figure 5 .

[0011] Figures 6 to 6B are diagrammatic views of a region of Figures 5 to 5B at an example processing stage after the example processing stage of Figures 1 to 1B . Figure 6 is a top view. Figure 6A and 6B are cross-sectional side views along lines A-A and B-B, respectively, of Figure 6 .

[0012] Figures 7 to 7B are diagrammatic views of a region of Figures 6 to 6B at an example processing stage after the example processing stage of Figures 1 to 1B . Figure 7 is a top view. Figure 7A and 7B are cross-sectional side views along lines A-A and B-B, respectively, of Figure 7 .

[0013] Figures 8 to 8B are diagrammatic views of a region of Figures 7 to 7B at an example processing stage after the example processing stage of Figures 1 to 1B . Figure 8 is a top view. Figure 8A and 8B are cross-sectional side views along lines A-A and B-B, respectively, of Figure 8 .

[0014] Figures 9 to 9B are diagrammatic views of a region of Figures 8 to 8B at an example processing stage after the example processing stage of Figures 1 to 1BA diagrammatic view of the area. Figure 9 It is a top view. Figure 9A and 9B They are respectively along Figure 9 The side view of the cross section of lines AA and BB.

[0015] Figures 10 to 10B Is Figures 9 to 9B The instance processing phase after the instance processing phase Figures 1 to 1B A diagrammatic view of the area. Figure 10 It is a top view. Figure 10A and 10B They are respectively along Figure 10 The side view of the cross section of lines AA and BB.

[0016] Figures 11 to 11B Is Figures 10 to 10B The instance processing phase after the instance processing phase Figures 1 to 1B A diagrammatic view of the area. Figure 11 It is a top view. Figure 11A and 11B They are respectively along Figure 11 The side view of the cross section of lines AA and BB. Figures 11 to 11B The structure can be viewed as a region of instance integration assembly, or a region of instance memory device.

[0017] Figures 12 to 12B Is Figures 11 to 11B The instance processing phase after the instance processing phase Figures 1 to 1B A diagrammatic view of the area. Figure 12 It is a top view. Figure 12A and 12B They are respectively along Figure 12 The side view of the cross section of lines AA and BB.

[0018] Figures 13 to 13B Is Figures 12 to 12B The instance processing phase after the instance processing phase Figures 1 to 1B A diagrammatic view of the area. Figure 13 It is a top view. Figure 13A and 13B They are respectively along Figure 13 The side view of the cross section of lines AA and BB. Figures 13 to 13B The structure can be viewed as a region of instance integration assembly, or a region of instance memory device.

[0019] Figures 14 to 14B Is Figures 13 to 13B The instance processing phase after the instance processing phase Figures 1 to 1B A diagrammatic view of the area. Figure 14 It is a top view. Figure 14A and 14B They are respectively alongFigure 14 cross-sectional side view of lines A-A and B-B.

[0020] Figure 15 is a schematic diagram of a region of an example memory array. DETAILED DESCRIPTION

[0021] Some embodiments include an integrated assembly (e.g., an integrated memory) having a conductive structure (e.g., a gate) between a pair of transistor channel regions. One of the channel regions is operatively proximate to the conductive structure such that operation of the conductive structure controls current flow within the channel region. The other of the channel regions is separated from the conductive structure by an intervening region that includes a void. Some embodiments include methods of forming an integrated assembly. Reference is made to Figures 1 to 15 Example embodiments are described.

[0022] Reference is made to Figures 1 to 1B , the integrated assembly (structure, architecture, etc.) 10 includes a base 12. The base 12 can comprise a semiconductor material; and, for example, can comprise, consist essentially of, or consist of monocrystalline silicon. The base 12 can be referred to as a semiconductor substrate. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, the base 12 can correspond to a semiconductor substrate that houses one or more materials associated with integrated circuit fabrication. Such materials can include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

[0023] An insulative material 14 is supported above the base 12. The insulative material 14 can comprise any suitable electrically insulative composition; and, in some embodiments, can comprise, consist essentially of, or consist of silicon dioxide. A gap is provided between the insulative material 14 and the base 12 to indicate that other materials, structures, etc. can be present that are provided between the base 12 and the insulative material 14. However, in some embodiments, the insulative material 14 can be directly against an upper surface of the base 12.

[0024] Digital lines 16 are above insulative material 14. Digital lines 16 include electrically conductive digital line material 18. Digital line material 18 can include any suitable electrically conductive composition; e.g., one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or electrically conductive doped semiconductor materials (e.g., electrically conductive doped silicon, electrically conductive doped germanium, etc.). In some embodiments, digital line material 18 can include, consist essentially of, or consist of one or more metal-containing materials; e.g., one or more of tungsten, titanium, tungsten nitride, titanium nitride, tungsten silicide, titanium silicide, etc.

[0025] Semiconductor material 20 is above digital lines 16. Semiconductor material 20 can include any suitable composition; and in some embodiments can include, consist essentially of, or consist of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; where the term III / V semiconductor material refers to a semiconductor material that includes an element selected from Groups III and V of the Periodic Table (where Groups III and V are the old nomenclature, and are now referred to as Groups 13 and 15). In some embodiments, semiconductor material 20 can include, consist essentially of, or consist of silicon. Silicon can be in any suitable crystalline form (e.g., one or more of single-crystalline, poly-crystalline, and amorphous).

[0026] Semiconductor material 20 and digital lines 16 are together patterned as tracks 22, where such tracks extend along a first direction indicated as the y-axis direction. Tracks 22 can be considered to be supported by insulative material 14, which in turn can be considered to be supported by base 12.

[0027] Semiconductor material 20 of tracks 22 is configured as a semiconductor material strand (linear configuration) 24 above the digital lines.

[0028] Semiconductor material 20 of each of semiconductor material linear configuration 24 is shown as including a lower heavily doped region 26, an upper heavily doped region 28, and an intermediate region 30 between the upper and lower regions 26 and 28. Dotted lines 25 and 27 are provided to schematically illustrate the approximate boundaries between the heavily doped regions and the intermediate region. Heavily doped regions 26 and 28 are to become, respectively, lower and upper source / drain regions of vertical transistors (access devices) and can be referred to as source / drain regions. Intermediate region 30 is to become the channel region of the transistors and thus can be referred to as a channel region. Although semiconductor material 20 is shown as being doped at processing stage 22, it is to be understood that in other embodiments at least some of the doping of semiconductor material 20 can occur at a later processing stage. Figures 1 to 1B

[0029] ​A metal-containing material 32 is formed over the semiconductor material 20. The material 32 can comprise any suitable composition, and in some embodiments can comprise one or more of the metal-containing materials described above with respect to the conductive material 18. The materials 18 and 32 can comprise the same composition as one another, or can comprise different compositions with respect to one another. In some embodiments, the material 18 of the digit line 16 can be referred to as a first electrode material, and the material 32 can be referred to as a second electrode material. The first electrode material 18 is electrically coupled with the bottom source / drain region 26, and the second electrode material 32 is electrically coupled with the upper source / drain region 28.

[0030] Insulating materials 34 and 36 are over the conductive material 32. Such insulating materials can comprise any suitable composition. In some embodiments, the first insulating material 34 can comprise, consist essentially of, or consist of silicon dioxide or carbon-doped silicon dioxide; and the second insulating material 36 can comprise, consist essentially of, or consist of silicon nitride.

[0031] The materials 32, 34, and 36 can be considered part of the track (linear feature) 22. In some embodiments, the materials 18, 20, 32, 34, and 36 can be patterned from a wide area to form the track 22.

[0032] The tracks 22 are spaced apart from one another by gaps 38, with such gaps extending to the upper surface of the insulating material 14 in the illustrated embodiment.

[0033] Referring to Figures 2 to 2B A first material 40 is provided over the tracks 22 and within the gaps 38. The first material 40 lines the tracks 22, and can be considered to form a track lining (linear feature lining) 42. The first material 40 can comprise any suitable composition; and in some embodiments can comprise, consist essentially of, or consist of carbon-doped silicon dioxide. The carbon-doped silicon dioxide can have any suitable carbon concentration; and in some embodiments can have a carbon concentration of at least about 1 atomic percent (at%), at least about 3 at%, at least about 5 at%, at least about 10 at%, etc. In some embodiments, the first material 40 can be omitted.

[0034] A second material 44 is formed within the gaps 38, and specifically is provided over (along, adjacent to) the track lining 42. The second material 44 can comprise an electrically insulating material; and in some embodiments can comprise, consist essentially of, or consist of silicon dioxide.

[0035] A planarized upper surface 45 is formed across the materials 40 and 44. Such a planarized surface can be formed with any suitable process including, for example, chemical mechanical polishing (CMP).

[0036] Referring Figures 3 to 3B , the insulating material 44 is recessed into the gap 38, and the first material 40 (e.g., carbon-doped silicon dioxide) is removed from above the material 36 (e.g., silicon nitride) of the rails 22. In some embodiments, the insulating material 44 comprises silicon dioxide, and is recessible by an etch selective to the carbon-doped silicon dioxide of the material 40. Subsequently, the material 40 can be subjected to an anisotropic etch to remove such material from above the top of the rails 22.

[0037] Referring Figures 4 to 4B , a material 46 is formed within the gap 38 and across the rails 22. In some embodiments, the material 46 comprises the same composition as the material 36, and thus the dashed line 47 is provided to indicate that the materials 36 and 46 can merge with one another. For example, the materials 36 and 46 can each comprise, consist essentially of, or consist of silicon nitride.

[0038] The material 46 has a planarized upper surface 49. Such a planarized surface can be formed with any suitable process including, for example, CMP.

[0039] Referring Figures 5 to 5B , a material 48 is formed above the planarized surface 49. In some embodiments, the material 48 can comprise, consist essentially of, or consist of silicon.

[0040] Referring Figures 6 to 6B , a trench 50 is formed to extend into the rails 22 Figures 5 to 5B ) and through the insulating material 44. The trench 50 extends along a second direction corresponding to the illustrated x-axis direction. The second direction of the trench (i.e., the x-axis direction) intersects the first direction of the rails 22 (i.e., the y-axis direction). In the illustrated embodiment, the second direction of the trench is orthogonal to the first direction of the rails. In other embodiments, the second direction of the trench can intersect the first direction of the rails without being orthogonal to such first direction.

[0041] The trench 50 extends into the semiconductor material linear configuration 24 Figures 5 to 5B ) and does not destroy the digit lines 16 (as shown in Figure 6A ). The trench 50 can or can not extend into the doped regions 26. The illustrated trench 50 has a first side 51, an opposing second side 53, and a bottom region 55.

[0042] The trench 50 patterns a semiconductor material structure 52 from the semiconductor material linear configuration 24 (e.g., as shown in Figure 5AThe semiconductor material structure 52 includes semiconductor material pillars 54, where such pillars extend upwardly from a semiconductor material base 56. The semiconductor material pillars include upper source / drain regions 28, and channel regions 30 below the upper source / drain regions. The pillars 54 can or can not include portions of lower source / drain regions 26. In the illustrated embodiment, the base 56 includes a majority of the lower source / drain regions 26. In other embodiments, the trench 50 can extend completely through the semiconductor material 20, such that the lower source / drain regions 26 are within the pillars 54 and the base 56 is substantially non-existent.

[0043] Referring to Figures 7 to 7B A first material liner 58 is formed within the trench 50, and a second material liner 60 is formed above the first liner. The first material liner 50 and the second material liner 60 partially fill the trench 50. A fill material 62 is formed within the remaining portion(s) of the partially filled trench.

[0044] The first material liner 58 includes a first liner material (first material) 64. The first liner material 64 can include any suitable composition; and in some embodiments, can include, consist essentially of, or consist of carbon-doped silicon dioxide. Thus, in some embodiments, the first liner material 64 can include the same composition as the rail liner material 40 of the rail liner 42. In some embodiments, the carbon-doped silicon dioxide of the first liner material 64 can have a carbon concentration of at least about 1 at%, at least about 3 at%, at least about 5 at%, at least about 10 at%, etc.

[0045] The second material liner 60 includes a second liner material (second material) 66. The second liner material 66 can include any suitable composition; and in some embodiments, can include, consist essentially of, or consist of silicon nitride.

[0046] The fill material 62 can include any suitable composition; and in some embodiments, can include, consist essentially of, or consist of silicon dioxide. The material 62 can be formed as a spin-on dielectric (SOD) or a spin-on glass (SOG).

[0047] A planarization surface 67 extends through the materials 48, 62, 64, and 66. The planarization surface 67 can be formed with any suitable process (e.g., CMP).

[0048] Referring to Figures 8 to 8BA masking material 68 is formed above a planarized surface 67 and patterned into segments 70. Gaps 72 are located between segments 70. The masking material 68 may include any suitable composition; and in some embodiments, it may include one or two of silicon dioxide and photoresist, substantially composed of one or two of silicon dioxide and photoresist, or composed of one or two of silicon dioxide and photoresist.

[0049] The second material liner 66 is exposed within the gap 72 along a region of the first side 51 of the trench 50. In some embodiments, the masking material 68 and the semiconductor material 48 may be considered to form a hard mask together, and the region of the second material liner 66 may be considered to be exposed within the window through this hard mask.

[0050] refer to Figures 9 to 9B The second material liner 60 is recessed along the first side 51 of the groove 50. The masking material 68 protects the second material liner 60 along the second side 53 of the groove, so that the second material liner 60 is not recessed along the second side of the groove.

[0051] The second material liner 60 recesses at the first side 51 of the trench 50 to form an opening 74 along the first material liner 58. The opening 74 may be formed to any suitable depth. In some embodiments, the bottom region of the opening 74 defines the approximate location of the transistor gate formed in a subsequent processing stage.

[0052] Section 76 of the first material liner 58 is exposed along the opening 74.

[0053] refer to Figures 10 to 10B The exposed section (area) 76 of the first material liner 58. Figures 9 to 9B The material 78 is converted into an electrostatic insulating material 78 suitable for use as a gate dielectric material. The electrostatic insulating material 78 may include any suitable composition; and in some embodiments, it may include silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide. In some embodiments, the exposed section 76 of the first material liner 58 is removed and replaced with the electrostatic insulating material 78. In other embodiments, the material 64 of the first material liner 58 comprises carbon-doped silicon dioxide, and this material is oxidized to convert it into silicon dioxide, thereby forming at least some of the electrostatic insulating materials 78 from the material 64 of the first material liner 58.

[0054] In the illustrated embodiment, material 78 has an interface 79 with material 64 of the first material liner 58, the interface extending substantially in common with the upper surface 81 of the recessed material 66 of the second material liner 60. In other embodiments, interface 79 may be below the upper surface 81.

[0055] Remove 68 pieces of concealing material. Figures 9 to 9B) and the fill material 62 is subsequently recessed to form a trench 80. In some embodiments, the fill material 62 comprises silicon dioxide and is recessed by wet oxidation etching. The fill material 62 can be recessed to any suitable level within the trench 80, and in some embodiments can be completely removed. The trench 80 coextends with the trench 50 of Figures 6 to 6B but is narrower than the trench 50. In some embodiments, the narrow trench 80 can be considered a region of the trench 50.

[0056] Referring to Figures 11 to 11B , the upper surface of the assembly 10 is planarized to remove the materials 46 and 48 from above the material 36, and a planarized upper surface 83 is formed beyond the materials 36, 46, 64, 66, and 78. In some embodiments, a sacrificial material can be formed within the trench 80 during this planarization, and the sacrificial material can be subsequently removed after planarization.

[0057] A word line (gate line) 84 is formed within the trench 80 and formed above the recessed second material liner 60. In the illustrated embodiment, the word line comprises two materials 86 and 88; where the material 86 is a metal-containing material and the material 88 is conductively doped silicon. The metal-containing material 86 can comprise any suitable composition; including, for example, one or more of tungsten, titanium, tungsten nitride, titanium nitride, tungsten silicide, titanium silicide, etc. The materials 86 and 88 have different work functions relative to one another, and thus the illustrated word line 84 can be considered a dual work function word line. In other embodiments, the word line can comprise other configurations, and can or can not have a dual work function configuration.

[0058] The word line 84 extends along the illustrated x-axis direction and thus crosses the digit line 16. In some embodiments, the word line 84 can be considered to represent a conductive structure extending along the x-axis direction.

[0059] The word line comprises a gate along the channel region 30 of the pillar 52.

[0060] Figure 11 The top-down view shows that the materials 40 and 64 are the same composition as one another and merge to form a configuration of the composition 40 / 64.

[0061] Referring to Figures 12 to 12B , the silicon nitride-containing materials 46 and 36 Figures 11 to 11B are removed with hot phosphoric acid etching, and the silicon nitride-containing material 66 of the second material liner 60 is recessed along the second side 53 of the trench 80. Thus, a void 90 is formed along an edge of the word line 84 adjacent the second side 53 of the trench 80.

[0062] Referring to Figures 13 to 13BAn insulative material 92 is formed within the trench 80 to cap the void 90. The insulative material 92 can comprise any suitable composition; and in some embodiments, can comprise, consist essentially of, or consist of silicon dioxide. The insulative material 92 can or can not extend to the uppermost surface of the word line 84. In the illustrated embodiment, a gap is maintained between the insulative material 92 and the top of the word line 84 to assist a reader in visualizing the region comprising the void 90.

[0063] A planarization surface 93 is formed extending across the materials 32, 40, 64, 78, and 92. The planarization surface 93 can be formed with any suitable process including, for example, CMP. Formation of the planarization surface 93 removes material 34 Figures 12 to 12B ) from the top of the source / drain regions 26 and 28.

[0064] Referring to Figures 14 to 14B A storage element 96 is formed in electrical coupling with the top electrode material 32, and coupled with the top source / drain regions 28 through the top electrode material 32. The storage element 96 can be any suitable device having at least two detectable states; and in some embodiments, can be, for example, a capacitor, a resistive memory device, a conductive bridging device, a phase change memory (PCM) device, a programmable metallization cell (PMC), etc. In the illustrated embodiment, the storage element 96 is a capacitor. Each of the capacitors has one node coupled with the top electrode material 32, and has another node coupled with a suitable reference voltage 97 (illustrated with a triangle). The reference voltage 97 can be, for example, ground, VCC / 2, etc.

[0065] The semiconductor material pillars 54 each include upper and lower source / drain regions 26, and a channel region 30 between such upper and lower source / drain regions. A word line (gate line) 84 can be considered to be operatively proximate the channel region 30, such that operation of the word line 84 can control current flow along the channel region 30 to control whether the source / drain regions 26 and 28 are coupled with one another. Specifically, a suitable voltage along one of the word lines 84 can induce an electric field within the associated channel region 30 to enable current flow within the channel region and thus couple the source / drain regions 26 and 28 with one another through the channel region. If the voltage is below a threshold suitable to induce a suitable electric field within the associated channel region, then current flow will not be induced and the source / drain regions will not be coupled with one another. In some embodiments, selective operation of a channel region by current flow along the associated word line can be referred to as a gated operation of the channel region, and the word line can be considered to be operated in a manner that gates the associated source / drain regions to be coupled with one another. A region of the word line that is operatively proximate the channel region 30 can be considered to be a gate, and corresponds to a region along Figure 14A the cross-section of the channel region 30.

[0066] Each of the semiconductor material pillars 54 can be considered to include a portion of an access transistor 98, where each of such access transistors includes an upper source / drain region 28, a lower source / drain region 26, a channel region 30 between the upper and lower source / drain regions, and a segment of a word line 84 associated with the channel region 30.

[0067] The storage elements 96 are coupled with the upper source / drain regions of the access transistors 98. Each storage element 96, along with the access transistor coupled with such storage element, can be considered to correspond to a memory cell 100 of a memory array 102. The memory array can be a DRAM array.

[0068] The memory array 102 can have a configuration of the type schematically illustrated in Figure 15 The memory array includes a series of word lines 84, indicated as word lines WL1-WL4, and includes a series of digit lines 16, indicated as digit lines DL1-DL4. The digit lines are coupled with sensing circuitry (e.g., sense amplifier circuitry) 104, and the word lines are coupled with driver circuitry (e.g., word line driver circuitry) 106. Each of the memory cells 100 is uniquely addressed by one of the word lines in conjunction with one of the digit lines.

[0069] Referring again to Figures 14 to 14B , the pillars 54 can be considered to be included in semiconductor material structures 108, each semiconductor material structure including a first source / drain region 26, a second source / drain region 28, and a channel region 30 between the first and second source / drain regions.

[0070] Each of the semiconductor material structures 108 includes a first side 107 and a second side 109 along a cross-section of Figure 14A , where the second side is in an opposing relationship to the first side.

[0071] A word line (e.g., conductive structure) 84 associated with the channel region 30 of a semiconductor material structure 108 is adjacent to the first side 107 of the semiconductor material structure, and is operatively proximate to the channel region 30 to gate control coupling of the first and second source / drain regions 26 and 28 through the channel region. For example, one of the semiconductor material structures 108 is labeled 108a in Figure 14A , and is associated with a word line 84 labeled 84a, such that the word line 84a is operatively proximate to the channel region 30 (i.e., the word line 84 is spaced apart from the channel region 30 by the electrostatically insulative material 78 corresponding to only the gate dielectric material). The word line 84a can be considered to be a first conductive structure along the first side 107 of the semiconductor material structure 108a.

[0072] The second conductive structure 84b is along a second side 109 of the semiconductor material structure 108a and is spaced apart from the second side 109 of the semiconductor material structure 84b by an intervening region 110 that includes the void 90. Thus, the second conductive structure 84b is not operatively proximate to the semiconductor material structure 108a, but is instead electrically isolated from this semiconductor material structure by the intervening void- containing region 110. In the illustrated embodiment, the intervening region 110 also includes the material 64. This material is directly against the second side 109 of the semiconductor material structure 108a, and thus is between the semiconductor material structure 108a and the void 90. As discussed above, in some embodiments, the material 64 can comprise carbon-doped silicon dioxide.

[0073] In some embodiments, the semiconductor material pillars 54 can be considered to be portions of the semiconductor structures 52 that extend upwardly from the digit lines 16. As shown in cross-section along Figure 14A and in plan view along Figure 14 , each of the word lines 84 can be considered to include a first side 121 and an opposite second side 123. The semiconductor structures along the first side 121 of the word line 84a can be considered to be a first set 130 of semiconductor structures, and the semiconductor structures along the second side 123 of the word line 84a can be considered to be a second set 132 of structures. The channel regions 30 of the first set 130 of semiconductor structures 52 are operatively proximate to the first side 121 of the word line 84a, as shown in Figure 14A . In contrast, the channel regions 30 within the second set of semiconductor structures 132 are spaced apart from the adjacent second side 123 of the word line 84a by an intervening region 110 that includes the void 90, as shown in Figure 14A .

[0074] In the illustrated embodiment of Figure 14A , the word lines 84 span the digit lines 16 and are spaced apart from the digit lines by intervening regions 140. Such intervening regions include insulative regions 142. The insulative regions include the material 66 (which can comprise silicon nitride) and the material 64 (which can comprise carbon-doped silicon dioxide); and in the illustrated embodiment, also include the material 62 (which can comprise silicon dioxide) over the material 66.

[0075] The digit lines 16 can be coupled with sensing circuitry 104 of the type previously described with respect to Figure 15 , and the word lines 84 can be coupled with driver circuitry 106 of the type previously described with respect to Figure 15 . Figure 14A Regions 104 and 106 supported by the base 12 and beneath the memory array 102 (specifically, beneath the memory cells 100, the word lines 84 and the digit lines 16) are shown.

[0076] In some embodiments, circuitry 104 and 106 can comprise logic (e.g., CMOS). Although circuitry 104 and 106 are shown below memory array 102, in other embodiments at least a portion of one or both of circuitry 104 and 106 can be in a location other than directly below memory array 102.

[0077] The assemblies and structures discussed above can be utilized within integrated circuits (where the term "integrated circuit" means an electronic circuit that is supported by a semiconductor substrate); and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and business machines, and can include multilayer, multichip modules. The electronic systems can be any that include a storage and / or a processing element, such as, for example, set top boxes, game consoles, lighting systems, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0078] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0079] The terms "dielectric" and "insulative" can be used to describe materials having insulative electrical properties. The terms are considered synonymous in the present disclosure. The term "dielectric" can be used in some instances and the term "insulative" (or "electrically insulative") in others can be used to provide linguistic variation within the present disclosure to simplify the premise within the following claims, rather than to indicate any significant chemical or electrical difference.

[0080] The terms "electrically connected" and "electrically coupled" can both be used in the present disclosure. The terms are considered synonymous. The use of one term over the other in some instances can be to provide linguistic variation within the present disclosure to simplify the premise within the following claims.

[0081] The particular orientations of the various embodiments in the figures are for purposes of illustration only and in some applications, embodiments can be rotated relative to the orientation shown. The description provided herein, and the following claims, relate to any structure that has the described relationship between the various features, regardless of the orientation of the structure in the figures.

[0082] Unless otherwise specified, the cross-sectional views of the accompanying drawings are taken along the plane which is indicated by the line 6-6 in the figures. The section line is shown as a long dashed line in the drawings.

[0083] When a structure is referred to as being "on," "adjacent," or "resisting" another structure, the structure can be directly on the other structure or there can also be intervening structures present. Conversely, when a structure is referred to as being "directly on," "directly adjacent," or "directly resisting" another structure, there are no intervening structures present. The terms "directly below," "directly above," and the like do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

[0084] A structure (e.g., a layer, material, etc.) can be referred to as "vertically extending" to indicate that the structure generally extends upward from an underlying base (e.g., a substrate). A vertically extending structure can or can not extend substantially orthogonally relative to an upper surface of the base.

[0085] Some embodiments include an integrated assembly having a semiconductor material structure having a first source / drain region, a second source / drain region, and a channel region between the first and second source / drain regions. The semiconductor material structure has a first side and an opposite second side. A first conductive structure is adjacent the first side and is operatively proximate the channel region to gate control coupling of the first and second source / drain regions through the channel region. A second conductive structure is adjacent the second side and is spaced apart from the second side by an intervening region including a void.

[0086] Some embodiments include an integrated memory having digit lines extending along a first direction and having semiconductor structures extending upward from the digit lines. The semiconductor structures include pillars. Each of the pillars has an upper source / drain region and a channel region below the upper source / drain region. The semiconductor structures include a lower source / drain region below the channel regions. The lower source / drain regions are coupled with the digit lines. Storage elements are coupled with the upper source / drain regions. Gate lines extend along a second direction that intersects the first direction. Each of the gate lines has a first side and an opposite second side. A first set of the semiconductor structures is along the first side of an associated one of the gate lines, and a second set of the semiconductor structures is along the second side of the associated one of the gate lines. Channel regions within the first set of the semiconductor structures are operatively proximate the adjacent first side of the associated one of the gate lines such that the associated one of the gate lines provides gate control of the channel regions within the first set of the semiconductor structures. Channel regions within the second set of the semiconductor structures are spaced apart from the adjacent second side of the associated one of the gate lines by an intervening region including a void.

[0087] Some embodiments include a method of forming an integrated assembly. Linear features are formed over a base. The linear features include digit lines and semiconductor material lines over the digit lines. The linear features extend along a first direction. Trenches are formed extending into the linear features. The trenches extend along a second direction that intersects the first direction. The trenches extend into the semiconductor material lines but do not damage the digit lines. The trenches pattern semiconductor material structures from the semiconductor material lines. The semiconductor material structures include semiconductor material pillars. The semiconductor material structures include upper source / drain regions at upper regions of the semiconductor material pillars, channel regions within the semiconductor material pillars and below the upper source / drain regions, and lower source / drain regions below the channel regions and coupled with the digit lines. First material liners are formed within the trenches. Second material liners are formed over the first material liners. The second material liners are recessed along a first side of the trenches without being recessed along an opposite second side of the trenches. Gate lines are formed within the trenches and over the recessed second material liners. After forming the gate lines, the second material liners are recessed along the second side of the trenches to form voids. The voids are capped.

[0088] In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific to structural or methodical features. It is to be understood that the claims are not limited to the specific features or arrangements described, since the apparatus disclosed herein is capable of other embodiments or of being practiced with other specific features. The claims are to be construed as including alternative language and should be interpreted in the context of the entire specification and not just the details of the description section.

Claims

1. An integrated assembly comprising: a semiconductor material structure having a first lower source / drain region, a second upper source / drain region, and a channel region between the first lower source / drain region and the second upper source / drain region; the semiconductor material structure having a first side and an opposite second side; a first conductive structure adjacent to the first side and in operative proximity to the channel region to gate control coupling of the first lower source / drain region and the second upper source / drain region through the channel region; and a second conductive structure adjacent to the second side and spaced apart from the second side by an intervening region including a void.

2. The integrated assembly of claim 1, wherein the semiconductor material of the semiconductor material structure comprises silicon.

3. The integrated assembly of claim 1, wherein the first lower source / drain region is coupled with a digit line, and wherein the second upper source / drain region is coupled with a storage element.

4. The integrated assembly of claim 3, wherein the storage element is a capacitor.

5. The integrated assembly of claim 1, wherein the intervening region includes carbon-doped silicon dioxide between the semiconductor material structure and the void.

6. The integrated assembly of claim 5, wherein a carbon concentration within the carbon-doped silicon dioxide is at least about 1 at%.

7. The integrated assembly of claim 5, wherein the carbon concentration within the carbon-doped silicon dioxide is at least about 5 at%.

8. The integrated assembly of claim 5, wherein the carbon concentration within the carbon-doped silicon dioxide is at least about 10 at%.

9. The integrated assembly of claim 1, wherein the first conductive structure is spaced apart from the first side only by an insulating material including silicon dioxide.

10. The integrated assembly of claim 1, wherein the first and second conductive structures each include a metal-containing region directly against a doped semiconductor- containing region.

11. An integrated memory comprising: a digit line extending along a first direction; a semiconductor structure extending upwardly from the digit line; the semiconductor structure including a pillar; each of the pillars having an upper source / drain region and a channel region below the upper region; the semiconductor structure including a lower source / drain region below the channel region; the lower source / drain region coupled with the digit line; a storage element coupled with the upper source / drain region; a gate line extending along a second direction intersecting the first direction; and a second conductive structure adjacent to the second side and spaced apart from the second side by an intervening region including a void. ​ Each of the gate lines has a first side and an opposite second side; a first set of the semiconductor structures is along the first side of an associated one of the gate lines, and a second set of the semiconductor structures is along the second side of the associated one of the gate lines; the channel regions within the first set of the semiconductor structures are operatively proximate the first side of the associated one of the gate lines, such that the associated one of the gate lines provides gated control of the channel regions within the first set of the semiconductor structures; the channel regions within the second set of the semiconductor structures are spaced from the second side of the associated one of the gate lines by intervening regions that include voids.

12. The integrated memory of claim 11, wherein upper regions of the voids are capped by insulative material.

13. The integrated memory of claim 12, wherein the insulative material comprises silicon dioxide.

14. The integrated memory of claim 11, wherein the intervening regions include carbon-doped silicon dioxide.

15. The integrated memory of claim 14, wherein the carbon-doped silicon dioxide within each of the intervening regions is directly against one of the pillars.

16. The integrated memory of claim 11, wherein each of the gate lines includes a metal-containing region directly against a doped-semiconductor-containing region.

17. The integrated memory of claim 11, wherein the gate lines span the digit lines and are spaced from the digit lines by intervening regions that include insulative regions comprising silicon nitride and carbon-doped silicon dioxide.

18. The integrated memory of claim 17, wherein the silicon nitride is over the carbon-doped silicon dioxide, and wherein the insulative regions further include silicon dioxide over the silicon nitride.

19. The integrated memory of claim 11, wherein the digit lines are coupled with sense amplifier circuitry; and wherein the sense amplifier circuitry is under the digit lines.

20. The integrated memory of claim 11, wherein the gate lines are coupled with driver circuitry; and wherein the driver circuitry is under the digit lines.

21. A method of forming an integrated assembly, comprising: forming linear features over a base; the linear features including digit lines and a linear arrangement of semiconductor material over the digit lines; the linear features extending along a first direction; forming trenches to extend into the linear features; the trenches extending along a second direction that intersects the first direction; the trenches being spaced from the linear features by intervening regions that include voids. The trench extends into the linear arrangement of semiconductor material without breaking the digit line; the trench patterns a semiconductor material structure from the linear arrangement of semiconductor material; the semiconductor material structure includes a semiconductor material pillar; the semiconductor material structure includes an upper source / drain region at an upper region of the semiconductor material pillar, a channel region within the semiconductor material pillar and below the upper source / drain region, and a lower source / drain region below the channel region and coupled with the digit line; forming a first material liner within the trench; forming a second material liner over the first material liner; recessing the second material liner along a first side of the trench without recessing the second material liner along an opposing second side of the trench; forming a gate line within the trench and over the recessed second material liner; after forming the gate line, recessing the second material liner along the second side of the trench to form a void; and capping the void.

22. The method of claim 21, wherein the first material liner comprises carbon-doped silicon dioxide.

23. The method of claim 22, wherein the second material liner comprises silicon nitride.

24. The method of claim 21, further comprising forming a storage element coupled with the upper source / drain region.

25. The method of claim 24, wherein the storage element is a capacitor.

26. The method of claim 21, wherein the recessing of the second material liner along the first side of the trench exposes regions of the first material liner; and the method further comprises removing the exposed regions of the first material liner and replacing the exposed regions with insulating material.

27. The method of claim 21, wherein the recessing of the second material liner along the first side of the trench exposes regions of the first material liner; wherein the first material liner comprises carbon-doped silicon dioxide; and the method further comprises oxidizing the exposed regions of the first material liner to convert the exposed regions to silicon dioxide.

28. The method of claim 21, wherein at least portions of the lower source / drain region are within portions of the semiconductor material structure that are below the pillar and that are not patterned into the pillar.

29. The method of claim 21, further comprising forming insulating material between the linear features, and forming the trench to extend into the insulating material and into the linear features.

30. The method of claim 29, wherein the linear features are spaced apart from one another by gaps, and the method further comprises forming linear-feature liners along the linear features and within the gaps; and wherein the forming the insulating material between the linear features comprises forming the insulating material over the linear-feature liners and within the gaps.

31. The method of claim 30, wherein the linear feature liner comprises the same material as the first material liner.

32. The method of claim 31, wherein the same material is carbon doped silicon dioxide.

33. The method of claim 21, wherein the capping the voids comprises capping the voids with silicon dioxide.

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