Alignment Metallization of Solar Cells

Abstract

The present disclosure provides an aligned metallization method for manufacturing a solar cell and the resulting solar cell. In a certain example, the solar cell includes a semiconductor layer above a semiconductor substrate. A first plurality of discrete openings are in the semiconductor layer and expose corresponding discrete portions of the semiconductor substrate. A plurality of doped regions are in the semiconductor substrate and correspond to the first plurality of discrete openings. An insulating layer is above the semiconductor layer and in the first plurality of discrete openings. A second plurality of discrete openings are in the insulating layer and expose corresponding portions of the plurality of doped regions. Each of the second plurality of discrete openings is completely within the periphery of a corresponding one of the first plurality of discrete openings. A plurality of conductive contacts are in the second plurality of discrete openings and on the plurality of doped regions.

Description

[0001] Cross-references to related patent applications

[0002] This application claims priority to U.S. Non-Provisional Application No. 17 / 116,472, filed on December 9, 2020, which claims the benefit of U.S. Provisional Application No. 62 / 946,396, filed on December 10, 2019, the entire contents of which are hereby incorporated by reference into this document. Technical Field

[0003] Embodiments of the present disclosure pertain to the field of renewable energy, and in particular, include aligned metallization methods for fabricating solar cells and the resulting solar cells. Background Art

[0004] Photovoltaic cells (often referred to as solar cells) are well-known devices for converting solar radiation directly into electrical energy. Generally speaking, solar cells are manufactured on semiconductor wafers or substrates using semiconductor processing techniques to form pn junctions near the surface of the substrate. Solar radiation that strikes the substrate surface and enters the substrate forms electron and hole pairs in the bulk of the substrate. These electron and hole pairs migrate to p-doped and n-doped regions in the substrate, thereby generating a voltage difference between the doped regions. The doped regions are connected to conductive regions on the solar cell to direct current from the cell to an external circuit coupled thereto. Electrical conversion efficiency is an important characteristic of solar cells because it is directly related to the ability of the solar cell to generate electricity; higher efficiency provides added value to the end customer; and, with all other conditions being equal, higher efficiency also reduces the manufacturing cost per watt. Similarly, simplified manufacturing methods provide opportunities to reduce manufacturing costs by reducing the unit cost of production. Therefore, technologies that improve the efficiency of solar cells and technologies that simplify the manufacture of solar cells are generally needed. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A cross-sectional view and corresponding plan view of a solar cell with alignment metallization according to an embodiment of the present disclosure are shown.

[0006] Figure 2A A plan view of an opening for forming a metallization structure of a solar cell according to another embodiment of the present disclosure is shown.

[0007] Figure 2B A plan view of a plurality of openings for forming a plurality of metallization structures of a solar cell according to another embodiment of the present disclosure is shown.

[0008] Figure 3 is a flowchart including various operations in a method of fabricating a solar cell with alignment metallization in accordance with an embodiment of the present disclosure.

[0009] Figure 4 is a flowchart including various operations in another method of fabricating a solar cell with alignment metallization in accordance with another embodiment of the present disclosure.

[0010] FIG. 5A to FIG. 5E Cross-sectional views are shown representing various operations in a method of fabricating a solar cell with alignment metallization in accordance with an embodiment of the present disclosure.

[0011] Figure 6 Shown are plan views showing various alignment metallization structures for solar cells according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] The following specific embodiments are merely exemplary in nature and are not intended to limit the application and use of these embodiments or such embodiments. As used herein, the word "exemplary" means "used as an example, instance or illustration". Any embodiment described herein as exemplary is not necessarily preferred or advantageous over other embodiments. In addition, it is not intended to be bound by any express or implied theory presented in the aforementioned technical field, background technology, summary of the invention or the following specific embodiments.

[0013] References to "one embodiment" or "an embodiment" are not necessarily to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0014] Terminology. The following paragraphs provide definitions and / or context for terms found in this disclosure, including the appended claims:

[0015] “Comprising” is an open term and does not exclude other structures or steps.

[0016] "Configured to" refers to a structure by indicating a device, such as a unit or component, including a structure that performs one or more tasks during operation, and such structure is configured to perform the task even if the device is not currently in operation (e.g., not turned on / activated). A device "configured to" perform one or more tasks is expressly intended not to invoke the interpretation of 35 U.S.C. §112, paragraph (f) (i.e., the sixth paragraph) as a method or step plus function.

[0017] The terms "first", "second", etc. are used as labels for the nouns that follow them and do not imply any type of order (e.g., spatial, temporal, logical, etc.). For example, referring to a "first" solar cell does not necessarily mean that such a solar cell is in a certain sequence; rather, the term "first" is used to distinguish the solar cell from another solar cell (e.g., a "second" solar cell).

[0018] Unless expressly stated otherwise, "coupled" means that an element, feature, structure, or node is or can be joined or communicated with another element / node / feature, either directly or indirectly, and not necessarily directly mechanically.

[0019] "Prevent" means to reduce, diminish, minimize, or effectively or physically eliminate something, such as to completely avoid an outcome, consequence, or future state.

[0020] "Doped regions," "semiconductor regions," and similar terms describe semiconductor regions disposed in, on, over, or above a substrate. Such regions may have N-type conductivity or P-type conductivity and may vary in doping concentration. Such regions may refer to multiple regions, such as a first doped region, a second doped region, a first semiconductor region, a second semiconductor region, and the like. These regions may be formed of polysilicon on the substrate or as part of the substrate itself.

[0021] "Thin dielectric layer", "tunnel dielectric layer", "dielectric layer", "thin dielectric material" or intermediate layer / material refers to a material located on a semiconductor region, between a substrate and another semiconductor layer, between doped regions or semiconductor regions on or in a substrate. In a certain embodiment, the thin dielectric layer can be a tunnel oxide layer or nitride layer having a thickness of about 2 nanometers or less. The thin dielectric layer can be referred to as a very thin dielectric layer through which electrical conduction can be achieved. The conduction can be due to quantum tunneling and / or the presence of small regions that are directly physically connected through thin points in the dielectric layer. Exemplary materials include silicon oxide, silicon dioxide, silicon nitride, and other dielectric materials.

[0022] An "intermediate layer" or "insulating layer" describes a layer that provides electrical insulation, passivation, and blocks light reflectivity. The intermediate layer can be a multilayer, such as a stack of intermediate layers. In some cases, the insulating layer can be interchanged with a tunneling dielectric layer, while in other cases, the insulating layer is a masking layer or an "anti-reflective coating" (ARC layer). Exemplary materials include silicon nitride, silicon oxynitride, silicon dioxide, aluminum oxide, amorphous silicon, polycrystalline silicon, molybdenum oxide, tungsten oxide, indium tin oxide, tin oxide, vanadium oxide, titanium oxide, silicon carbide, and other materials. In a certain example, the intermediate layer may include a material that can act as a moisture barrier. In addition, for example, the insulating material can be a passivation layer of a solar cell.

[0023] "Substrate" may refer to, but is not limited to, a semiconductor substrate such as silicon, and specifically, such as a monocrystalline silicon substrate, a polycrystalline silicon substrate, a wafer, a silicon wafer, and other semiconductor substrates for solar cells. In a certain example, such substrates may be used in microelectronic devices, photovoltaic cells or solar cells, diodes, photodiodes, printed circuit boards, and other devices. These terms are used interchangeably herein.

[0024] "About" or "approximately." As used herein, with respect to recited values, including, for example, integers, fractions, and / or percentages, the term "about" or "approximately" generally indicates that the recited value encompasses a range of values ​​(e.g., + / - 5% to 10% of the recited value) that one of ordinary skill in the art would consider equivalent to the recited value (e.g., performing substantially the same function, acting in substantially the same manner and / or having substantially the same results).

[0025] In addition, certain terms may be used in the following description for reference purposes only, and therefore, these terms are not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings for which reference is provided. Terms such as "front," "back," "rear," "side," "outer," and "inner" describe the orientation and / or position of certain portions of a component within a consistent but arbitrary reference system, which orientation and / or position can be clearly understood by reference to the text describing the component in question and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0026] Aligned metallization methods for manufacturing solar cells and the resulting solar cells are described herein. In the following description, many specific details such as specific process flow operations are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other examples, well-known manufacturing techniques, such as lithography and patterning techniques, are not described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure. In addition, it should be understood that the various embodiments shown in the figures are exemplary displays and are not necessarily drawn to scale.

[0027] The present invention discloses a solar cell. In one embodiment, the solar cell includes a semiconductor layer above a semiconductor substrate. A first plurality of discrete openings are in the semiconductor layer and expose corresponding discrete portions of the semiconductor substrate. A plurality of doped regions are in the semiconductor substrate and correspond to the first plurality of discrete openings. An insulating layer is above the semiconductor layer and in the first plurality of discrete openings. A second plurality of discrete openings are in the insulating layer and expose corresponding portions of the plurality of doped regions. Each of the second plurality of discrete openings is completely within the perimeter of a corresponding one of the first plurality of discrete openings. A plurality of conductive contacts are in the second plurality of discrete openings and on the plurality of doped regions.

[0028] Also disclosed herein is a method of manufacturing a solar cell. In one embodiment, the method of manufacturing a solar cell includes forming a first plurality of discrete openings in a semiconductor layer above a substrate. The method also includes forming an insulating layer in the first plurality of discrete openings. The method also includes forming a second plurality of discrete openings in the insulating layer using a laser ablation process. Each of the second plurality of discrete openings is completely within the perimeter of a corresponding one of the first plurality of discrete openings.

[0029] In a certain embodiment, a method for manufacturing a solar cell includes forming a semiconductor layer above a semiconductor substrate. The method also includes forming an insulating layer above the semiconductor layer. The method also includes forming a first plurality of discrete openings in the insulating layer and in the semiconductor layer, the first plurality of discrete openings exposing corresponding discrete portions of the semiconductor substrate. The method also includes forming a doping source layer above the insulating layer and in the first plurality of discrete openings. The method also includes forming a plurality of doping regions corresponding to the first plurality of discrete openings in the semiconductor substrate, the plurality of doping regions being formed by the doping source layer. The method also includes forming a second plurality of discrete openings in the doping source layer using a laser ablation process, each of the second plurality of discrete openings being completely within the periphery of a corresponding one of the first plurality of discrete openings. The method also includes forming a plurality of conductive contacts in the second plurality of discrete openings and on the plurality of doping regions.

[0030] Thus, one or more embodiments described herein may be implemented to provide methods and architectures for high efficiency and low cost solar cells with maximized high lifetime passivation area by precisely aligning conductive vias over spatially confined emitter regions. According to embodiments, the aligned metallization structures may be used to fabricate conductive contacts for interdigitated back contact (IBC) solar cell architectures.

[0031] To provide context, in a first aspect, the most advanced approach to reduce the total number of process operations but maintain high cell efficiency is to place a lower lifetime P-type polysilicon layer (P-poly) on top of an N-type polycrystalline layer (N-poly) for a very limited area by using screen printing or selective laser ablation mask processes. In such an architecture, there is no restriction to have the P+ emitter region in continuous contact with the silicon (Si) substrate. A selective laser ablation mask process is used for the P-poly (or lower lifetime polarity emitter) to minimize the P-poly coverage. Contact formation involves laser ablation, and since the metal layer needs to have a certain large area coverage for maximum current collection, there may be an associated risk of current leakage (or shunting) between the P-finger metal and the N-poly under the P-poly. This is particularly true around the area that is hit by the laser during the contact formation process.

[0032] On the second side, the most advanced approach to reduce the total number of process operations but maintain high cell efficiency is to combine a low lifetime p++ c-Si emitter region with a high lifetime N-poly emitter (by reducing the p+ area as much as possible, ideally to less than 2% wafer coverage). Since this approach may involve the use of screen printing or inkjet printing, it is difficult to achieve wafer coverage less than 8%, which may limit the achievable cell efficiency of such an architecture.

[0033] According to one or more embodiments of the present disclosure, a high-efficiency solar cell with a spatially confined emitter region and spatially aligned conductive holes is described. Such a structure can be manufactured by depositing or manufacturing a first emitter region (e.g., N+ polysilicon) with excellent surface passivation, and then depositing an insulating (e.g., SiNx, SiOx, and SiONx) layer. Selective removal of the first emitter from a spatially confined area (e.g., a row of dots, squares, or rectangles) can then be performed, with a total area coverage of less than 2% of the wafer. In one example, although dots, squares, or rectangles are disclosed, any shape can be used, such as a rectangle, triangle, trapezoid, polygon, ellipse, and / or any other type of shape can be used. The single dimension (diameter or length) of each feature can be, for example, less than 100 μm. In some examples, the single dimension (diameter or length) of each feature can be, for example, less than 150 μm. A second emitter region (e.g., a P+ region in a silicon substrate) can then be manufactured by forming a doped layer at the location where the first emitter region is removed and then driving dopants from the doped layer into the substrate. A second insulating dielectric layer (e.g., SiOx, SiNx, or SiONx) may be formed on top of the doped layer. Selective removal of portions of the second insulating layer is performed by aligning the second emitter polarity fingers directly on top of the spatially confined doped layer (and the doped "second emitter" region below), and aligning the first emitter polarity fingers directly on top of the first emitter. In one embodiment, the contact holes on the second emitter region are smaller than the size of the emitter region to avoid shunting between different polarities. In the examples described above, the first emitter region may include n+ polysilicon, wherein the second emitter region may include a p+ region in the silicon substrate. In another example, the first emitter region may include p+ polysilicon, wherein the second emitter region may include an n+ region in the silicon substrate.

[0034] As an exemplary structure, Figure 1 A cross-sectional view and corresponding plan view of a solar cell with alignment metallization according to an embodiment of the present disclosure are shown. The plan view is taken through axis 130, noting that structures 128 and 124 have been removed from the plan view in order to depict openings below structures 128 and 124.

[0035] refer to Figure 1, solar cell 100 includes substrate 102, such as a monocrystalline silicon substrate. Substrate 102 has a back side 104 and a front side 106, the front side 106 being opposite to the back side 104. In some embodiments, the front side 106 may be referred to as a front surface, and the back side 104 may be referred to as a back surface. In a certain embodiment, the front side may have a textured surface 107. The textured surface may be a surface having a regular or irregular shape, which is used to scatter incident light, reduce the amount of light reflected from the light receiving surface and / or exposed surface of the solar cell 100. An anti-reflective coating 108 may be conformal to the textured surface 107, as depicted.

[0036] Reference again Figure 1 , semiconductor layer 112 is above substrate 102. A first plurality of discrete openings 114 are in semiconductor layer 112 and expose corresponding discrete portions 103 of semiconductor substrate 102. A plurality of doped regions (shown as shaded 103) are in semiconductor substrate 102 and correspond to first plurality of discrete openings 114. Insulating layer 118 is above semiconductor layer 112 and in first plurality of discrete openings 114. A second plurality of discrete openings 122 are in insulating layer 118 and expose corresponding portions of the plurality of doped regions 103.

[0037] In a certain embodiment, as depicted, each of the second plurality of discrete openings 122 is within and / or completely within the perimeter of a corresponding one of the first plurality of discrete openings 114. A plurality of conductive contacts 124 are within the second plurality of discrete openings 122 and on the plurality of doped regions 103. Although a plurality of discrete openings are shown, in another embodiment, non-discrete openings may also be used and these embodiments are described below. Figure 6 Described in.

[0038] In certain embodiments, as depicted, the solar cell 100 further includes a third plurality of discrete openings 126 in the insulating layer 118. The third plurality of discrete openings 126 expose corresponding discrete portions of the semiconductor layer 112. The second plurality of conductive contacts 128 are in the third plurality of discrete openings 126 and on corresponding discrete portions of the semiconductor layer 112. In certain embodiments, as depicted, the plurality of conductive contacts 124 (and thus, along with the second plurality of discrete openings 122) are a first unidirectional conductive contact row. The second plurality of conductive contacts 128 (and thus, along with the third plurality of discrete openings 126) are a second unidirectional conductive contact row 128 parallel to the first unidirectional conductive contact row 124. It should be understood that the two rows of each row are in Figure 1 The plan views are shown as alternating.

[0039] In a certain embodiment, as depicted, semiconductor layer 112 is on thin dielectric layer 110 on substrate 102. A first plurality of discrete openings 114 are further in thin dielectric layer 110. In a certain example, thin dielectric layer 110 may be a thin oxide layer, such as a tunnel dielectric layer (e.g., tunnel oxide, silicon oxynitride, silicon oxide). In a certain embodiment, thin dielectric layer 110 may have a thickness of approximately 2 nanometers or less.

[0040] In one embodiment, the semiconductor layer 112 may be a polysilicon layer. In one embodiment, the semiconductor layer 112 may include a first conductivity type. In one example, the semiconductor layer 112 may be a first polysilicon layer of the first conductivity type.

[0041] In a specific embodiment, the first conductivity type is N-type (e.g., formed using phosphorus atoms or arsenic impurity atoms). In another specific embodiment, the first conductivity type is P-type (e.g., formed using boron impurity atoms). In some embodiments, the first semiconductor layer is a pre-doped polysilicon layer. In one such embodiment, a first semiconductor layer having a specific conductivity type (e.g., N-type or P-type) is formed.

[0042] In certain embodiments, the insulating layer 118 is a doping source layer. As depicted, the solar cell 100 further includes a second insulating layer 116 between the semiconductor layer 112 and the doping source layer (118). The first plurality of discrete openings 114 are further in the second insulating layer 116. In one such embodiment, as depicted, the solar cell 100 further includes an anti-reflective coating 120 over the doping source layer (118). The second plurality of discrete openings 114 are further in the anti-reflective coating 120. In certain examples, the anti-reflective coating 120 may include a silicon nitride layer.

[0043] In one embodiment, the doping source layer (118) may include a second conductivity type. In one embodiment, the doping source layer (118) is of a conductivity type opposite to that of the semiconductor layer 112. In one example, the doping source layer (118) is of a P type (e.g., formed using boron atoms). In another example, the doping source layer (118) is of an N type (e.g., formed using phosphorus atoms or arsenic impurity atoms).

[0044] In one embodiment, the semiconductor layer 112 has a first conductivity type, and the plurality of doped regions 103 have a second conductivity type opposite to the first conductivity type. In one such embodiment, the semiconductor layer 112 is N-type, and the plurality of doped regions 103 are P-type, providing Figure 1 In another embodiment, the semiconductor layer 112 is of P type and the plurality of doped regions 103 are of N type, and in one example, a PNPN arrangement is provided as a Figure 1 An alternative NPNP arrangement is shown.

[0045] In some embodiments, the conductive contacts 124 and 128 may include electroplated metals. In one example, the conductive contacts 124 and 128 may include electroplated copper, tin, titanium, tungsten, and / or nickel, among other metals.

[0046] In some embodiments, the conductive contacts 124 and 128 may include a deposited metal. In a certain embodiment, the deposited metal may be aluminum-based. In one such embodiment, the aluminum-based deposited metal may have a thickness in the range of approximately 0.3 microns to 20 microns, and include an aluminum content greater than about 97%, and a silicon content in the range of approximately 0% to 2%. In a certain example, the aluminum-based deposited metal may include copper, titanium, titanium tungsten, nickel and / or aluminum and other metals. In a certain embodiment, the aluminum-based deposited metal is formed by a blanket deposition process. In a certain embodiment, the aluminum-based deposited metal may be a metal seed layer. In some examples, the deposited metal may be deposited aluminum. In one embodiment, the conductive contacts as described herein may include copper, tin, nickel and / or aluminum and other metals.

[0047] In some embodiments, the conductive contacts 124 and 128 may include metal foil. In a certain example, the conductive contacts 124 and 128 may include aluminum or aluminum foil. In a certain embodiment, the metal foil is an aluminum (Al) foil having a thickness in the range of about 5 microns to 100 microns. In one embodiment, the Al foil is an aluminum alloy foil containing aluminum and a second element (such as but not limited to copper, manganese, silicon, magnesium, zinc, tin, lithium or a combination thereof). In one embodiment, the Al foil is a tempered grade foil, such as but not limited to F grade (free state), O grade (fully soft), H grade (strain hardened) or T grade (heat treated). In one embodiment, the aluminum foil is an anodized aluminum foil. In another embodiment, the aluminum foil is not anodized.

[0048] In some embodiments, the conductive contacts 124 and 128 may include conductive wires. In certain embodiments, the conductive wires may include a conductive material (e.g., a metal such as aluminum, copper, or another suitable conductive material, with or without a coating such as tin, silver, nickel, or an organic solderability preservative). In certain examples, the conductive wires may be bonded to the semiconductor layer by a thermocompression bonding, ultrasonic bonding, or thermosonic bonding process. In one example, the conductive wires may be bonded to a metal seed or metal paste material on the semiconductor region.

[0049] In certain embodiments, each of the first plurality of discrete openings 114 is approximately circular, and each of the second plurality of discrete openings 122 is approximately circular, such as Figure 1 Floor plan and Figure 2A Depicted, among which Figure 2AA plan view of an opening for forming a metallization structure of a solar cell according to another embodiment of the present disclosure is shown.

[0050] However, it should be understood that the shape of the openings of one or both of the first plurality of discrete openings 114 and the second plurality of discrete openings 122 need not be circular. The shape of the openings of one or both of the first plurality of discrete openings 114 and the second plurality of discrete openings 122 can be any shape, as long as the overall small area and alignment requirements (e.g., the second opening is within and / or completely within the first opening) are met. In a certain example, the shape of the openings of one or both of the first plurality of discrete openings 114 and the second plurality of discrete openings 122 can be square, rectangular, oval, etc.

[0051] In one embodiment, one or more of the second plurality of discrete openings 122 are centered within the perimeter of a corresponding one or more of the first plurality of discrete openings 114, such as Figure 1 Floor plan and Figure 2A However, in another embodiment, one or more of the second plurality of discrete openings 122 are offset from the center within the perimeter of a corresponding one or more of the first plurality of discrete openings 114. As an example, Figure 2B FIG. 1 is a plan view showing a plurality of openings for forming a plurality of metallization structures of a solar cell according to another embodiment of the present disclosure. Figure 2B , the left and right columns of openings 252 are off-center, but still acceptable because the second plurality of discrete openings 122 are completely within the perimeter of a corresponding one or more of the first plurality of discrete openings 114. The left column of openings 252 is slightly off-center, while the right column of openings 252 is even more off-center. On the other hand, opening column 254 is unacceptable because the bottom discrete openings 262 are not completely within the perimeter of the corresponding discrete openings 114.

[0052] Figure 3 is a flowchart including various operations in a method of fabricating a solar cell with alignment metallization in accordance with an embodiment of the present disclosure.

[0053] refer to Figure 3 In the flowchart 300 of the embodiment of the present invention, at operation 302, a semiconductor layer is formed over a substrate. In one embodiment, the semiconductor layer may be a polysilicon layer. In one example, the semiconductor layer may be a P-type or N-type polysilicon layer.

[0054] In one embodiment, at operation 304, a first plurality of emitter regions are formed in portions of the semiconductor layer and a second plurality of emitter regions are formed in portions of the substrate, the second plurality of emitter regions being formed in a plurality of discrete openings in the semiconductor layer. In one embodiment, the first plurality of emitter regions may include doped regions in the semiconductor layer. In one embodiment, the second plurality of emitter regions may include doped regions in the substrate. In one embodiment, the plurality of discrete openings in the semiconductor layer are formed using a laser ablation process, which may be followed by an etching process. In one embodiment, the first plurality of discrete openings are formed using a screen printing etching process.

[0055] In one embodiment, at operation 306, a plurality of discrete openings are formed in an insulating layer disposed over the substrate, the plurality of discrete openings being formed over the first plurality and the second plurality of emitter regions. In a certain embodiment, the plurality of discrete openings in the insulating layer formed over the second plurality of emitter regions are formed entirely within the plurality of discrete openings in the semiconductor layer (e.g., starting from operation 304). In a certain embodiment, the plurality of discrete openings in the insulating layer formed over the second plurality of emitter regions are formed entirely within a perimeter of a corresponding one of the plurality of discrete openings in the semiconductor layer. In one embodiment, at operation 306, forming the plurality of discrete openings in the insulating layer includes forming one or more of the plurality of discrete openings centered within a perimeter of a corresponding one or more of the plurality of discrete openings in the semiconductor layer. In one embodiment, at operation 306, forming the plurality of discrete openings in the insulating layer includes forming one or more of the plurality of discrete openings in the insulating layer off-center within a perimeter of a corresponding one or more of the plurality of discrete openings. Figure 4 FIG. 1 is a flow chart including various operations in another method of manufacturing a solar cell with alignment metallization according to another embodiment of the present disclosure. Figure 4 In a flowchart 400 of the present invention, at operation 402, a semiconductor layer is formed above a semiconductor substrate. At operation 404, an insulating layer is formed above the semiconductor layer. At operation 406, a first plurality of discrete openings are formed in the insulating layer and in the semiconductor layer. The first plurality of discrete openings expose corresponding discrete portions of the semiconductor substrate. At operation 408, a doping source layer is formed above the insulating layer and in the first plurality of discrete openings. At operation 410, a plurality of doping regions corresponding to the first plurality of discrete openings are formed in the semiconductor substrate. The plurality of doping regions may be formed by the doping source layer. At operation 412, a second plurality of discrete openings are formed in the doping source layer using a laser ablation process. At operation 414, a plurality of conductive contacts are formed in the second plurality of discrete openings and on the plurality of doping regions.

[0056] In one embodiment, before, after, or simultaneously with performing operation 414, the method further includes forming a third plurality of discrete openings in the doping source layer and the insulating layer. The third plurality of discrete openings expose corresponding discrete portions of the semiconductor layer. A second plurality of conductive contacts are formed in the third plurality of discrete openings and on corresponding discrete portions of the semiconductor layer.

[0057] In one embodiment, at operation 406, the first plurality of discrete openings are formed using a laser ablation process, which may be followed by an etching process. In one embodiment, at operation 406, the first plurality of discrete openings are formed using a screen printing etching process.

[0058] In one embodiment, at operation 414, each of the second plurality of discrete openings is formed entirely within a perimeter of a corresponding one of the first plurality of discrete openings. In one embodiment, at operation 414, forming the second plurality of discrete openings includes forming one or more of the second plurality of discrete openings centered within a perimeter of a corresponding one or more of the first plurality of discrete openings. In one embodiment, at operation 414, forming the second plurality of discrete openings includes forming one or more of the second plurality of discrete openings off-center within a perimeter of a corresponding one or more of the first plurality of discrete openings.

[0059] As including by the above combination Figure 3 and / or Figure 4 An exemplary processing scheme for a combination of operations described, FIG. 5A to FIG. 5E Cross-sectional views representing various operations in a method of fabricating a solar cell with alignment metallization are illustrated in accordance with an embodiment of the present disclosure.

[0060] refer to Figure 5A , the startup structure 500 includes a semiconductor substrate 502, such as a single crystal silicon substrate. The substrate 502 has a back side 504 and a front side 506, the front side 506 being opposite to the back side 504. In some embodiments, the front side 506 may be referred to as a front surface, and the back side 504 may be referred to as a back surface. In a certain embodiment, the front side may have a textured surface 507. The textured surface 507 may be a surface having a regular or irregular shape, which is used to scatter incident light, reduce the amount of light reflected from the light receiving surface and / or exposed surface of the solar cell. The anti-reflective coating 508 may be conformal to the textured surface 107, as depicted.

[0061] Semiconductor layer 512 is formed over semiconductor substrate 502. Insulating layer 514 is formed over semiconductor layer 512. In one embodiment, thin dielectric layer 510 is formed over semiconductor substrate 502, and semiconductor layer 512 is formed over thin dielectric layer 510, as depicted.

[0062] In a certain embodiment, the textured surface 507 is formed using a texturing process performed on the front side of the substrate. In a certain example, a textured surface can be formed on the front side of the substrate using a hydroxide-based wet etchant. However, it should be understood that the texturing of the front side can be omitted from the process flow. In a certain embodiment, the substrate can be cleaned, polished, flattened and / or thinned before or within the same or single process operation of the texturing process. In a certain example, a wet chemical cleaning process can be performed before and / or after the texturing process. Although the texturing process can be performed at the beginning of the manufacturing process, in another embodiment, the texturing process can be performed in another operation of the manufacturing process. In a certain example, the texturing process can be performed alternatively after the patterning process. In one example, the texturing process can be performed before the thermal process. In one such example, the texturing process can be performed after patterning (e.g., patterning of polysilicon regions) and before the thermal process. In a certain embodiment, the thin dielectric layer 510 can be formed during the oxidation process and is a thin oxide layer, such as a tunnel dielectric layer (e.g., silicon oxide). In one embodiment, the thin dielectric layer 510 may be formed in a deposition process. In one embodiment, the thin dielectric layer 510 is a thin oxide layer or a silicon oxynitride layer. In one embodiment, forming the thin dielectric layer 510 may include forming the thin dielectric layer 510 to a thickness of about 2 nanometers or less. In one example, the thin dielectric layer 510 may be grown using a thermal process or an oven.

[0063] In a certain embodiment, forming the semiconductor layer 512 may include forming a polycrystalline silicon layer. In a certain embodiment, forming the semiconductor layer 512 may include forming a silicon layer on the thin dielectric layer 510. In a certain example, forming the silicon layer may include growing an N-type silicon layer above the thin dielectric layer 510. In other embodiments, the silicon layer may be a P-type silicon layer. In a certain embodiment, the silicon layer is an amorphous silicon layer. In one such embodiment, the amorphous silicon layer is formed using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). In a certain embodiment, the silicon layer may be polycrystalline silicon. In a certain embodiment, the silicon layer is grown on the thin dielectric layer 510 in a thermal process and / or oven. In one embodiment, the thin dielectric layer 510 and the silicon layer may be grown in the same or a single oven and / or in the same or a single process operation. In another embodiment, the silicon layer may be formed without doping. In one such embodiment, a dopant layer may be formed on the silicon layer, and a thermal process may be performed to drive dopants from the dopant layer into the silicon layer, thereby producing a silicon layer having a second conductivity type (eg, P-type or N-type).

[0064] refer to Figure 5B, first discrete openings 516 are formed in insulating layer 514, in semiconductor layer 512, and, if included, in thin dielectric layer 510. First discrete openings 516 expose corresponding discrete portions of semiconductor substrate 502. In certain embodiments, first discrete openings 516 have a diameter of, for example, less than 70 μm.

[0065] In certain embodiments, a laser ablation process (e.g., direct writing) may be used to form the first discrete openings 516. In certain examples, pulsed (fs-ps range) laser ablation of the insulating layer 514 is performed using a laser with a pulse duration between 10s to 15s and 10s to 7s, wherein the laser wavelength is between 248nm to 535nm, followed by selective etching of the semiconductor layer 512. In certain embodiments, a photolithography or screen / inkjet printing mask and a subsequent etching process may be used to form the first discrete openings 516. In certain examples, a mask may be formed, and a subsequent wet chemical etching process may be performed to form the contact openings. In some embodiments, a wet chemical cleaning process may be performed to remove the mask. In certain embodiments, any other photolithography process may be used, such as an inkjet process, etc. In one embodiment, a combination of a laser ablation process, photolithography (e.g., screen printing), and an etching process may be performed to form the first discrete openings 516. In certain examples, forming the first discrete openings 516 may include performing a laser ablation process and an etching process (e.g., a mask and a wet etching process).

[0066] refer to Figure 5C , a doping source layer 524 is formed over the insulating layer 514 and in the first discrete openings 516. Doped regions may be formed in the semiconductor substrate 502 in the areas corresponding to the first discrete openings 516. In one such embodiment, the doped regions are formed by the doping source layer 524. In a certain embodiment, as depicted, an anti-reflective coating 526 is formed over the doping source layer 524.

[0067] In one embodiment, a thermal process may be performed to drive dopants from the doping source layer 524 to the substrate 502, thereby forming a doped region in an area of ​​the semiconductor substrate 502. In one embodiment, the conductivity type of the dopant is N-type, for example, the dopant is a boron-containing dopant. In one example, the thermal process may include heating to a temperature of about or greater than 900 degrees Celsius to drive the dopant from the doping source layer 524 to a portion of the substrate 502.

[0068] refer to Figure 5D, second discrete openings 528 are formed in the doping source layer 524 and, if included, in the anti-reflective coating 526. In one embodiment, the second discrete openings 528 are formed using a laser ablation process. In some embodiments, the second discrete openings 528 are formed using a laser ablation process and an etching process. In a certain embodiment, before, after, or simultaneously with the formation of the second discrete openings 528, third discrete openings 530 are formed in the doping source layer 524 and in the insulating layer 514 and, if included, in the anti-reflective coating 526. The third discrete openings 530 expose corresponding discrete portions of the semiconductor layer 512.

[0069] In one example, the diameter of the second discrete openings 528 is less than 30 μm. In another example, the diameter of the second discrete openings 528 is about half the diameter of the first discrete openings 516. In one embodiment, the second discrete openings are formed by first screen / inkjet printing a negative resist for contact holes, followed by pulsed (fs-ps range) laser ablation performed using a laser with a pulse duration between 10s to 15s and 10s to 7s, and the laser wavelength is between 248nm and 535nm.

[0070] In some embodiments, the patterning processes used to form the second discrete openings 528 and the third discrete openings 530 may be performed in the same or a single operation (e.g., using lasers in the same or a single laser processing chamber), or alternatively may be performed separately (e.g., separate laser patterning processes may be used to form contact openings in the first insulating layer and the second insulating layer).

[0071] In certain embodiments, the doping source layer 524 and the anti-reflective coating 526 may be configured to be highly absorptive above the opening 516 and highly reflective above the region outside the opening 516 (e.g., above the semiconductor layer 512) for a particular laser wavelength. In certain examples, for a green laser (e.g., approximately 532 nm wavelength), the film material (e.g., the doping source layer 524 and / or the anti-reflective coating 526) may be approximately 800 angstroms above the opening 516 and approximately 1300 angstroms above the semiconductor layer 512. In one example, for a film material including an oxynitride stack, the reflectivity minimum may be near 532 nm on a P-type contact (e.g., above the opening 516), and the reflectivity maximum is on an N-type contact (e.g., above the semiconductor layer 512). In the same instance, this can result in the N-type contact process (e.g., above semiconductor layer 512) requiring higher laser power and the P-type contact process (e.g., above opening 516) requiring lower laser power, where a stray P contact (e.g., above opening 516) that falls in the N-finger region (e.g., above semiconductor layer 512) will not be able to open a contact on the higher reflective film.

[0072] refer to Figure 5E , first conductive contacts 538 are formed in second discrete openings 528 and, if included, on corresponding doped regions of substrate 502 exposed by discrete openings 528. In one such embodiment, as depicted, first conductive contacts 538 are further formed in first discrete openings 516. In a certain embodiment, second conductive contacts 540 are formed in third discrete openings 530 and on corresponding exposed discrete portions of semiconductor layer 512, also as depicted.

[0073] In a certain embodiment, forming the first conductive contact 538 and the second conductive contact 540 may include performing a sputtering process, locally depositing a metal, a blanket deposition process, a plating process, bonding a metal foil and / or a bonding wire to the first semiconductor layer and the second semiconductor layer. In a certain example, the first conductive contact 538 and the second conductive contact 540 may include locally deposited aluminum, aluminum foil and / or aluminum wire. In a certain embodiment, the first conductive contact 538 and the second conductive contact 540 may include one or more metals and / or metal alloys. In a certain example, the first conductive contact 538 and the second conductive contact 540 may include aluminum, titanium tungsten and / or copper and other metals. In a certain embodiment, the first conductive contact 538 and the second conductive contact 540 may include one, two or more metal layers. In a certain example, the first conductive contact 538 and the second conductive contact 540 may include a metal seed layer. In a certain embodiment, the metal seed layer may include a first layer, a second layer and a third layer, wherein the first layer includes copper, the second layer includes tungsten, and the third layer includes aluminum.

[0074] In a certain embodiment, a hot pressing process may be used to electrically connect the first conductive contact structure 538 to the second conductive contact 540. In a certain example, a hot pressing process may be used to adhere one or more wires. In one embodiment, the first conductive contact 538 and the second conductive contact 540 include bonded or welded metal foils. In a certain embodiment, forming the first conductive contact 538 and the second conductive contact 540 may include performing a blanket deposition process. In a certain example, forming the first conductive contact 538 and the second conductive contact 540 may include performing an electroplating process. In some examples, forming the first conductive contact 538 and the second conductive contact 540 may include performing a blanket deposition process to form a metal seed layer, followed by plating metal and performing a patterning process to form the first conductive contact 538 and the second conductive contact 540. In a certain example, forming the first conductive contact 538 and the second conductive contact 540 using a plating process may include placing the substrate in a bath to plate the metal to the substrate and forming the first conductive contact and the second conductive contact. In another embodiment, the first conductive contact 538 and the second conductive contact 540 may be formed in one process operation using a localized metal deposition process.

[0075] Although certain materials are specifically described with reference to the above embodiments, in such embodiments, other materials can be easily replaced with some of the materials, and these embodiments are still within the spirit and scope of the embodiments of the present disclosure. For example, in a certain embodiment, a substrate of a different material, such as a substrate of a III-V material, can be used instead of a silicon substrate. In addition, although the back contact solar cell arrangement is mainly mentioned, it should be understood that the methods described herein can also be applied to front contact electrode solar cells. In other embodiments, the above methods can be applicable to the manufacture of things other than solar cells. For example, the manufacture of light emitting diodes (LEDs) can benefit from the methods described herein. In addition, it is to be understood that in the case of specific descriptions of N+ type and P+ type doping, other embodiments envisioned include respectively opposite conductivity types, for example, P+ type and N+ type doping.

[0076] Thus, an aligned metallization method for making solar cells and the resulting solar cells have been disclosed.The above structures and techniques can be readily applied to solar cell products such as solar cell strings, photovoltaic (PV) laminates, and photovoltaic (PV) modules.

[0077] Although specific embodiments have been described above, even if only a single embodiment is described with respect to a particular feature, these embodiments are not intended to limit the scope of the present disclosure. Unless otherwise specified, the examples of features provided in the present disclosure are intended to be illustrative rather than limiting. The above description is intended to cover those alternatives, modifications, and equivalents that will be apparent to those skilled in the art that have the beneficial effects of the present disclosure.

[0078] The scope of the present disclosure includes any feature or combination of features disclosed herein (expressly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be made for any such combination of features during the examination process of the present application (or an application claiming priority thereto). In particular, with reference to the attached claims, features from dependent claims may be combined with those of the independent claims, and features from corresponding independent claims may be combined in any appropriate manner, and not just in the specific forms enumerated in the attached claims.

[0079] The following examples relate to more embodiments. The various features of the different embodiments can be combined in various ways with some features included and other features excluded to suit various applications.

[0080] Example 1: A solar cell includes a semiconductor layer above a semiconductor substrate. A first plurality of discrete openings are in the semiconductor layer and expose corresponding discrete portions of the semiconductor substrate. A plurality of doped regions are in the semiconductor substrate and correspond to the first plurality of discrete openings. An insulating layer is above the semiconductor layer and in the first plurality of discrete openings.

[0081] A second plurality of discrete openings are in the insulating layer and expose corresponding portions of the plurality of doped regions. Each of the second plurality of discrete openings is completely within the perimeter of a corresponding one of the first plurality of discrete openings. A plurality of conductive contacts are in the second plurality of discrete openings and on the plurality of doped regions.

[0082] Exemplary Embodiment 2: The solar cell of Exemplary Embodiment 1, wherein each of the first plurality of discrete openings is approximately circular, and each of the second plurality of discrete openings is approximately circular.

[0083] Exemplary Embodiment 3: The solar cell of Exemplary Embodiment 1 or 2, wherein one or more of the second plurality of discrete openings are centered within a perimeter of a corresponding one or more of the first plurality of discrete openings.

[0084] Exemplary Embodiment 4: The solar cell of Exemplary Embodiment 1, 2, or 3, wherein one or more of the second plurality of discrete openings are off-center within a perimeter of a corresponding one or more of the first plurality of discrete openings.

[0085] Exemplary embodiment 5: According to the solar cell described in Exemplary Embodiment 1, 2, 3 or 4, the solar cell further includes: a third plurality of discrete openings and a second plurality of conductive contacts, the third plurality of discrete openings exposing corresponding discrete portions of the semiconductor layer in the insulating layer, and the second plurality of conductive contacts in the third plurality of discrete openings and on corresponding discrete portions of the semiconductor layer.

[0086] Example 6: The solar cell of Example 5, wherein the plurality of conductive contacts is a first unidirectional conductive contact row, and the second plurality of conductive contacts is a second unidirectional conductive contact row parallel to the first unidirectional conductive contact row.

[0087] Exemplary Embodiment 7: The solar cell of Exemplary Embodiment 1, 2, 3, 4, 5 or 6, wherein the semiconductor layer is on a thin dielectric layer on a substrate, and the first plurality of discrete openings are further in the thin dielectric layer.

[0088] Exemplary Embodiment 8: The solar cell according to Exemplary Embodiment 1, 2, 3, 4, 5, 6 or 7, wherein the insulating layer is a doping source layer, and the solar cell further includes a second insulating layer between the semiconductor layer and the doping source layer, wherein the first plurality of discrete openings are further in the second insulating layer.

[0089] Example 9: The solar cell according to Example 8, the solar cell further comprising an anti-reflective coating over the doping source layer, wherein the second plurality of discrete openings are further in the anti-reflective coating.

[0090] Exemplary embodiment 10: The solar cell according to exemplary embodiment 1, 2, 3, 4, 5, 6, 7, 8 or 9, wherein the semiconductor layer has a first conductivity type and the plurality of doped regions have a second conductivity type opposite to the first conductivity type.

[0091] Example embodiment 11: A method of manufacturing a solar cell includes forming a first plurality of discrete openings in a semiconductor layer above a substrate. The method also includes forming an insulating layer in the first plurality of discrete openings. The method also includes forming a second plurality of discrete openings in the insulating layer using a laser ablation process. Each of the second plurality of discrete openings is completely within the perimeter of a corresponding one of the first plurality of discrete openings.

[0092] Example Embodiment 12: The method of Example Embodiment 11, wherein forming the first plurality of discrete openings includes using a laser ablation process.

[0093] Example Embodiment 13: The method of Example Embodiment 11, wherein forming the first plurality of discrete openings comprises using a screen printing etching process.

[0094] Exemplary Embodiment 14: A method according to Exemplary Embodiment 11, 12 or 13, wherein forming a second plurality of discrete openings includes forming one or more of the second plurality of discrete openings, and one or more of the second plurality of discrete openings are centered within a perimeter of a corresponding one or more of the first plurality of discrete openings.

[0095] Exemplary embodiment 15: A method for manufacturing a solar cell includes forming a semiconductor layer above a semiconductor substrate. The method also includes forming an insulating layer above the semiconductor layer. The method also includes forming a first plurality of discrete openings in the insulating layer and in the semiconductor layer, the first plurality of discrete openings exposing corresponding discrete portions of the semiconductor substrate. The method also includes forming a doping source layer above the insulating layer and in the first plurality of discrete openings. The method also includes forming a plurality of doping regions corresponding to the first plurality of discrete openings in the semiconductor substrate, the plurality of doping regions being formed by the doping source layer. The method also includes forming a second plurality of discrete openings in the doping source layer using a laser ablation process, each of the second plurality of discrete openings being completely within the periphery of a corresponding one of the first plurality of discrete openings. The method also includes forming a plurality of conductive contacts in the second plurality of discrete openings and on the plurality of doping regions.

[0096] Exemplary Embodiment 16: The method of Exemplary Embodiment 15, wherein forming the first plurality of discrete openings comprises using a laser ablation process.

[0097] Exemplary Embodiment 17: The method of Exemplary Embodiment 15, wherein forming the first plurality of discrete openings comprises using a screen printing etching process.

[0098] Exemplary Embodiment 18: According to the method described in Exemplary Embodiment 15, 16 or 17, the method further includes forming a third plurality of discrete openings in the doping source layer and in the insulating layer to expose corresponding discrete portions of the semiconductor layer, and forming a second plurality of conductive contacts in the third plurality of discrete openings and on corresponding discrete portions of the semiconductor layer.

[0099] Exemplary Embodiment 19: A method according to Exemplary Embodiments 15, 16, 17 or 18, wherein forming a second plurality of discrete openings includes forming one or more of the second plurality of discrete openings, wherein one or more of the second plurality of discrete openings are centered within a perimeter of a corresponding one or more of the first plurality of discrete openings.

[0100] Exemplary Embodiment 20: A method according to Exemplary Embodiments 15, 16, 17, 18 or 19, wherein forming a second plurality of discrete openings includes forming one or more of the second plurality of discrete openings, one or more of the second plurality of discrete openings being offset from the center within a perimeter of a corresponding one or more of the first discrete openings.

[0101] Although an exemplary embodiment is provided above, another exemplary embodiment of the present disclosure is provided below.

[0102] In an embodiment, a solar cell includes a semiconductor layer above a semiconductor substrate. A continuous opening is in the semiconductor layer and exposes a corresponding continuous portion of the semiconductor substrate. A doped region may be in the semiconductor substrate and corresponds to the continuous opening. An insulating layer may be above the semiconductor layer and in the continuous opening. Other openings in the insulating layer may expose corresponding portions of the doped region. Each of these openings in the insulating layer may be completely within a corresponding perimeter in the continuous opening. A plurality of conductive contacts are in the continuous opening and on the doped region.

[0103] In some instances, the continuous opening may include non-discrete structures and / or openings. In some instances, the continuous opening may include openings of lines, rectangular shapes, overlapping circular or elliptical shapes, and other shapes. In some instances, the continuous opening may include an opening having an area at least twice the area of ​​a discrete opening (e.g., a discrete opening as described above). In some instances, the continuous opening may have no gaps and / or cover a majority of the doped region of the solar cell throughout. In some instances, the continuous opening may include discrete openings with overlapping portions, such as forming a continuous opening, the continuous opening includes a circle, a rectangle, a triangle, a trapezoid, a polygon, an ellipse and / or any other type of shape may be used, such as having overlapping portions.

[0104] A method of manufacturing a solar cell is also disclosed herein. In one embodiment, the method of manufacturing a solar cell includes forming a continuous opening in a semiconductor layer above a substrate. The method also includes forming an insulating layer in the continuous opening. The method also includes forming a plurality of discrete openings in the insulating layer using a laser ablation process. Each of the plurality of discrete openings is completely within a corresponding perimeter in the continuous opening.

[0105] refer to Figure 6 , plan views (a) to (d) show various alignment metallization structures for solar cells. For reference, Figure 6 (a) Yes Figure 1 A copy of the floor plan is provided for comparison. Figure 6 (b) to Figure 6 (d) shows an exemplary continuous opening, for example with Figure 1 and Figure 6 The discrete openings shown in (a) are contrasted, as described below.

[0106] refer to Figure 6 (a), showing a plurality of discrete openings 650. In one embodiment, Figure 6 (a) shows the Figure 1 Structures similar to the structures shown in the plan views, such as the same structures, in which like reference numerals refer to Figure 1 The same or similar components described in (e.g., with increments of +500 from 100s to 600s to indicate Figure 6 In one example, the first plurality of discrete openings 614 may correspond to Figure 1 In another example, the discrete portions / doped regions 603 within the first plurality of discrete openings 614 may correspond to Figure 1 Discrete portions / doped regions 103 of.

[0107] Reference again Figure 6(a), in certain embodiments, a single dimension of the discrete openings 614, such as the length 660 / diameter 662, may be approximately less than 150 μm. In one example, the length of one side 660 may be equal to the length of the other side 662. In another example, the length of the side 660 may be approximately greater than the length of the side 662. In yet another example, the length of the side 662 may be approximately greater than the length of the side 660. In certain examples, the length of the side 660 may be approximately less than 150 μm, while the length of the side 662 may be approximately less than 100 μm. In certain embodiments, the edge-to-edge distance 664 separating the discrete openings 614 may be approximately less than 100 μm. In some examples, the edge-to-edge distance 664 separating the discrete openings 614 may be approximately less than 100 μm and approximately greater than 50 μm. In certain embodiments, the distance 665 between one of the plurality of discrete openings 622 and another opening may be approximately less than 200 μm. In a certain embodiment, a distance 665 between one of the plurality of discrete openings 622 and another opening may be approximately less than 200 μm and approximately greater than 150 μm.

[0108] As discussed above and below, Figure 6 (b) to Figure 6 (d) shows Figure 1 and Figure 6 (a) wherein the same numbers and descriptions may refer to the same or similar structures, and wherein the structures described Figure 6 (b) to Figure 6 The structure in (d) can be compared with Figure 1 and Figure 6 The same or similar structures in (a) are used interchangeably.

[0109] refer to Figure 6 (b) shows an example of a first continuous opening 652. The first continuous opening 652 is in the semiconductor layer and exposes a corresponding discrete portion of the semiconductor substrate / doped region 603 of the semiconductor substrate (e.g., see Figure 1 112, 102). The insulating layer 618 and / or the anti-reflective layer 620 are above the semiconductor layer and in the first continuous opening 654. A plurality of discrete openings 622 are in the insulating layer 618 / anti-reflective layer 620 and expose corresponding portions of the doped regions 103. In a certain embodiment, a distance 665 between one of the plurality of discrete openings 622 and another opening may be approximately less than 200 μm. In a certain embodiment, a plurality of conductive contacts may be in the first continuous opening 652 and on the plurality of doped regions 603. In a certain embodiment, the first continuous opening may include a rectangular shape as shown, as well as other shapes such as a rectangle, a triangle, a trapezoid, a polygon, an ellipse, and / or any other type of shape.

[0110] refer to Figure 6(c) shows an example of a second continuous opening 654. In one embodiment, Figure 6 (c) shows the Figure 6 (b) is similar to the structure shown in FIG. 1 , for example, the same structure, wherein like reference numerals refer to Figure 6 (b) . In certain embodiments, the second continuous opening 654 may include a first plurality of discrete openings 614 having an overlap 670, for example, forming a second continuous opening 654. In certain embodiments, the first plurality of discrete openings 614 of the second continuous opening 654 may include circular, rectangular, square, etc. shaped openings (e.g., circular, rectangular, square, etc.) having an overlap 670. In certain embodiments, if the openings are discrete openings, the overlap 670 may include less than 50% of the total area. In certain embodiments, a plurality of conductive contacts may be in the second continuous opening 654 and on the plurality of doped regions 603.

[0111] refer to Figure 6 (d) shows an example of a third continuous opening 656. In one embodiment, Figure 6 (d) shows the Figure 6 (c) and Figure 6 (b) and similar structures, wherein similar reference numerals refer to Figure 6 (c) and Figure 6 (b) The same or similar elements described in. In one embodiment, the third continuous opening 656 is Figure 6 (c) is substantially similar to the second continuous opening 654, except that the plurality of openings 622 are spaced further apart. In one example, the third continuous opening 656 may include the first plurality of discrete openings 614 having overlapping portions 670, such as to form the third continuous opening 656. In one embodiment, the distance 667 between one of the plurality of discrete openings 622 and another opening may be approximately less than 400 μm. In one embodiment, the distance 667 between one of the plurality of discrete openings 622 and another opening may be approximately less than 400 μm and approximately greater than 200 μm. As shown, the third continuous opening 656 may include a portion 672 without one of the openings 622. In one example, the third continuous opening 656 may include a portion 672 without one of the openings 622. Figure 6 (c) compared to the second continuous opening 654, the portion 672 without the opening 622 may be located between the openings 622 at one of the plurality of discrete openings 614, such as Figure 6 (d) as shown.

[0112] use Figure 6 (a) to Figure 6 Advantages of such embodiments described in (d) may include improved carrier lifetime and reduced solar cell series resistance. Figure 6 (b) and Figure 6(d) Compared with Figure 6 The solar cell of the configuration shown in (a) may have an improved carrier lifetime because, in one example, Figure 6 (b) and Figure 6 (d) having fewer p+ doped regions in an n+ silicon substrate compared to similarly configured solar cells. Figure 6 Compared with the solar cell with the configuration shown in (c), Figure 6 The solar cell configured as shown in (a) can have reduced series resistance because, in one example, it has a smaller p+ contact area. Figure 6 (a) to Figure 6 One configuration of (d) may have advantages over another, but in examples, each configuration allows for a reduction in process operations for manufacturing a solar cell while maintaining high cell efficiency.

[0113] Such a configuration can combine a low lifetime p++ c-Si emitter region with a high lifetime N-poly emitter, in one example by tuning the p+ area to be as small as possible, ideally less than 2% of wafer coverage.

Claims

1. A solar cell, comprising: a semiconductor layer, the semiconductor layer being above the semiconductor substrate; a first plurality of discrete openings exposing corresponding discrete portions of the semiconductor substrate in the semiconductor layer, wherein all adjacent openings of the first plurality of discrete openings have an overlap; a plurality of doped regions, the plurality of doped regions corresponding to the first plurality of discrete openings in the semiconductor substrate; an insulating layer over the semiconductor layer and in the first plurality of discrete openings; a second plurality of discrete openings exposing corresponding portions of the plurality of doped regions in the insulating layer, each of the second plurality of discrete openings being completely within a perimeter of a corresponding one of the first plurality of discrete openings and completely outside a perimeter of two adjacent openings of the first plurality of discrete openings that overlap the corresponding one of the first plurality of discrete openings; as well as A plurality of conductive contacts are provided in the second plurality of discrete openings and on the plurality of doped regions.

2. The solar cell of claim 1, wherein each of the first plurality of discrete openings is approximately circular, and each of the second plurality of discrete openings is approximately circular.

3. The solar cell of claim 1, wherein one or more of the second plurality of discrete openings are centered within a perimeter of a corresponding one or more of the first plurality of discrete openings.

4. The solar cell of claim 1, wherein one or more of the second plurality of discrete openings are off-center within a perimeter of a corresponding one or more of the first plurality of discrete openings.

5. The solar cell according to claim 1, further comprising: a third plurality of discrete openings exposing corresponding discrete portions of the semiconductor layer in the insulating layer; as well as A second plurality of electrically conductive contacts are provided in the third plurality of discrete openings and on the corresponding discrete portions of the semiconductor layer.

6. The solar cell of claim 5, wherein the plurality of conductive contacts is a first unidirectional conductive contact row, and the second plurality of conductive contacts is a second unidirectional conductive contact row parallel to the first unidirectional conductive contact row.

7. The solar cell of claim 1, wherein the semiconductor layer is on a thin dielectric layer on the substrate, and the first plurality of discrete openings are further in the thin dielectric layer.

8. The solar cell according to claim 1, wherein the insulating layer is a doping source layer, and the solar cell further comprises: A second insulating layer is provided between the semiconductor layer and the doping source layer, wherein the first plurality of discrete openings are further provided in the second insulating layer.

9. The solar cell according to claim 8, further comprising: An antireflective coating is provided over the dopant source layer, wherein the second plurality of discrete openings are further in the antireflective coating. 10 . The solar cell according to claim 1 , wherein the semiconductor layer has a first conductivity type, and the plurality of doped regions have a second conductivity type opposite to the first conductivity type.

11. A method for manufacturing a solar cell, the method comprising: forming a semiconductor layer over a semiconductor substrate; forming an insulating layer over the semiconductor layer; forming a first plurality of discrete openings in the insulating layer and in the semiconductor layer, the first plurality of discrete openings exposing corresponding discrete portions of the semiconductor substrate, wherein all adjacent openings of the first plurality of discrete openings have an overlap; forming a dopant source layer over the insulating layer and in the first plurality of discrete openings; forming a plurality of doped regions in the semiconductor substrate corresponding to the first plurality of discrete openings, the plurality of doped regions being formed by the doping source layer; forming a second plurality of discrete openings in the dopant source layer using a laser ablation process, each of the second plurality of discrete openings being completely within a perimeter of a corresponding one of the first plurality of discrete openings and completely outside a perimeter of two adjacent openings of the first plurality of discrete openings that overlap the corresponding one of the first plurality of discrete openings; as well as A plurality of conductive contacts are formed in the second plurality of discrete openings and on the plurality of doped regions.

12. The method of claim 11, wherein forming the first plurality of discrete openings comprises using a laser ablation process.

13. The method of claim 11, wherein forming the first plurality of discrete openings comprises using a screen printing etching process.

14. The method according to claim 11, further comprising: forming a third plurality of discrete openings in the doping source layer and the insulating layer to expose corresponding discrete portions of the semiconductor layer; as well as A second plurality of electrically conductive contacts are formed in the third plurality of discrete openings and on the corresponding discrete portions of the semiconductor layer.

15. The method of claim 11, wherein forming the second plurality of discrete openings comprises forming one or more of the second plurality of discrete openings that are centered within a perimeter of a corresponding one or more of the first plurality of discrete openings.

16. The method of claim 11, wherein forming the second plurality of discrete openings comprises forming one or more of the second plurality of discrete openings, the one or more of the second plurality of discrete openings being off-center within a perimeter of a corresponding one or more of the first plurality of discrete openings.

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