WAT Test Structure and Method

Abstract

The present invention provides a WAT test structure and method. The WAT test structure includes: a plurality of three-region array units, where each three-region array unit includes an input region and an output region having a first doping type and a base region having a second doping type; the base region separates the input region from the output region, and there are different spacing sizes between the input regions and the output regions of the plurality of three-region array units; the input region receives a voltage input signal, and the output region outputs a voltage output signal; a plurality of voltage detection array units, where the voltage detection array units correspond to the three-region array units one by one, and the voltage detection array units receive the voltage output signal and output a corresponding current output signal according to the magnitude of the voltage output signal. By setting the input regions and the output regions with different spacing sizes, the present invention determines the number of three-region array units in which the PN junction has been turned on by applying the same voltage input signal and characterizes the depletion layer width range of the PN junction.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and particularly to a WAT test structure and method. Background Art

[0002] The PN junction is the basic structure of semiconductor devices. In the WAT (wafer acceptable test) for PN junctions, the performance of the PN junctions of semiconductor devices is generally measured from three dimensions, namely the forward conduction voltage drop, the reverse leakage current, and the reverse breakdown voltage.

[0003] Currently, for the PN junctions in devices, an important characteristic parameter affecting the above three dimensions is the depletion layer width. Especially when a reverse bias voltage is applied, the depletion layer width is of great significance for formulating design rules related to isolation in semiconductor circuit design. During the platform development stage, for PN junctions formed by different ion implantations, tests that can accurately characterize the depletion layer width will play an important role in research and development.

[0004] However, currently there is no WAT test structure that can directly characterize the depletion layer width of PN junctions. How to accurately characterize the depletion layer width of device PN junctions is of great significance for device development.

[0005] Therefore, it is necessary to propose a new WAT test structure and method to solve the above problems. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a WAT test structure and method for solving the problem that the WAT test structure in the prior art cannot accurately characterize the depletion layer width of PN junctions.

[0007] To achieve the above purpose and other related purposes, the present invention provides a WAT test structure, including:

[0008] A plurality of three-region array units, the three-region array unit includes an input region and an output region having a first doping type and a base region having a second doping type; the base region separates the input region from the output region, and there are different interval sizes between the input regions and the output regions of the plurality of three-region array units; the input region receives a voltage input signal, and the output region outputs a voltage output signal;

[0009] A plurality of voltage detection array units, the voltage detection array unit corresponds to the three-region array unit one by one, and the voltage detection array unit receives the voltage output signal and outputs a corresponding current output signal according to the magnitude of the voltage output signal.

[0010] As an alternative embodiment of the present invention, the first doping type is N-type and the second doping type is P-type, or the first doping type is P-type and the second doping type is N-type.

[0011] As an alternative embodiment of the present invention, the maximum value of the plurality of different spacer sizes is the maximum predicted value of the depletion layer width of the PN junction between the input region and the base region, and the minimum value of the plurality of different spacer sizes is the minimum predicted value of the depletion layer width of the PN junction between the input region and the base region.

[0012] As an alternative embodiment of the present invention, the number of the three-region array units is n, where n is an integer greater than 1, and the plurality of spacer sizes form an arithmetic sequence, and the common difference is the difference between the maximum predicted value and the minimum predicted value of the depletion layer width divided by n - 1.

[0013] As an alternative embodiment of the present invention, the voltage detection array unit is a MOS transistor, the source region and the drain region of the MOS transistor have the first doping type, and the plurality of MOS transistors correspond to the plurality of three-region array units one by one.

[0014] As an alternative embodiment of the present invention, the output region of the three-region array unit is connected to the gate of the MOS transistor, the input regions of the plurality of three-region array units are connected together as the total input terminal of the WAT test structure, the source regions of the plurality of MOS transistors are connected together as the total output terminal of the WAT test structure, and a MOS transistor input voltage is applied to the drain regions of the plurality of MOS transistors.

[0015] As an alternative embodiment of the present invention, the input region of the three-region array unit is connected to the drain region of the MOS transistor, and the input voltage of the total input terminal of the WAT test structure is simultaneously used as the MOS transistor input voltage.

[0016] As an alternative embodiment of the present invention, the input region of the three-region array unit is connected to the drain region or the source region of the MOS transistor, the input regions of the plurality of three-region array units are connected together as the total input terminal of the WAT test structure, the source regions or the drain regions of the plurality of MOS transistors are connected together as the total output terminal of the WAT test structure, and a MOS transistor switching voltage is applied to the gates of the plurality of MOS transistors.

[0017] As an alternative embodiment of the present invention, the three-region array unit is fabricated on a semiconductor substrate, and the three-region array unit is connected to the voltage detection array unit through a via structure; a heavily doped region of the first doping type is further formed between the input region and the via structure and between the output region and the via structure.

[0018] The present invention also provides a WAT test method, including the following steps:

[0019] Provide the WAT test structure as described in the present invention;

[0020] Apply the same voltage input signal to the input regions of multiple said three-region array units;

[0021] Judge that the number of PN junctions between the input region and the base region that have been turned on in multiple said three-region array units is m according to the current output signal;

[0022] The maximum spacing size among the m three-region array units with the smallest spacing size among multiple said three-region array units is the minimum estimated value of the depletion layer width; the maximum spacing size among the m + 1 three-region array units with the smallest spacing size among multiple said three-region array units is the maximum estimated value of the depletion layer width.

[0023] As described above, the present invention provides a WAT test structure and method, which set input regions and output regions with different spacing sizes, and judge the number of three-region array units in which the PN junctions have been turned on by applying the same voltage input signal and characterize the range of the depletion layer width of the PN junctions. Brief Description of the Drawings

[0024] Figure 1 Shown is a top view of a single three-region array unit in Embodiment 1 of the present invention.

[0025] Figure 2 Shown is a cross-sectional view of a single three-region array unit in Embodiment 1 of the present invention.

[0026] Figure 3 Shown is the WAT test structure composed of multiple three-region array units and multiple MOS transistors in Embodiment 1 of the present invention.

[0027] Description of Element Numbers

[0028] 100 Three-region array unit

[0029] 101 Semiconductor substrate

[0030] 102 Input region

[0031] 103 Output region

[0032] 104 Base region

[0033] 105 Via structure

[0034] 106 Heavily doped region

[0035] 107 Local oxidation of silicon isolation

[0036] 108 Interlayer dielectric layer

[0037] 200 MOS transistor Detailed implementation manners

[0038] The following describes the implementation manners of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. When detailing the embodiments of the present invention, for ease of description, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0039] For convenience of description, spatial relationship terms such as "beneath", "below", "lower than", "under", "above", "on" etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation, in addition to the directions depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0040] In the context of the present application, the structure in which the first feature is "above" the second feature described may include an embodiment where the first and second features are formed in direct contact, and may also include an embodiment where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0041] Please refer to Figures 1 to 3 Note that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Although only the components related to the present invention are shown in the illustrations and are not drawn according to the number, shape, and size of the components in actual implementation, the form, number, and ratio of each component in actual implementation can be arbitrarily changed, and the layout form of its components may also be more complex.

[0042] Embodiment 1

[0043] Please refer to Figures 1 to 3 , the present invention provides a WAT test structure, including:

[0044] Multiple three-region array units 100, the three-region array unit 100 includes an input region 102 and an output region 103 having a first doping type and a base region 104 having a second doping type; the base region 104 separates the input region 102 from the output region 103, and there are different interval sizes D between the input regions 102 and the output regions 103 of the multiple three-region array units 100; the input region 102 receives a voltage input signal, and the output region 103 outputs a voltage output signal;

[0045] Multiple voltage detection array units, the voltage detection array units correspond to the three-region array units 100 one by one, and the voltage detection array units receive the voltage output signal and output a corresponding current output signal according to the magnitude of the voltage output signal.

[0046] As an example, such as Figure 1 shown, is a top view of a single three-region array unit 100, and the three-region array unit 100 is fabricated on a semiconductor substrate 101. Figure 2 Is Figure 1 a cross-sectional view of the single three-region array unit 100 in Figure 3 is the WAT test structure composed of multiple three-region array units 100 and multiple MOS transistors 200.

[0047] As an example, the first doping type is N-type and the second doping type is P-type, or the first doping type is P-type and the second doping type is N-type.

[0048] In this embodiment, the first doping type is N-type and the second doping type is P-type, that is, the three-region array unit 100 is an NPN structure, and the MOS transistor is an NMOS transistor. In other embodiments of the present invention, it may also be that the first doping type is P-type and the second doping type is N-type, that is, the three-region array unit is a PNP structure, and the MOS transistor is a PMOS transistor. Such as Figure 1 shown, the semiconductor substrate 101 is a P-type substrate, the base region 104 is composed of a part of the P-type substrate, and the input region 102 and the output region 103 form an N-type doped region on the P-type substrate through a furnace tube diffusion process or an ion implantation process,. Specifically, the maximum value of the multiple different interval sizes D is the maximum predicted value of the depletion layer width of the PN junction between the input region and the base region, and the minimum value of the multiple different interval sizes D is the minimum predicted value of the depletion layer width of the PN junction between the input region and the base region. Such as Figure 3As shown, the number of the three - region array units is n, where n is an integer greater than 1. The multiple interval sizes form an arithmetic sequence, and the common difference is the difference between the maximum estimated value and the minimum estimated value of the depletion layer width divided by n - 1. For example, assuming that the approximate width range of the depletion layer is 1 - 2 μm, then the value range of the interval size D of the n three - region array units is 1 - 2 μm. Assuming that n is 11 in this embodiment, Figure 3 There are 11 three - region array units in total, such as S1 - S11. Then the common difference of the arithmetic sequence is 0.1 μm, and the values of its interval size D are 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, and 2 μm in sequence. In other embodiments of the present invention, the value range of the interval size D and the common difference of the arithmetic sequence can also be changed according to actual situations and experience.

[0049] As an example, as Figure 3 shown, in this embodiment, the voltage detection array unit is the MOS transistor 200. The source region and the drain region of the MOS transistor 200 have the first doping type, and the multiple MOS transistors 200 correspond to the multiple three - region array units 100 one by one.

[0050] As an example, as Figure 3 shown, the output region 103 of the three - region array unit 100 is connected to the gate of the MOS transistor. The input regions 102 of the multiple three - region array units 100 are connected together as the total input end of the WAT test structure. The source regions of the multiple MOS transistors 200 are connected together as the total output end of the WAT test structure, and a MOS transistor input voltage is applied to the drain regions of the multiple MOS transistors 200.

[0051] The present invention also provides a WAT test method, including the following steps:

[0052] Provide a WAT test structure as described in this embodiment;

[0053] Apply the same voltage input signal to the input regions 102 of the multiple three - region array units 100;

[0054] Judge that the number of PN junctions between the input region 102 and the base region 104 that are already conducting in the multiple three - region array units 100 is m according to the current output signal;

[0055] The maximum interval size D in the m three - region array units with the smallest interval size among the multiple three - region array units 100 is the minimum estimated value of the depletion layer width; the maximum interval size in the m + 1 three - region array units with the smallest interval size among the multiple three - region array units is the maximum estimated value of the depletion layer width.

[0056] Specifically, in Figure 3 , the input region 102 of the three-region array unit 100 is connected to the drain region of the MOS transistor 200, and the input voltage of the total input terminal of the WAT test structure serves as the input voltage of the MOS transistor at the same time. In other embodiments of the present invention, the input region and the drain region of the MOS transistor may also be connected to different input voltage sources. Assuming that the saturation current of the MOS transistor 200 is 5 mA, if the current output signal is 20 mA, it can be determined that the number of PN junctions between the input region 102 and the base region 104 that are already conducting in multiple three-region array units 100 is 4. That is, the PN junctions of the three-region array units 100 with the spacer sizes D taking values of 1 μm, 1.1 μm, 1.2 μm, and 1.3 μm in sequence are already conducting, and the actual depletion layer width ranges between 1.3 and 1.4 μm. In the NPN structure of this embodiment, the conduction of the reverse PN junction depends on its breakdown, and the breakdown of the PN junction is related not only to the electric field strength but also to the width of the space charge region. Under the same voltage condition, the depletion layer width in the reverse PN junctions of the three-region array units 100 with smaller spacer sizes D such as 1 μm, 1.1 μm, 1.2 μm, and 1.3 μm has reached their spacer size D, so they will conduct prior to the reverse PN junctions of other three-region array units. In the three-region array unit 100 with a spacer size D of 1.4 μm, the depletion layer width has not reached its spacer size D, and the reverse PN junction is not conducting, indicating that the depletion layer width is less than 1.4 μm. Therefore, the actual depletion layer width ranges between 1.3 and 1.4 μm. It should be noted that in this embodiment, the voltage detection array unit is the MOS transistor 200, which can give its corresponding current output signal according to the corresponding change of the voltage input signal with different spacer sizes. That is, in this embodiment, the MOS transistor 200 corresponding to the three-region array unit 100 that meets the condition that the depletion layer width reaches the spacer size D will output a saturation current signal, while the MOS transistors 200 corresponding to other three-region array units 100 will not output current signals. In other embodiments of the present invention, the voltage detection array unit may also select other possible device structures to give its corresponding current output signal according to the corresponding change of the voltage input signal with different spacer sizes.

[0057] As an example, such as Figure 2As shown, the three-region array unit 100 is fabricated on a semiconductor substrate 101, and the three-region array unit 100 is connected to the voltage detection array unit through a via structure 105; a heavily doped region 106 of the first doping type is also formed between the input region 102 and the via structure 105, and between the output region 103 and the via structure 105. Optionally, a local oxidation of silicon isolation 107 (LOCOS) is also formed in the surrounding regions of the input region 102 and the output region 103, and the via structure 105 is formed in an interlayer dielectric layer 108. In this embodiment, the three-region array unit 100 and the MOS transistor 200 can be integrated on the same semiconductor substrate 101. In other embodiments of the present invention, a zener diode can also be connected in parallel between the gate of the MOS transistor and the output region, so that the voltage of the input region can be adjusted to meet the requirements of continuous reading; the WAT test structure can continuously collect values under continuously changing voltages to further analyze the structural characteristics.

[0058] Embodiment 2

[0059] The WAT test structure provided in this embodiment is different from that in Embodiment 1 in that the input region of the three-region array unit is connected to the drain region or the source region of the MOS transistor, the input regions of multiple three-region array units are connected together as the total input terminal of the WAT test structure, the source regions or drain regions of multiple MOS transistors are connected together as the total output terminal of the WAT test structure, and a MOS transistor switching voltage is applied to the gates of multiple MOS transistors.

[0060] In this embodiment, the voltage detection array unit is a MOS transistor, and a corresponding current output signal is given according to the corresponding change of the voltage input signal with different interval sizes. That is, the MOS transistor corresponding to the three-region array unit when the depletion layer width reaches the interval size D will output a saturation current signal.

[0061] The other components and manufacturing methods of the WAT test structure provided in this embodiment are the same as those in Embodiment 1, and will not be elaborated here.

[0062] In summary, the present invention provides a WAT test structure and method. The WAT test structure includes: a plurality of three-region array units, where each three-region array unit includes an input region and an output region having a first doping type and a base region having a second doping type; the base region separates the input region from the output region, and different spacing sizes exist between the input regions and the output regions of the plurality of three-region array units; the input region receives a voltage input signal, and the output region outputs a voltage output signal; a plurality of voltage detection array units, which correspond to the three-region array units one by one, and each voltage detection array unit receives the voltage output signal and outputs a corresponding current output signal according to the magnitude of the voltage output signal. By setting the input region and the output region with different spacing sizes, the present invention determines the number of three-region array units in which the PN junction has been turned on by applying the same voltage input signal and characterizes the depletion layer width range of the PN junction.

[0063] The above embodiments merely illustrate the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A WAT test structure, characterized in that, Comprising: A plurality of three-region array units, each of the three-region array units including an input region and an output region having a first doping type and a base region having a second doping type; the base region separating the input region from the output region, and different spacing dimensions existing between the input regions and the output regions of the plurality of three-region array units; the input region receiving a voltage input signal, and the output region outputting a voltage output signal; A plurality of voltage detection array units, the voltage detection array units corresponding to the three-region array units one by one, the voltage detection array units receiving the voltage output signal and outputting a corresponding current output signal according to the magnitude of the voltage output signal; the current output signal being used to determine the number of PN junctions between the input region and the base region; Wherein, according to the current output signal, it is determined that the number of PN junctions between the input region and the base region that are conducting in the plurality of three-region array units is m; the maximum spacing dimension among the m three-region array units with the smallest spacing dimensions among the plurality of three-region array units is the estimated minimum value of the depletion layer width of the PN junction between the input region and the base region; the maximum spacing dimension among the m + 1 three-region array units with the smallest spacing dimensions among the plurality of three-region array units is the estimated maximum value of the depletion layer width.

2. The WAT test structure according to claim 1, wherein The first doping type is N-type and the second doping type is P-type, or the first doping type is P-type and the second doping type is N-type.

3. The WAT test structure according to claim 1, characterized in that, The maximum value of the plurality of different spacing dimensions is the maximum estimated value of the depletion layer width of the PN junction between the input region and the base region, and the minimum value of the plurality of different spacing dimensions is the minimum estimated value of the depletion layer width of the PN junction between the input region and the base region.

4. The WAT test structure according to claim 3, wherein, The number of the three-region array units is n, where n is an integer greater than 1, and the plurality of spacing dimensions form an arithmetic sequence, and its common difference is the difference between the maximum estimated value and the minimum estimated value of the depletion layer width divided by n - 1.

5. A WAT test structure according to claim 1, characterized in that, The voltage detection array unit is a MOS transistor, and the source region and the drain region of the MOS transistor have a first doping type, and the plurality of MOS transistors correspond to the plurality of three-region array units one by one.

6. The WAT test structure according to claim 5, characterized in that, The output region of the three-region array unit is connected to the gate of the MOS transistor, the input regions of the plurality of three-region array units are connected together as the total input terminal of the WAT test structure, the source regions of the plurality of MOS transistors are connected together as the total output terminal of the WAT test structure, and a MOS transistor input voltage is applied to the drain regions of the plurality of MOS transistors.

7. The WAT test structure according to claim 6, wherein The input region of the three-region array unit is connected to the drain region of the MOS transistor, and the input voltage of the total input terminal of the WAT test structure serves as the MOS transistor input voltage at the same time.

8. A WAT test structure according to claim 5, wherein The input region of the three-region array unit is connected to the drain region or the source region of the MOS transistor, the input regions of the plurality of three-region array units are connected together as the total input terminal of the WAT test structure, the source regions or the drain regions of the plurality of MOS transistors are connected together as the total output terminal of the WAT test structure, and a MOS transistor switching voltage is applied to the gates of the plurality of MOS transistors.

9. The WAT test structure according to claim 1, characterized in that, The three-region array unit is fabricated on a semiconductor substrate, and the three-region array unit is connected to the voltage detection array unit through a via structure; a heavily doped region of the first doping type is further formed between the input region and the via structure, and between the output region and the via structure.

10. A WAT test method, characterized in that, The method includes the following steps: Providing a WAT test structure according to any one of claims 1 to 9; Applying the same voltage input signal to the input regions of a plurality of the three-region array units; Judging, according to the current output signal, that the number of PN junctions between the input regions and the bases that are turned on in a plurality of the three-region array units is m; The maximum interval size among the m three-region array units with the smallest interval sizes among a plurality of the three-region array units is the estimated minimum value of the depletion layer width of the PN junction between the input region and the base; the maximum interval size among the m + 1 three-region array units with the smallest interval sizes among a plurality of the three-region array units is the estimated maximum value of the depletion layer width.

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