Cross-power domain electrostatic discharge protection circuit

Abstract

The present invention discloses a cross-power domain electrostatic discharge protection circuit, wherein a clamping circuit 1 is connected between VDD1 and VSS1, a device SCR1 is connected between VDD1 and VSS2, the anode of SCR1 is connected to VDD1, the cathode of SCR1 is connected to VSS2, and the P well of SCR1 is connected to VSS1; a clamping circuit 2 is connected between VDD2 and VSS2, a device SCR2 is connected between VDD2 and VSS2, the anode of SCR2 is connected to VDD2, the cathode of SCR2 is connected to VSS1, and the P well of SCR2 is connected to VSS2. The structure of the present invention only needs to expand the isolation diode in the traditional solution into an SCR device and make appropriate connections, the increased layout area is small, the expanded SCR device can be formed by the most basic structure, and no additional trigger circuit is required.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit electrostatic discharge (ESD) protection, and relates to a cross-power domain electrostatic discharge protection circuit. Background Art

[0002] With the rapid development of the integrated circuit industry, the characteristic size of components is constantly decreasing, the oxide layer is getting thinner and thinner, and the integrated circuit components are becoming more and more sensitive to electrostatic discharge, causing a large number of integrated circuits to fail due to ESD events. Among them, the ESD design across power domains is a difficult point. This is mainly because the ground lines of different power domains often need to be isolated by diodes to reduce the crosstalk caused by noise in different power domains. However, when an ESD event occurs between different power domains, the presence of the above-mentioned isolation diode increases a part of the voltage drop, resulting in a higher terminal voltage and the integrated circuit is more easily damaged. Therefore, it is necessary to design a new type of cross-power domain ESD protection circuit to adapt to the development of the integrated circuit industry.

[0003] The typical circuit block diagram with isolated power domain is as follows: Figure 1 As shown, power domain 1 generates an output signal and sends it to receiving end B of power domain 2. When discharge occurs from the power line VDD1 of power domain 1 to the ground line VSS2 of power domain 2, the ESD current flows from VDD1 into the clamp circuit A, flows through the ground line VSS1 into the isolation diode D1, and then flows into the ground through the ground line VSS2. In this process, since the internal circuit A is in an abnormal working state, the voltage of node A is in an unstable state, which often causes the PMOS field effect transistor Mpa to turn on, so that the voltage of node B is pulled up to VDD1 (ignoring the wire voltage drop). At this time, the voltage between the gate and source of the NMOS field effect transistor Mnb is VDD1, which is the largest in the entire circuit, making Mnb the device most likely to fail. Since the ESD protection path at this time is composed of the clamp circuit A and the diode D1 in series, the total terminal voltage is large, which further increases the possibility of Mnb failure [1]. This ESD event of mutual discharge between the power line of one power domain and the ground line of another power domain is one of the most threatening situations in the cross-power domain ESD category. The present invention will provide a solution to this problem.

[0004] Silicon controlled rectifier (SCR) can be used as an ESD protection device. It forms a positive feedback conductive path based on parasitic cross-coupled bipolar transistors and has a high discharge capability. In Figure 19 of reference [1], a cross-power domain protection design based on SCR is proposed. An SCR device triggered by an N-type field effect transistor is set between VDD1 and VSS2, and the gate of the N-type field effect transistor is connected to VSS1. When discharge from VDD1 to VSS2 occurs, the voltage divider on the isolation diode turns on the NMOS transistor, and then triggers the SCR positive feedback conductive path. This design ensures that the discharge path from VDD1 to VSS2 becomes an SCR device, which improves the cross-power domain ESD discharge efficiency compared to the traditional discharge path consisting of a clamp circuit and a diode in series. References [2] and [3] proposed different SCR-based cross-power domain ESD protection designs. Compared with reference [1], references [2] and [3] also formed an SCR discharge path between one power line and another ground line, thereby improving the cross-power domain ESD discharge efficiency. In addition, the solutions proposed in references [2] and [3] reduce the layout area because their respective protection paths in the two power domains (i.e., VDD1-VSS1 and VDD2-VSS2) also use SCR devices instead of traditional clamping circuits, and are nested with the cross-power domain protection path. However, the disadvantage of this design is that the series length of some discharge paths is relatively large, such as the Figure 3 In the SCR path that discharges from VDD1 to VSS2, the N-well region is relatively long and the series resistance is large, which is not conducive to fast conduction under ESD events. In addition, this design requires major changes to the original design, which brings additional design costs. Summary of the invention

[0005] The purpose of the present invention is to provide a cross-power domain electrostatic discharge protection circuit, which solves the problems of weak cross-power domain ESD protection capability and complex design in the prior art.

[0006] The technical solution adopted by the present invention is a cross-power domain electrostatic discharge protection circuit, wherein a clamping circuit 1 is connected between VDD1 and VSS1, a device SCR1 is connected between VDD1 and VSS2, an anode of SCR1 is connected to VDD1, a cathode of SCR1 is connected to VSS2, and a P-well of SCR1 is connected to VSS1; a clamping circuit 2 is connected between VDD2 and VSS2, a device SCR2 is connected between VDD2 and VSS2, an anode of SCR2 is connected to VDD2, a cathode of SCR2 is connected to VSS1, and a P-well of SCR2 is connected to VSS2.

[0007] The cross-power domain electrostatic discharge protection circuit of the present invention is also characterized in that:

[0008] The structures of the clamping circuit 1 and the clamping circuit 2 are consistent, and the structures of the device SCR1 and the device SCR2 are consistent.

[0009] The clamping circuit 1 includes an RC network, an inverter and a discharge tube, wherein the RC network is composed of a capacitor C1 and a resistor R1, one end of the capacitor C1 is connected to VSS1, the other end of the capacitor C1 is connected to the resistor R1, and the other end of the resistor R1 is connected to VDD1; the common connection point of the capacitor C1 and the resistor R1 is used as the output signal CLK of the RC detection; the inverter is composed of an N-type field effect transistor Mn1 and a P-type field effect transistor Mp1, the source of the N-type field effect transistor Mn1 is connected to VSS1, and the gate is connected to the output signal C of the RC detection LK is connected, and the drain is connected to the drain of the P-type field effect transistor Mp1; the source of the P-type field effect transistor is connected to VDD1, the gate is connected to the output signal CLK of the RC detection, and the drain is connected to the drain of the N-type field effect transistor Mn1; the common connection point of the drain of the N-type field effect transistor Mn1 and the P-type field effect transistor Mp1 serves as the output end of the inverter, and the output end is connected to the gate of the N-type field effect transistor Mc1, the source of the N-type field effect transistor Mc1 is connected to VSS1, and the drain of the N-type field effect transistor Mc1 is connected to VDD1.

[0010] The cross-sectional structure of the SCR1 is as follows: it includes a P substrate, an N well and a P well are arranged side by side on the upper surface of the P substrate, a first N+ injection region, a first groove, a first P+ injection region, and a part of a second groove are arranged in sequence on the upper surface of the N well in the lateral direction; another part of the second groove, a second N+ injection region, a third groove, and a second P+ injection region are arranged in sequence on the upper surface of the P well; the first N+ injection region and the first P+ injection region are both connected to VDD1 externally, the second N+ injection region is connected to VSS2 externally, and the second P+ injection region is connected to VSS1 externally.

[0011] The first P+ injection region, N well, P well and second N+ injection region together constitute a positive feedback discharge path in the SCR device; the second P+ injection region, P well and second N+ injection region together constitute a diode D1.

[0012] The beneficial effect of the present invention is that when an ESD event occurs in which discharge occurs from a power line of one power domain to a ground line of another power domain, the clamping circuit and the isolation diode series branch will be turned on first, and the conduction of the SCR positive feedback path will be quickly triggered, thereby achieving efficient discharge from a power line of one power domain to a ground line of another power domain. At the same time, the design complexity and circuit cost of the present invention are very low. It only needs to expand the isolation diode in the traditional solution into an SCR device and make appropriate connections. The increased layout area is small, and the expanded SCR device can be composed of the most basic structure, and no additional trigger circuit is required. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a cross-power domain ESD protection circuit diagram of the prior art;

[0014] Figure 2 It is a schematic diagram of discharge from a power line of one power domain to a ground line of another power domain in a cross-power domain ESD protection circuit of the prior art;

[0015] Figure 3 is a circuit diagram of a protection circuit of the present invention;

[0016] Figure 4 It is a device cross-sectional view of SCR1 in the protection circuit of the present invention.

[0017] In the figure, 1. P substrate, 2. N well, 3. P well, 4. first N+ injection region, 5. first trench, 6. first P+ injection region, 7. second trench, 8. second N+ injection region, 9. third trench, 10. second P+ injection region, 11. clamping circuit one, 12. clamping circuit two. DETAILED DESCRIPTION

[0018] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] Reference Figure 1, is a cross-power domain ESD protection circuit structure of the prior art, wherein a clamping circuit A, an internal circuit A, and a series branch of an N-type field effect transistor Mna and a P-type field effect transistor Mpa are connected between VDD1 and VSS1, and the gate of the N-type field effect transistor Mna and the gate of the P-type field effect transistor Mpa are connected to the output signal of the internal circuit A; at the same time, a clamping circuit B, an internal circuit B, and a series branch of an N-type field effect transistor Mnb and a P-type field effect transistor Mpb are connected between VDD2 and VSS2, and a connection point B between the gate of the N-type field effect transistor Mnb and the gate of the P-type field effect transistor Mpb is connected to the output signal of the common connection point of the N-type field effect transistor Mnb and the P-type field effect transistor Mpb; in addition, anti-parallel diodes D1 and D2 branches are arranged between VSS1 and VSS2.

[0020] Reference Figure 2 In the process of discharging from the power line of one power domain to the ground line of another power domain in the cross-power domain ESD protection circuit of the prior art, its shortcomings refer to the relevant description in the background technology.

[0021] The innovative structure of the present invention is that, based on the above structure, the original clamping circuits of the respective power domains are kept unchanged, the diodes used for isolation are expanded into SCRs, and connected between the power line of one power domain and the ground line of another power domain. When ESD discharges, the clamping circuit is first turned on and acts as a substrate trigger, so that the SCR device is quickly turned on, and a direct discharge path from the power line of one power domain to the ground line of another power domain is realized, that is, the discharge path is shortened and the terminal voltage is reduced, thereby reducing the risk of device breakdown. The technical solution includes: a clamping circuit 11 is arranged between VDD1 and VSS1, a clamping circuit 2 12 is arranged between VDD2 and VSS2, SCR1 is arranged between VDD1 and VSS2, and SCR2 is arranged between VDD2 and VSS1; the P well area of ​​SCR1 is connected to VSS1, and the P well area of ​​SCR2 is connected to VSS2.

[0022] Reference Figure 3 The specific structure of the protection circuit of the present invention is: a clamp circuit 11 is connected between VDD1 and VSS1, a device SCR1 is connected between VDD1 and VSS2, the anode of SCR1 is connected to VDD1, the cathode of SCR1 is connected to VSS2, and the P well of SCR1 is connected to VSS1; a clamp circuit 2 12 is connected between VDD2 and VSS2, a device SCR2 is connected between VDD2 and VSS2, the anode of SCR2 is connected to VDD2, the cathode of SCR2 is connected to VSS1, and the P well of SCR2 is connected to VSS2; the structure of the clamp circuit 11 is consistent with that of the clamp circuit 2 12, and the structure of the device SCR1 is consistent with that of the device SCR2.

[0023] The following description is made by taking the discharge from VDD1 to VSS2 as an example. The clamping circuit 11 is constructed in a common form, including an RC network, an inverter and a discharge tube.

[0024] The RC network is composed of a capacitor C1 and a resistor R1, one end of the capacitor C1 is connected to VSS1, the other end of the capacitor C1 is connected to the resistor R1, and the other end of the resistor R1 is connected to VDD1; the common connection point of the capacitor C1 and the resistor R1 is used as the output signal CLK of the RC detection;

[0025] The inverter is composed of an N-type field effect transistor Mn1 and a P-type field effect transistor Mp1, and the discharge tube adopts an N-type field effect transistor Mc1, wherein the source of the N-type field effect transistor Mn1 is connected to VSS1, the gate is connected to the output signal CLK of RC detection, and the drain is connected to the drain of the P-type field effect transistor Mp1; the source of the P-type field effect transistor Mp1 is connected to VDD1, the gate is connected to the output signal CLK of RC detection, and the drain is connected to the drain of the N-type field effect transistor Mn1; the common connection point of the drain of the N-type field effect transistor Mn1 and the P-type field effect transistor Mp1 serves as the output end of the inverter, and the output end is connected to the gate of the N-type field effect transistor Mc1, the source of the N-type field effect transistor Mc1 is connected to VSS1, and the drain of the N-type field effect transistor Mc1 is connected to VDD1.

[0026] Reference Figure 4 The cross-sectional structure of the SCR1 in the protection circuit of the present invention is as follows: it comprises a P substrate 1, an N well 2 and a P well 3 are arranged side by side on the upper surface of the P substrate 1, a first N+ injection region 4, a first groove 5, a first P+ injection region 6, and a part of a second groove 7 are arranged in sequence on the upper surface of the N well 2 in a lateral direction; another part of the second groove 7, a second N+ injection region 8, a third groove 9, and a second P+ injection region 10 are arranged in sequence on the upper surface of the P well 3; the first N+ injection region 4 and the first P+ injection region 6 are both connected to VDD1 externally, the second N+ injection region 8 is connected to VSS2 externally, and the second P+ injection region 10 is connected to VSS1 externally.

[0027] The above three trenches are all oxides for isolating different heavily doped (i.e., N+, P+) implanted regions, and their materials are all silicon dioxide. The first trench 5 is used to isolate the first N+ implanted region 4 from the first P+ implanted region 6, the second trench 7 is used to isolate the first P+ implanted region 6 from the second N+ implanted region 8, and the third trench 9 is used to isolate the second N+ implanted region 8 from the second P+ implanted region 10.

[0028] The essence of the above structure includes the following three points:

[0029] 1) The first P+ injection region 6, the N-well 2, the P-well 3 and the second N+ injection region 8 together constitute a positive feedback discharge path in the SCR device; the second P+ injection region 10, the P-well 3 and the second N+ injection region 8 together constitute a diode D1; the N-well 2 is connected to the first N+ injection region 4 to connect the potential of the N-well 2 to the power supply, and the P-well 3 is connected to the second P+ injection region 10 to connect the potential of the P-well 3 to the ground.

[0030] 2) The first P+ injection region 6, the N well 2 and the P well 3 form a PNP bipolar transistor, while the N well 2, the P well 3 and the second N+ injection region 8 form an NPN bipolar transistor. The above two bipolar transistors are cross-coupled to form a parasitic positive feedback path, which serves as the main discharge path of the SCR device in the present invention under ESD events.

[0031] 3) Diode D1 is the base-emitter of the NPN bipolar transistor. When an ESD event occurs across the power domain, diode D1 will first conduct forward, causing the NPN bipolar transistor to conduct quickly, and then establish positive feedback conduction of the SCR to discharge current.

[0032] The working principle of the protection circuit of the present invention is:

[0033] When an ESD discharge event occurs (ESD current flows from VDD1 and flows out of VSS2), the VDD1 voltage rises rapidly, the RC network in the clamp circuit 11 responds, the CLK signal is low, the inverter output level is high, and the discharge tube Mc1 is turned on. Therefore, the ESD current flows from VDD1 to VSS1 through Mc1, and then flows into VSS2 through diode D1. As the D1 diode is turned on, the base-emitter junction of the NPN bipolar transistor in the SCR1 device is forward biased, thereby quickly establishing the SCR positive feedback conduction to discharge current. That is, the clamp circuit 11 plays the role of substrate triggering, accelerating the establishment of the SCR positive feedback conduction [4].

[0034] Compared with the solution in FIG. 19 in document [1], the protection circuit of the present invention has two advantages:

[0035] 1) The layout area is smaller. This is because the SCR device constructed in the present invention utilizes the existing isolation diode, that is, the isolation diode is nested in the SCR device, while the SCR and the isolation diode in the document [1] are independent of each other.

[0036] 2) Under an ESD event, the substrate trigger current received by the SCR device in the present invention is the entire ESD current, that is, near the triggering moment, the entire ESD current flows into the isolation diode, while the substrate trigger current received by the SCR in the literature is provided by a path composed of its own anode diode and NMOS transistor, which is obviously only a part of the total ESD current, and another part of the current flows out through the clamping circuit and the isolation diode. Therefore, the SCR device in the present invention is turned on faster.

[0037] Compared with the solutions in references [2] and [3], the protection circuit of the present invention has a simple circuit structure, a shorter N-well length in the SCR device, and a higher discharge efficiency, as described in the background technology section.

[0038] In summary, the cross-power domain ESD protection circuit of the present invention has the characteristics of simple design and high discharge efficiency.

[0039] References:

[0040] [1]M.Okushima.ESD Protection Design for Mixed-Power Domains in 90nmCMOS with New Efficient Power Clamp and GND Current Trigger(GCT)Technique.Electrical Overstress / Electrostatic Discharge Symposium,2006.

[0041] [2] Federico A. Altolaguirre, Ming-Dou Ker. Quad-SCR Device for Cross-Domain ESD Protection. IEEE Transactions on Electron Devices, 2016.

[0042] [3]Jie-Ting Chen,Ming-Dou Ker.ESD Protection Design With Diode-Triggered Quad-SCR for Separated Power Domain.IEEE Transactions on Device andMaterials Reliability.2019.

[0043] [4]M.-D.Ker and K.-C.Hsu,Substrate-triggered SCR device for on-chipESD protection in fully silicided sub-0.25-μm CMOS process,IEEETrans.Electron Devices,2003.

Claims

1. A cross-power domain electrostatic discharge protection circuit, characterized in that: A clamping circuit 1 (11) is connected between VDD1 and VSS1, a device SCR1 is connected between VDD1 and VSS2, an anode of SCR1 is connected to VDD1, a cathode of SCR1 is connected to VSS2, and a P-well of SCR1 is connected to VSS1; a clamping circuit 2 (12) is connected between VDD2 and VSS2, a device SCR2 is connected between VDD2 and VSS2, an anode of SCR2 is connected to VDD2, a cathode of SCR2 is connected to VSS1, and a P-well of SCR2 is connected to VSS2.

2. The cross-power domain electrostatic discharge protection circuit according to claim 1, characterized in that: The structures of the clamping circuit 1 (11) and the clamping circuit 2 (12) are consistent, and the structures of the device SCR1 and the device SCR2 are consistent.

3. The cross-power domain electrostatic discharge protection circuit according to claim 2, characterized in that: The clamping circuit 1 (11) comprises an RC network, an inverter and a discharge tube. The RC network is composed of a capacitor C1 and a resistor R1, one end of the capacitor C1 is connected to VSS1, the other end of the capacitor C1 is connected to the resistor R1, and the other end of the resistor R1 is connected to VDD1; the common connection point of the capacitor C1 and the resistor R1 is used as the output signal CLK of the RC detection; The inverter is composed of an N-type field effect transistor Mn1 and a P-type field effect transistor Mp1. The discharge tube adopts an N-type field effect transistor Mc1. The source of the N-type field effect transistor Mn1 is connected to VSS1, the gate is connected to the output signal CLK of RC detection, and the drain is connected to the drain of the P-type field effect transistor Mp1; the source of the P-type field effect transistor is connected to VDD1, the gate is connected to the output signal CLK of RC detection, and the drain is connected to the drain of the N-type field effect transistor Mn1; the common connection point of the drain of the N-type field effect transistor Mn1 and the P-type field effect transistor Mp1 serves as the output end of the inverter, and the output end is connected to the gate of the N-type field effect transistor Mc1, the source of the N-type field effect transistor Mc1 is connected to VSS1, and the drain of the N-type field effect transistor Mc1 is connected to VDD1.

4. The cross-power domain electrostatic discharge protection circuit according to claim 2, characterized in that: The cross-sectional structure of the SCR1 is as follows: it comprises a P substrate (1), an N well (2) and a P well (3) are arranged side by side on the upper surface of the P substrate (1), a first N+ injection region (4), a first groove (5), a first P+ injection region (6), and a part of a second groove (7) are arranged in sequence on the upper surface of the N well (2) in a lateral direction; another part of the second groove (7), a second N+ injection region (8), a third groove (9), and a second P+ injection region (10) are arranged in sequence on the upper surface of the P well (3); the first N+ injection region (4) and the first P+ injection region (6) are both externally connected to VDD1, the second N+ injection region (8) is externally connected to VSS2, and the second P+ injection region (10) is externally connected to VSS1.

5. The cross-power domain electrostatic discharge protection circuit according to claim 4, characterized in that: The first P+ injection region (6), the N well (2), the P well (3) and the second N+ injection region (8) together constitute a positive feedback discharge path in the SCR device; The second P+ implantation region (10), the P well (3) and the second N+ implantation region (8) together form a diode D1.

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